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WritePhi Study — Library + IC Designs Blueprint
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
WritePhi Library — The SDK + 5 Reference ICs That Make Design Real
This is where custom silicon becomes practical. The Library ships a Python SDK that compiles design intent into .wpprog bytecode, plus 5 fully-working reference IC designs you can build today.
What's In The Zip
The Python SDK (writephi.design module)
- HDL-like abstractions: logic gates, flip-flops, memories (SRAM cells), arithmetic blocks (adders, multipliers), state machines
- Grade constraints: M-grade (max ~500 transistors, 800 nm process) vs H-grade (max ~3,500 transistors, 300 nm process); enforced at compile time so you can't ship an oversized design
- .wpprog compiler: Outputs mask data + layer stack instructions for the Writer
- Simulator: Cycle-accurate simulation before you burn a die
- Test bench framework: Waveform generation, expected-output checking, coverage reports
5 Native Reference ICs (Each Fully Working)
- WPIC-INVERT-01: Logic inverter chain (27 transistors, M-grade). Simplest possible design. Great teaching example.
- WPIC-UART-01: 8-bit serial UART transceiver (300 transistors, M-grade). Baud rate 9600-115200. Configurable stop bits, parity. Full state machine.
- WPIC-PWM-01: 8-channel PWM controller (480 transistors, M-grade). 16-bit resolution per channel. SPI configuration interface. Use case: LED drivers, motor control.
- WPIC-SPI-DAC-01: 4-channel 12-bit SPI DAC (906 transistors, H-grade). 1 MS/s per channel. Reference-voltage input. Ideal for waveform generation, sensor calibration.
- WPIC-AES-CORE: AES-128 cipher engine (3,160 transistors, H-grade). Encrypts one 128-bit block in 200 cycles. This proves WritePhi can do real crypto compute.
Reference Carrier Board
- RP2040 microcontroller as host
- WritePhi-PKG-H socket (accepts H-grade dies)
- 4× SMA outputs for RF/analog testing
- USB-C connection to PC
- Full schematic, PCB layout, BOM, assembly guide
- Software: Python + MicroPython examples for driving each reference IC
Documentation
- SDK_REFERENCE.md — Every function, every abstraction, with examples
- DESIGN_GUIDE.md — How to think about WritePhi designs (grade budget, timing constraints, power)
- PORTING_GUIDE.md — How to port existing Verilog designs to WritePhi SDK
- PERFORMANCE_BENCHMARKS.md — Actual measured performance of each reference IC
- LICENSE.md, HANDOFF.md, CONTACT_INFO.txt
Why This Toolkit Matters
Commercial ASIC design tools cost $50k-500k/seat/year (Cadence, Synopsys, Mentor). The WritePhi SDK is free with this package and generates production-quality designs. The 5 reference ICs are proof that the SDK works.
The AES-CORE is particularly notable: a full AES-128 cipher in 3,160 transistors. Comparable standard-cell ASIC implementations use 15,000-20,000 transistors. WritePhi's density advantage comes from custom analog cells optimized for the substrate's specific chemistry.
Your Work
- Learn SDK: 1-2 days for a competent Python + hardware engineer
- Design your own IC: 1-4 weeks depending on complexity
- Simulate: Built-in simulator; run test benches to verify functionality
- Compile: One command produces .wpprog output
- Write: Load .wpprog onto Writer, expose blank, get die
- Package: Send diced die through PKG or V2 packaging
- Test: Use reference carrier or your own PCB
Timeline
- SDK familiarization: 1-2 days
- Port simple design (~100 transistors): 3-5 days
- Port complex design (~1000+ transistors): 2-6 weeks
- Reference carrier PCB assembly: 1 week (if you order the board)
License (Study Tier)
✅ Use SDK for research, publish papers, copy reference ICs freely. ❌ Sell custom ICs commercially. Upgrade: WRITEPHI-COMMERCIAL ($24,999) grants right to sell your custom silicon.
Portfolio conversation — WritePhi (Project 57) + WritePhi Devices (Project 58)
These two product families are one continuous story in two chapters, not unrelated store listings. WritePhi (Project 57) is the kitchen-table fabrication layer: Writer → Blank → Dicer → PKG → Chassis → Library makes replaceable WritePhi dies at the bench. WritePhi Devices / WPD (Project 58) is the deployment layer for those same dies: the V2 inset package (carried forward from WRITEPHI-PKG and cut geometry from WRITEPHI-DICER) drops into pinned sockets on a reference PCIe 5.0 card, where Windows-facing CSD and ACCEL personas plus on-card firmware turn a homemade die into a plug-and-play host peripheral.
If you are buying on this page, you are in the make chapter. An OEM or power user who completes the 57 pipeline and wants volume-manufacturable packaging plus a Windows card stack continues in the run chapter — browse WritePhi Devices (WPD) on the same store. Neither family requires the other to be useful alone; together they describe the full path from blank substrate to installed Windows accelerator.
Fulfillment: Instant download after checkout. SHA-256 checksum published for integrity verification.
Region: USA-only (nginx geoblocking enforced). International buyers: contact us for special licensing.
Currency: USD only. Sub-$10k via standard checkout (Stripe). Over $10k: Term Sheet financing available.
Support: crioneaka@outlook.com | Christopher Gabriel Brown, Inventor | 24-48hr response.
Chris's philosophy: Every design engineered by hand. If it's specced, it works. If it has limits, we say so.
© 2026 Christopher Gabriel Brown · cri-one.com · Patent-pending inventions
