WPD Study — Reference Cards Blueprint

WPD Reference Cards — PCIe 5.0 Add-In Card, Two Personas

This is where WritePhi meets standard PC hardware. A PCIe 5.0 x8 add-in card with 4 V2 sockets and an AutoPhi 1Z-Edge bus master. Strap a resistor differently, get a different device: WPD-CSD (NVMe storage + Computational Programs) or WPD-ACCEL (compute accelerator with DirectML backend).

Card Architecture

• Form factor: PCIe 5.0 x8 add-in card, full-height half-length (109 × 111 mm)
• Bus interface: PCIe 5.0 x8 (32 GT/s per lane, 32 GB/s aggregate)
• Bus master: AutoPhi 1Z-Edge (Chris's own chip, from AutoPhi portfolio)
• Sockets: 4× V2 sockets (accepts M-grade or H-grade dies)
• Memory: DDR4 buffer (typically 2-4 GB) for CSD cache or ACCEL working memory
• Boot flash: NOR flash for persona firmware (CSD vs ACCEL selection)
• Power: 75W from PCIe slot + 6-pin auxiliary connector
• Cooling: Passive heatsink (default) or optional axial fan

The Two-Persona Design

WPD-CSD (Computational Storage Device) Persona

• Card enumerates as NVMe 2.0 storage device
• Uses Windows in-box stornvme.sys driver (no custom driver needed)
• Computational Programs extension (NVMe 2.0 feature): host can query on-device WritePhi ICs as NVMe namespaces
• Ideal for: on-device data processing, encrypted storage with hardware crypto, filter offload

WPD-ACCEL (Compute Accelerator) Persona

• Card enumerates as generic PCIe device (Vendor ID: cri-one)
• Requires custom KMDF driver (wpd_accel.sys)
• DirectML backend integration for GPU-agnostic ML workloads
• MMIO command queues for host-to-device job submission
• Ideal for: on-device inference (ML models compiled to WritePhi ICs), custom compute (crypto, signal processing)

Persona Selection

Two solder-jumper resistors (R1 and R2) select the persona at boot:

• R1 populated, R2 empty: CSD persona
• R1 empty, R2 populated: ACCEL persona
• Both populated: Default to CSD (safer)
• Both empty: Fault mode (LED indicator)

What's In The Zip

• PCIe_CARD_SPEC.md — Master spec: form factor, power delivery, cooling, connector pinouts, host system requirements
• BUS_MASTER_SCHEMATIC.kicad_sch — 1Z-Edge + DDR4 + NOR flash + PCIe interface. All pins wired, all decoupling shown, all impedance-controlled traces marked.
• SOCKET_INTERFACE.kicad_sch — 4× V2 sockets with independent PCIe Gen4 x2 links to the bus master (8 GB/s per socket)
• PERSONA_STRAP.kicad_sch — R1/R2 strap resistor circuit + boot-time detection logic
• THERMAL_ANALYSIS.pdf — CFD simulation: heat map at 75W dissipation, worst-case junction temp (72°C at 40°C ambient), airflow requirements for optional fan
• INSET_PCB_M.kicad_sch — Reference INSET-PCB-M carrier (also included in WPD-STUDY-V2, bundled here for context)
• FIRMWARE_LOADER.c — Boots 1Z-Edge, reads strap resistors, loads CSD or ACCEL persona firmware from NOR flash
• BOM.csv — Full BOM with vendor part numbers (Digikey, Mouser, Avnet)
• PCB_LAYOUT_HINTS.md — Length matching (±10 mils), impedance control (100 Ω differential, 50 Ω single-ended), power plane design, decoupling capacitor placement
• LICENSE.md, HANDOFF.md, CONTACT_INFO.txt

Why PCIe 5.0 (Not 4.0)?

• Bandwidth: WritePhi ICs can generate/consume ~4 GB/s per die. With 4 sockets, aggregate 16 GB/s. PCIe 4.0 x8 = 16 GB/s (bottlenecked). PCIe 5.0 x8 = 32 GB/s (comfortable headroom).
• Future-proofing: PCIe 5.0 is the current-gen standard (2022+). Cards will remain relevant for 5-7 years.
• Backwards compatibility: PCIe 5.0 cards work in PCIe 4.0 or 3.0 slots at reduced speed.

Your Work

1. PCB layout: Impedance-controlled 12-layer stackup, Megtron 6 dielectric. Requires HSD-experienced PCB engineer (~40-80 hours, $6k-15k)
2. Fab: Sanmina, TTM, or Multek. ~$3-8k for 5 prototypes.
3. Assembly: Contract EMS (Sanmina, Jabil, or smaller shops) or manual assembly. ~$2-5k for 5 prototypes.
4. Bring-up: PCIe link training, memory training (DDR4), firmware boot. Budget 2-4 weeks.
5. Certification: FCC Part 15 Class B (~$3-5k), PCI-SIG electrical + protocol compliance ($2-5k), WHCP for Windows drivers (~$5-10k)

Timeline

• Schematic capture from reference: 2-3 weeks
• PCB layout: 4-8 weeks
• Fab + assembly: 5-8 weeks
• Bring-up: 2-4 weeks
• Firmware integration: 4-8 weeks (depends on persona choice)
• Certification: 4-8 weeks
• Total to first shippable card: 5-8 months

License (Study Tier)

✅ Build cards for research/lab use. ❌ Sell cards commercially. Upgrade: WPD-COMMERCIAL ($49,999).

Portfolio conversation — WritePhi Devices (Project 58) + WritePhi (Project 57)

WPD does not exist in isolation. It is the Windows host deployment half of the same portfolio conversation that begins in WritePhi (Project 57). Project 57's kitchen-table pipeline — Writer, Blank, Dicer, PKG socket-BGA, Chassis bed, and reference IC library — fabricates the M-grade and H-grade WritePhi dies that this card's four pinned sockets accept. The V2 package blueprint here is an explicit production-scale extension of 57's PKG plus additional cut marks and tabs that WRITEPHI-DICER executes in the same dicing pass.

If you are buying on this page, you are in the run chapter: PCIe card reference designs, persona firmware, and Windows driver plans. Makers who need to produce the dies themselves start in the make chapter — browse WritePhi (Project 57). Either half stands alone for study or commercial licensing; both halves together narrate bench fabrication through installed Windows compute.

Fulfillment: Instant download after checkout. SHA-256 checksum published for integrity verification.

Region: USA-only (nginx geoblocking enforced). International buyers: contact us for special licensing.

Currency: USD only. Sub-$10k via standard checkout (Stripe). Over $10k: Term Sheet financing available.

Support: crioneaka@outlook.com | Christopher Gabriel Brown, Inventor | 24-48hr response.

Chris's philosophy: Every design engineered by hand. If it's specced, it works. If it has limits, we say so.

© 2026 Christopher Gabriel Brown · cri-one.com · Patent-pending inventions