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WritePhi Study — Chassis Blueprint
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
WritePhi Chassis — The Platform That Runs Multiple Dies in Parallel
Now you have packaged dies. The Chassis is the platform that holds 4, 8, or 16 sockets and routes them over a PCIe 5.0 x8 bus with an AutoPhi 1Z-Edge bus master running the show. This is the multi-die compute platform.
Two Form Factors
- CHASSIS-BOX: Standalone enclosure (rack-mount 1U or desktop), integrated power supply, cooling, front-panel LCD, USB-C or Ethernet host connection. 4/8/16-socket variants. Best for lab/research.
- CHASSIS-CARD: PCIe 5.0 x8 (or x16) add-in card for standard PC. 4-socket variant. Best for OEM/embedded integration.
What's In The Zip
- CHASSIS_BOX_SPEC.md — Standalone spec: mechanical (1U rack, EIA-310 compliant), thermal (200W total budget), power (48V DC input, converted to 12V/5V/3.3V rails), host connection (USB-C 3.2 Gen 2×2 or 10 GbE)
- CHASSIS_CARD_SPEC.md — Add-in card spec: PCIe 5.0 x8 form factor (109 × 111 mm full-height half-length), 75W power budget from PCIe slot + 6-pin aux, thermal solution (heatsink + optional fan)
- BUS_ARCHITECTURE.md — Star topology: 1Z-Edge master with 4/8/16 point-to-point PCIe links (Gen4 x2 per socket = 4 GB/s per die). Hyperthreading enables concurrent access across multiple sockets.
- PCIe_BACKPLANE_SCHEMATIC.kicad_sch — Reference PCIe 5.0 backplane: 32 GT/s trace routing, ±10 mil length matching, differential pair symmetry, controlled impedance (100 Ω ±10%), termination (VTT + 50 Ω), clock distribution (100 MHz reference + PLLs per socket)
- FIRMWARE_LOADER.c — 1Z-Edge boot code: PCIe root complex init, socket enumeration + hotplug support, fault isolation (bad socket doesn't take down the chassis), graceful degradation
- THERMAL_ANALYSIS.pdf — Heat path: dies → V2 package → socket contact → PCB → heatsink. CFD-simulated airflow, hotspot map, worst-case junction temp (85°C at 40°C ambient)
- POWER_BUDGET.xlsx — Per-socket, per-rail power breakdown
- FCC_PRECOMPLIANCE.md — Emissions predictions, mitigation strategies
- LICENSE.md, HANDOFF.md, CONTACT_INFO.txt
The Physics
PCIe 5.0 at 32 GT/s is fast but unforgiving:
- Signal integrity: Wrong trace length = deterministic jitter budget violated = link training fails. Length matching must be ±10 mils (~1.5 ps skew).
- Insertion loss: Standard FR4 loses ~6 dB/inch at 16 GHz. Chassis backplane traces must use low-loss dielectric (Megtron 6, Isola Tachyon) if traces exceed 3-4 inches.
- Impedance discontinuities: Via stubs must be back-drilled. Standard PCB via has an ~800 ps stub—kills PCIe 5.0.
- Return current path: Ground plane cutouts create impedance bumps. The reference schematic shows how to route ground properly.
The bus master firmware is production-grade: handles socket hotplug (insertion/removal during operation), fault isolation (bad die can be quarantined), graceful degradation (missing socket doesn't take down the chassis).
Your Work
- PCB layout: Impedance-controlled routing, differential pair symmetry. Requires competent HSD (High-Speed Digital) engineer. Rate: $150-250/hr, ~40-60 hours for a 4-socket card layout.
- Fab: Sanmina, TTM, or Multek for Megtron 6 stackup. ~$3-5k for 5 prototypes.
- Bus master silicon: AutoPhi 1Z-Edge chip (buy from Chris's AutoPhi store: SKU AUTOPHI-1Z-EDGE, ~$500-2k depending on qty)
- Thermal: Heatsink design (custom finned aluminum, $50-200), optional axial fan (Delta AFB0812), thermal interface material (Arctic MX-6 or Bergquist Sil-Pad 2000)
- Firmware: Chris provides the loader. You integrate with your host OS driver (see WPD-STUDY-WINDOWS or WPD-STUDY-FIRMWARE for Windows examples).
- Certification (CHASSIS-CARD): FCC Part 15 Class B (~$3-5k at a compliance lab), PCI-SIG compliance testing ($2-5k for PCIe electrical/protocol compliance)
Timeline
- Schematic capture (adapt reference): 1-2 weeks
- PCB layout: 4-6 weeks
- Fab: 3-4 weeks
- Assembly + bring-up: 2-3 weeks
- Firmware integration: 2-4 weeks
- Compliance testing: 4-6 weeks
- Total to first shippable card: 4-6 months
License (Study Tier)
✅ Build Chassis for research, publish designs. ❌ Sell Chassis units commercially. Upgrade: WRITEPHI-COMMERCIAL ($24,999).
Portfolio conversation — WritePhi (Project 57) + WritePhi Devices (Project 58)
These two product families are one continuous story in two chapters, not unrelated store listings. WritePhi (Project 57) is the kitchen-table fabrication layer: Writer → Blank → Dicer → PKG → Chassis → Library makes replaceable WritePhi dies at the bench. WritePhi Devices / WPD (Project 58) is the deployment layer for those same dies: the V2 inset package (carried forward from WRITEPHI-PKG and cut geometry from WRITEPHI-DICER) drops into pinned sockets on a reference PCIe 5.0 card, where Windows-facing CSD and ACCEL personas plus on-card firmware turn a homemade die into a plug-and-play host peripheral.
If you are buying on this page, you are in the make chapter. An OEM or power user who completes the 57 pipeline and wants volume-manufacturable packaging plus a Windows card stack continues in the run chapter — browse WritePhi Devices (WPD) on the same store. Neither family requires the other to be useful alone; together they describe the full path from blank substrate to installed Windows accelerator.
Fulfillment: Instant download after checkout. SHA-256 checksum published for integrity verification.
Region: USA-only (nginx geoblocking enforced). International buyers: contact us for special licensing.
Currency: USD only. Sub-$10k via standard checkout (Stripe). Over $10k: Term Sheet financing available.
Support: crioneaka@outlook.com | Christopher Gabriel Brown, Inventor | 24-48hr response.
Chris's philosophy: Every design engineered by hand. If it's specced, it works. If it has limits, we say so.
© 2026 Christopher Gabriel Brown · cri-one.com · Patent-pending inventions
