WPD Study — Firmware Blueprint

WPD Firmware — A Minimal OS for the AutoPhi 1Z-Edge Bus Master

The on-device firmware that makes WPD work. Runs on the AutoPhi 1Z-Edge bus master. Boots, reads persona strap, initializes hardware, exposes the right interface (NVMe for CSD, MMIO queues for ACCEL). Same codebase, two personas.

Architecture

┌─────────────────────────────────────┐
│ Boot / Persona Select               │  ← reads strap R1/R2
│ (reads NOR flash, sets up MMU)      │
└─────────────────────────────────────┘
           ↓
┌─────────────────────────────────────┐
│ Shared Runtime                       │
│ - PCIe root complex init             │
│ - Hyperthreading (2 threads/core)    │
│ - Socket management (4 V2 sockets)   │
│ - DDR4 controller (2-4 GB buffer)    │
│ - NOR flash driver (firmware storage)│
└─────────────────────────────────────┘
           ↓
┌────────────────────┬────────────────┐
│ CSD Persona        │ ACCEL Persona  │
│ - NVMe front-end   │ - MMIO queues  │
│ - Comp Programs    │ - Job dispatch │
│ - Query engine     │ - Scheduler    │
│ - Namespace mgmt   │ - DirectML VM  │
└────────────────────┴────────────────┘

What's In The Zip

FIRMWARE_SPEC.md — Master Specification

• Boot flow (from reset to persona ready)
• Memory map (BAR0, BAR1, DDR4 layout)
• Interrupt architecture (MSI-X vectors)
• Power management (idle states, wake events)

Bootloader

• Read strap resistors via GPIO
• Initialize MMU + cache
• Load persona firmware from NOR flash (SHA-256 verified)
• Jump to persona main()
• Fallback: if persona firmware corrupt, boot recovery mode (allows re-flash via PCIe DMA)

Shared Runtime

• PCIe root complex: Enumerate host bridge, configure BAR windows, handle config-space accesses
• Hyperthreading management: 1Z-Edge supports 2 hardware threads per core; runtime provides thread pool for both personas
• Socket management: 4× V2 socket enumeration, hotplug support (die insertion/removal detection), fault isolation (bad die quarantine)
• DDR4 controller: Memory training on boot, ECC scrubbing during idle, error reporting to host
• NOR flash driver: Persona firmware storage, wear leveling, verify-after-write

CSD Persona Firmware

• NVMe front-end: Parses NVMe commands from host, translates to internal operations
• Namespace management: Standard NVMe namespaces map to storage; Computational Programs map to WritePhi ICs
• Computational Programs registry: Table of installed programs, maps namespace ID → WritePhi IC → parameters
• Query engine: Executes on-device IC (via socket bus), returns results as NVMe read response
• SMART logging: Standard NVMe SMART fields (endurance, temperature, error counts)

ACCEL Persona Firmware

• MMIO queue listener: Monitors host-mapped ring buffers for new job submissions
• Job dispatcher: Routes jobs to available sockets based on required IC type
• Scheduler:
  • FIFO by default, priority-boostable
  • Dependency tracking (job B waits for job A completion)
  • Fault recovery (retry on transient error, quarantine socket on persistent error)
• DirectML bytecode interpreter:
  • Consumes DirectML operator streams from the wpd_accel.sys driver
  • JIT-compiles operators to WritePhi IC sequences
  • Manages activation memory in DDR4

Test Harness

• Bare-metal tests for each subsystem (bootloader, memory, PCIe, socket, both personas)
• Loopback tests (host command → firmware → host response, verify end-to-end)
• Fault injection (simulate socket failure, verify graceful degradation)

Real Capability

This is a minimal but complete OS for a specialized device. You'll understand:

• How a hypervisor-style platform handles multiple work modes on shared silicon
• How to build a real MMIO queue system that survives concurrent host+device access
• How to integrate DirectML for GPU-agnostic ML inference on custom silicon
• How NVMe 2.0 Computational Programs work (they're new; few implementations exist)

Your Work

1. Firmware integration: Adapt to your specific PCB variant (BAR layouts, GPIO mappings, DDR4 config)
2. Performance tuning: Memory bandwidth optimization, cache line alignment, hyperthread scheduling
3. Testing: Extend test harness with your workload-specific tests
4. Power management: Implement idle state entry/exit if targeting battery-powered use cases
5. Field updates: Design a firmware update mechanism (via PCIe DMA to NOR flash, with rollback)

Timeline

• Bootloader adaptation: 1-2 weeks
• Shared runtime integration: 2-4 weeks
• Persona firmware bring-up: 4-8 weeks per persona
• Testing + hardening: 4-8 weeks
• Total to production-grade firmware: 3-6 months

License (Study Tier)

✅ Modify firmware for research/personal use. ❌ Sell WPD cards with this firmware commercially. Upgrade: WPD-COMMERCIAL ($49,999).

Portfolio conversation — WritePhi Devices (Project 58) + WritePhi (Project 57)

WPD does not exist in isolation. It is the Windows host deployment half of the same portfolio conversation that begins in WritePhi (Project 57). Project 57's kitchen-table pipeline — Writer, Blank, Dicer, PKG socket-BGA, Chassis bed, and reference IC library — fabricates the M-grade and H-grade WritePhi dies that this card's four pinned sockets accept. The V2 package blueprint here is an explicit production-scale extension of 57's PKG plus additional cut marks and tabs that WRITEPHI-DICER executes in the same dicing pass.

If you are buying on this page, you are in the run chapter: PCIe card reference designs, persona firmware, and Windows driver plans. Makers who need to produce the dies themselves start in the make chapter — browse WritePhi (Project 57). Either half stands alone for study or commercial licensing; both halves together narrate bench fabrication through installed Windows compute.

Fulfillment: Instant download after checkout. SHA-256 checksum published for integrity verification.

Region: USA-only (nginx geoblocking enforced). International buyers: contact us for special licensing.

Currency: USD only. Sub-$10k via standard checkout (Stripe). Over $10k: Term Sheet financing available.

Support: crioneaka@outlook.com | Christopher Gabriel Brown, Inventor | 24-48hr response.

Chris's philosophy: Every design engineered by hand. If it's specced, it works. If it has limits, we say so.

© 2026 Christopher Gabriel Brown · cri-one.com · Patent-pending inventions