978a74253da3efd0dd61ce38681fc31ce78ce105baca6e1a6b8939fae74b9dcb
AutoPhi Build Your Accelerator - Complete Vertical Stack
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
The whole vertical stack for building a PCIe accelerator card, in one download. RTL, GDSII generator, OpenLane2 flow, driver, firmware, and hardware Verilog. You choose the core, run the generator, take the .gds to a foundry, order the interposer and carrier from this store, flash the driver, plug it in.
This is the flagship blueprint. Every other product on this store is a slice of the same stack sold separately. This bundle is the whole thing at once, ordered top to bottom, with the integration documentation that binds it together.
What is in the download
| Layer | Contents | Substance |
| 01-silicon/ | 10 APM01 core specification sheets and full synthesised RTL netlists (color_math_alu, em_cooling_ctrl, led_power_recycler, light_trigger_core, nanophotonic_io, neuromorphic_engine, qec_surface_code, quantum_battery_ctrl, quantum_exec_unit, apm01_s and more) | 178 MB raw |
| 02-gdsii-generator/ | Standalone disc: FAILSAFE_GDSII_GENERATOR.py, MULTI_GEN_GDSII_GENERATOR.py, VERIFY_GDSII.py, CHECK_SETUP.py, standalone guide, quick reference, RUN_GDSII_GENERATION.bat | 5.9 MB, self-contained |
| 03-openlane2/ | Complete OpenLane2 RTL-to-GDSII flow with Nix-reproducible build, so you can audit or re-run every step the generator performs | 16 MB, open source |
| 04-driver/ | software/ Linux kernel driver (autophi_drv_bus, core, i2c, spi, uart, ioctl.h). firmware/ on-chip firmware (autophi_fw_bus, core, i2c, spi, uart, regmap.h, ic_table.h, failover.h). hardware/ reference Verilog (autophi_aes256.v, bus_driver.v, commandments.v, debug_port.v, i2c_driver.v, spi_driver.v, uart_driver.v, universal_driver.v, watchdog.v, testbench.v) | 30+ files |
| 05-integration-docs/ | README.md with step-by-step build instructions, STACK_MAP.md diagramming how the layers wire together | Written to be read once |
Ten cores
You pick which core to fabricate. The bundle ships specs and RTL for all ten so you can decide based on what you are actually building.
| Code | Core | Role |
| APM01-D | NEXUS | Data Processing Unit — network, storage, security offload |
| APM01-E | EDGE | Edge inference, low-power |
| APM01-I | INFER | Datacentre inference |
| APM01-L | LINGUA | Language model acceleration |
| APM01-N | SPIKE | Spiking, neuromorphic |
| APM01-Q | QUBIT | Quantum control + surface-code cycles |
| APM01-R | REV | Data-path acceleration |
| APM01-S | SCALE | Control plane, orchestration |
| APM01-T | TRAIN | Training / gradient hardware |
| APM01-V | VISION | Vision, imaging pipeline |
What is NOT in this bundle
Pre-generated GDSII. You run the generator; you get your own GDSII. Selling the pre-fabbed layout would defeat the point of shipping the generator, and would let a buyer re-sell the design without paying for it. This way, the design is yours the moment you run the flow.
Interposer PCB. Sold separately in three tiers on this store — Access $400k, Standard $760k, Premium $1.2M.
Carrier board PCB. Sold separately: BGA-256, BGA-900, BGA-1536.
MSP430 firmware for the carrier. Board-specific and buyer-authored. The interface skeleton is included in 04-driver/hardware/autophi_commandments.v if you want a starting point.
The stack, top to bottom
Host Linux ioctl / char device (04-driver/software/)
v
PCIe x16 finger electrical + transaction layer
v
Carrier board BGA under-die, MSP430, LDOs, cage (buy separately)
v
Under-die BGA 0.8 mm pitch
v
Interposer 12/18/24 layer HDI substrate (buy separately)
v
Die-side pads microvia landings
v
APM01 core single die, one function (01-silicon/rtl/)
compiled by 02-gdsii-generator/
or via 03-openlane2/ if you want
to modify the RTL first
firmware in 04-driver/firmware/
bus interfaces in 04-driver/hardware/
Independent auditability
Nothing in this stack requires a running AutoPhi service. Nothing phones home. The generator runs offline. The RTL synthesises with open-source tools (see 03-openlane2/). The driver builds against a standard Linux kernel tree. The KiCad projects open in KiCad 10 without extensions. That is intentional — a buyer at this level needs a design they can audit, modify, and take to any foundry, not a design that requires AutoPhi's cooperation to build.
Who this is for
The buyer building an accelerator from scratch and unwilling to build every layer alone. The team that has the wafer budget but does not have the substrate router. The startup that needs a PCIe device shipped in one product cycle. The lab that wants a reference stack to audit before designing their own.
Not for someone who wants a single component to drop into an existing design — that customer is served by the individual products on this store, cheaper.
Support
This is a design-source product. Delivered as a single download, editable at every layer, no license server, no runtime dependencies on AutoPhi infrastructure. If a generator regeneration bulletin is issued, it is posted on this product page.
