AutoPhi V19 PCIe 5.0 QSFP28 Optical - BGA-1536 Editable KiCad Design Source

AutoPhi V19 PCIe 5.0 QSFP28 Optical — BGA-1536 Editable KiCad Design Source

The complete, editable engineering design. Not gerbers. Not a datasheet. The actual KiCad project, opened and modified on your own bench.

What this is

This is the flagship carrier — the largest ball field in the family, sized for 64-plus SerDes lanes, dual QSFP28 optical cages and a dense management fabric. You receive the design as source: the full hierarchical schematic, the routed board, every library the project references, the 3D models, the ball-map spreadsheets, and a netlist exported from the schematic so you can audit connectivity before you ever launch KiCad. Open board/*.kicad_pro in KiCad 10 and the entire project loads with its libraries already wired up.

AutoPhi ships blueprints. You take the design to whichever fabricator and whichever volumes you already trust — there is no tooling lock, no per-unit royalty, and no obligation to come back to us to build it.

The board at a glance

Component census: 383 × C · 62 × R · 32 × U · 9 × FB · 8 × RT · 6 × TP · 5 × J · 4 × CS · 4 × MH

Layer stackup

Twelve copper layers in an HDI arrangement, with dedicated ground and power planes interleaved between the signal layers so every high-speed pair has a reference plane adjacent to it.

Copper pours: GND on 10 layers · +3.3V on 1 layer · 1V0 on 1 layer.

Routing, layer by layer

Via geometry in use (pad / drill): 0.30/0.15 mm ×1,077 · 0.50/0.30 mm ×485 · 0.35/0.20 mm ×409 · 0.34/0.24 mm ×11 · 0.36/0.26 mm ×10 · 0.60/0.35 mm ×5.

Design rules and netclasses

This is an HDI-class design. Confirm your fabricator can hold these before quoting — the annular ring and laser drill sizes are the numbers that decide whether a shop can build it.

Eleven netclasses are defined, so the router and DRC treat a PCIe lane differently from a 12 V rail rather than applying one global rule:

All dimensions in millimetres.

The schematic — 28 sheets

A hierarchical design, not one enormous page. The root sheet indexes the pages below; each is self-contained and connected by global labels, so the same net name means the same net everywhere in the project.

1. 01 central processor — the BGA site itself — the accelerator's ball field, its decoupling and its escape fan-out
2. 02 pcie retimers redrivers — DS80PCI810 retimers conditioning the PCIe lanes between the edge fingers and the die
3. 03 pcie x16 edge connector — the x16 gold-finger interface, all 164 pins, with PCIe-spec pin naming
4. 04 power tree — rail derivation and distribution across the card
5. 05 compute — the compute cluster and its local support
6. 06 telemetry clock — clock generation and the telemetry path
7. 07 optical thermal — optical front end and thermal sensing
8. 08 esd protection array — ESD clamps on every externally exposed line
9. 09 bracket i o connectors — the QSFP28 cages and bracket-edge I/O
10. 10 mounting test — mounting holes, fiducials and test points
11. 11 passives — the bulk passive population
12. 12 retimer decoupling — per-retimer decoupling networks
13. 13 pcie ac coupling — AC-coupling capacitors on the high-speed pairs
14. 14 ddr3 aux — DDR3 auxiliary support
15. 15 power supplements — supplementary rail conditioning
16. 16 ddr3 flyby term — fly-by topology termination for the DDR3 address/command bus
17. 17 ddr3 chip — the DDR3 device and its byte lanes
18. 18 boot eeprom leds — boot EEPROM and status indication
19. 19 power tree main — the main power tree
20. 20 clock si5351 — Si5351 programmable clock generation
21. 21 charger usbc — USB-C side-channel and charging
22. 22 esd protection — further ESD protection
23. 23 telemetry — telemetry acquisition
24. 24 mcu msp430 — the MSP430 housekeeping controller
25. 25 power filter — rail filtering
26. 26 heatsink mounting — heatsink mounting provisions
27. 27 qsfp cage — the first QSFP28 cage
28. 28 qsfp cage 3 — the second QSFP28 cage

Everything in the download (13.7 MB)

• schematic/ — the root sheet plus all 28 child pages
• board/ — the routed .kicad_pcb, the .kicad_pro project carrying the rules and netclasses above, and both library tables
• libraries/ — every symbol and footprint library the design references, including the AutoPhi BGA symbols, the BGA-1536 footprint, the 164-pin PCIe x16 edge connector, the DDR3 x16 FBGA and the DS80PCI810 retimer
• 3d/ — the 3D models used by the footprints, so the board renders and mechanically checks straight out of the box
• pinmaps/ — the ball-to-signal assignment as CSV, which is the document you will actually work from when adapting the design
• netlist/ — a netlist exported from this schematic (1,708 nets), so connectivity can be verified with a text editor and no KiCad install
• KNOWN-ISSUES.txt — see below
• README.txt — orientation and verification steps

Read this before you buy — known gaps

Who this is for

Teams standing up a PCIe 5.0 accelerator prototype who would rather start from a routed HDI carrier than draw a 1536-ball escape from scratch. The ball-field escape, the plane structure and the high-speed lane routing represent the largest block of layout time in a design like this, and it is done. What remains is the power section, which is well-defined work with a known architecture.

If you need a finished, fully-populated design you can send straight to assembly, this is not that, and the section above says so plainly. If you want the hard layout done and are equipped to close out a power tree, this will save you weeks.

Delivered as a ZIP (13.7 MB, 113 files). Licensed for your own fabrication and modification. Christopher Gabriel Brown — CRI-ONE.COM