ScopePhi Card Blueprint
Why you'd want it
The add-in card that carries the ScopePhi die, drawn to standard PCIe full-length size for normal server slots.
- Who it's for: board teams that need the carrier card design for the ScopePhi die and interposer.
- The problem it solves: a populated 525-part card design plus fab files, with remaining routing items listed by name.
- What you get: KiCad board, schematic, BOM, Gerbers, drill and assembly files on encrypted Blu-ray; fab fees not included.
A chip should have somewhere to live. The ScopePhi die is one of the densest pieces of silicon anyone has drawn, but silicon by itself does not plug into a server — it needs a carrier, a printed-circuit board with the right slot connector at one end, the right pads for the die at the other, and the right lanes between the two to carry everything the die wants to say out of the package and into the world.
The ScopePhi Card is that carrier. From across the room it looks the way every datacenter accelerator card has looked for the last twenty years: a rectangle of green or dark laminate, 256 millimetres long, 111 millimetres wide, a gold-fingered PCIe edge on one side, a small bank of QSFP optical cages at the back, a thick heatsink on top. The familiarity is on purpose. Any system that already takes a standard full-length PCIe Gen 5 card will take this one. No new chassis. No new rails. No new power supply category. Operators keep their existing fleet layout and swap cards.
Under the heatsink is where it stops looking familiar. The right-hand third of the board carries the 1,536-ball ScopePhi BGA at reference designator U16. The left two thirds carry everything that lets the die behave in a datacenter: the retimer chain so the PCIe signal survives the trip from the card edge to the die, the DDR3 memory next to the compute end, the sideband management that lets the host talk to the card at startup and under fault, and the QSFP28 optical front end so bytes can leave the chassis on fiber instead of copper. Twelve layers of Megtron 6 low-loss laminate under all of it — the material you choose when the signal has to arrive clean at a few tens of gigabits per second per lane without the dielectric smearing it.
The number that matters here is 525. That is how many real parts are drawn and placed on this card. Earlier tier boards in the AutoPhi family hold around 46 placeholder parts and no main silicon — those are landing pads, not products. This one is a drawn card with the compute part on it, routed to roughly 70% today, with every open item listed in plain English rather than hidden under a cover sheet. 8,388 track segments. 1,997 vias. 37 copper zones. 50 clearance items left to resolve by hand in the dense ball-escape under U16. 70 airwires still open on the LDO orphan pins. That is engineering state, said straight.
What a patron is pledging for on this card is slightly different from the die pledges. The die pledges fund the mask set and the fab — a chip that does not exist yet. This one is a board design that exists now: KiCad PCB, schematic, netlist, flat BOM, Gerbers, drill, IPC-2581, pick-and-place, STEP, pinmap, and a 33-script Python pipeline that respins the TI TIDA-00423 reference into 34 different I/O variants so a buyer can swap the front end without touching the compute end. The deliverable is a working data set on an AES-256-encrypted Blu-ray; the patron can walk into Advanced Circuits with it and order boards. Non-exclusive on purpose — multiple patrons, each with their own copy.
ScopePhi Card Blueprint
The PCI Express Gen 5 add-in card that carries the ScopePhi die plus its 1,536-ball interposer. A finished design, drawn to standard datacenter mechanicals so the card drops into a chassis slot the way any production accelerator card would. Looks like a familiar PCIe accelerator from the outside; what sits under the heatsink is a single ScopePhi die on its interposer.
Mechanical and electrical.
- 12-layer Megtron 6 low-loss laminate (datacenter-grade)
- 256.625 × 111.95 mm — standard PCIe full-length form factor
- Controlled impedance on PCIe Gen 5, QSFP28 SerDes, and DDR3 byte lanes
- 1,536-ball BGA footprint for the ScopePhi die at U16 (right-hand third of the board)
- Retimer chain, DDR3 memory, sideband management, and QSFP28 optical front end on the left two thirds
- 75 W standard-slot power envelope, with headroom for higher PCIe CEM power tiers if the chassis provides them
- 525 real components placed — this is a drawn-and-populated card, not a placeholder board
What makes this a “finished” design. Earlier tier boards in the AutoPhi family hold roughly 46 placeholder parts and no main silicon. This one holds 525 real components and the ScopePhi BGA itself at U16. Every number in the deliverable was read from the working KiCad file and checked against KiCad's own export statistics. After the 2026-10-24 cleanup the live board file sits at production-handoff state: 8,388 track segments, 1,997 vias, 37 copper zones, zero shorts, zero mask bridges, defective footprints repaired, with 50 DRC clearance items + 70 airwires remaining as a named open-item list rather than a percentage of unrouted copper. The production handoff pack (SCOPEPHI-CARD-BLUEPRINT-PACK-2026-10-24) — Gerbers, Excellon drill, IPC-2581, 3D STEP, positions.csv, IPC-D-356 netlist, PDF layer book, renders — is in the deliverable, generated from the live board file.
Deliverable (ships now — design is complete).
- KiCad PCB file
- Schematic + netlist + flat BOM
- Gerber RS-274X set
- Excellon drill files
- IPC-2581 (full build-dataset)
- Pick-and-place CSV
- 3D STEP for mechanical fit
- 1,536-ball pinmap
- Specctra routing pair for continued auto-route
- 33-script Python pipeline that forks the TI TIDA-00423 reference into 34 I/O variants — so a buyer can respin the front end without redrawing the compute end
Target fab: Advanced Circuits (blind + buried + stacked microvia all confirmed in-scope). Patent pending: USPTO 19/835,210 (umbrella).
Non-exclusive on purpose. Multiple patrons may pledge; each receives their own copy; the IP, package program and routing pipeline stay with the inventor.
Inventor. Christopher Gabriel Brown (cri-one.com), sole inventor.
Exhaustive deliverable checklist
- ☐ KiCad PCB file (the live working file, 525 real components placed)
- ☐ Full schematic (every one of the 525 parts, every net that joins them)
- ☐ Machine-readable netlist
- ☐ Flat BOM with manufacturer part numbers and reference designators
- ☐ Gerber RS-274X set (every copper, mask, silkscreen and paste layer)
- ☐ Excellon drill files (plated + non-plated)
- ☐ IPC-2581 (full build dataset in the current industry exchange format)
- ☐ Pick-and-place CSV
- ☐ 3D STEP for mechanical fit in the target chassis
- ☐ 1,536-ball pinmap (CSV + visual)
- ☐ Specctra routing pair (so a buyer can continue auto-route rather than start over)
- ☐ 33-script Python pipeline that forks the TI TIDA-00423 reference into 34 I/O variants
- ☐ Stackup spec: 12 layers, Megtron 6 low-loss laminate, controlled impedance on PCIe + QSFP28 + DDR3
- ☐ Power envelope spec: 75 W slot with headroom for higher PCIe CEM tiers
- ☐ Open-item inventory (dense BGA escape clearance items + LDO orphan pins) stated in plain English
- ☐ Advanced Circuits fab-notes README (blind + buried + stacked microvia confirmed)
- ☐ AES-256 encryption of the Blu-ray and the key-handoff procedure
- ☐ Patent filing: USPTO 19/835,210 (umbrella)
What could go wrong, and what we have done about it
- Named open items, not a percentage of unrouted copper. After the 2026-10-24 cleanup the live board file carries 50 DRC clearance items + 70 airwires, zero shorts, zero mask bridges, defective footprints repaired. The remaining items are listed by name — mostly in the dense BGA escape under U16 and on LDO orphan pins. The Specctra routing pair ships with the package so a buyer's board team continues the finishing work rather than starts over.
- Fab fees are not in the pledge. The pledge covers the engineering handoff — the AES-256-encrypted Blu-ray with the file set and the production handoff pack generated from the live board file. Advanced Circuits panels (or any equivalent HDI fab) are ordered by the patron directly at the fab's standard pricing.
- Two paths at Advanced Circuits, patron picks. Either (a) order HDI panels only, against the Gerbers and IPC-2581 in the handoff pack — standard HDI pricing, no design involvement from AC; or (b) hire AC's Design Services to close the remaining DRC + airwires on the live board file and then fab the panels in the same engagement — turnkey from file to populated board. Both are at AC's own standard pricing, both sit outside this pledge.
- Dense BGA escape under a 1,536-ball package. Advanced Circuits' blind + buried + stacked microvia capability covers the escape geometry. The 28-layer interposer is where most of the pitch translation lives; the card itself does not have to do the hard HDI.
- PCIe Gen 5 signal integrity on a 256 mm card. Megtron 6 low-loss laminate with controlled impedance on the PCIe lanes; retimer chain between the slot and the die so the signal arrives clean at the far end.
- Chassis compatibility. Standard PCIe full-length form factor (256.625 × 111.95 mm). Standard CEM edge connector. Standard 75 W slot power. No custom chassis, no custom rails.
- Front-end lock-in (the datacenter wants different optics / memory / sideband). The 33-script pipeline forks the TI TIDA-00423 reference into 34 I/O variants. A buyer who wants a different front end respins the front end without touching the compute end.
- LDO orphan pins. These are the PCIe 75W+ front-end LDOs that let the card accept standard slot power. Chris has confirmed intent; schematic completion is a short follow-up and is listed openly as engineering state.
- Thermal budget on a 525-part card with the ScopePhi die at U16. Standard datacenter chassis cooling at 75 W; higher-tier chassis supply higher PCIe CEM power if more headroom is wanted.
- IP escape. AES-256-encrypted Blu-ray with keyed handoff. The IP, package program and routing pipeline stay with the inventor; patrons receive a copy, not control.
Tests and measurements (internal, in the deliverable)
- 2026-10-24 cleanup session results: ScopePhi Card board file from 1,655 DRC violations + 128 airwires down to 50 DRC clearance items + 70 airwires, zero shorts, zero mask bridges
- Defective footprints repaired this session: SOT-23-6 and TPS735
- File promoted to live board file after the cleanup
- Component count measured from the working KiCad file: 525 placed components
- Routing stats from KiCad's own export: 8,388 track segments, 1,997 vias, 37 copper zones
- Production handoff pack
SCOPEPHI-CARD-BLUEPRINT-PACK-2026-10-24generated from the live board file: Gerbers, Excellon drill, IPC-2581, 3D STEP, positions.csv, IPC-D-356 netlist, PDF layer book, renders - ERC (electrical rules check) history captured:
erc_baseline_256,erc_after_sheet01…erc_after_all,erc_1536— all shipped with the package - bom_vs_v3_report.txt drift analysis included so the buyer can see every delta vs the reference BOM
References
- USPTO Patent Center — patentcenter.uspto.gov — filing 19/835,210 (umbrella)
- Advanced Circuits / AdvancedPCB / APCT (target HDI fab, blind + buried + stacked microvia capability) — advancedpcb.com (Design Services at advancedpcb.com → Design Services)
- PCI-SIG (PCIe Gen 5 Card Electromechanical specification) — pcisig.com
- Panasonic Megtron 6 low-loss laminate datasheet — industrial.panasonic.com → multi-layer circuit board materials
- Texas Instruments TIDA-00423 reference design (the 34-variant respin base) — ti.com/tool/TIDA-00423
- KiCad EDA (the design is drawn in KiCad) — kicad.org
- Freerouting (Specctra routing pair interop) — freerouting.org
Also patent-pending under Quantum-Reactor-Scale. The compute-core architecture of this product is additionally covered by U.S. patent-pending applications 19/865,419 and 19/865,443 (filed 2026-11-06), with the chip-scale instantiation available as QRS-116 Compute Core Blueprint, and the reactor-scale embodiments available as QRS-117 Quantum Electric Reactor Blueprint (electricity-primary) and QRS-118 Compute Reactor Blueprint (compute-primary).
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ScopePhi Performance IC BlueprintThe two-reticle ScopePhi: one larger stitched die.
$216,000,000,000.00 -
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