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50-pcie8-standard

$884,148.75

In stock

SKU

2081

Cri-One PCIe 8.0 SSD: data rises from the NAND into the AutoPhi Compute Engine on the drive and only one small answer leaves for the host, animated picture

Asset valuation: $20,000,000,000. Master index of all projects: PROJECTSINDEX. Last edited: 2026-06-14 Status: Research — working software simulator; HDL / firmware / driver skeletons; KiCad form-factor stub Maturity (per PACKAGEARCHITECTURE.md): L1 (Research / Working Software)

For the curious

A drive should do more than hold your data and hand it back. This design puts an AutoPhi compute core and a PCIe 8.0 NVMe solid-state drive on one die, so it can run a search, a histogram or a hash check where the bytes live and return only the answer. Terabytes stay inside and a small result crosses the bus: bandwidth amplification of roughly a hundred to a thousand times. Every stored byte is encrypted at rest with AES-256-XTS, keys loaded at power-on and never readable, tweaked by the physical page address rather than the host block address, so ciphertext is bound to where it sits and crypto-erase is instant. The drive is governed by the WonderPhi Universal Permanent Driver, version 1.0.0, locked by a constitution of ten commandments that shall never be updated, on a standard M.2 22110 card.

These are design targets, not shipping silicon. PCIe 8.0 runs 256 GT/s per lane, so a four-lane link carries about 256 GB/s. Sequential reads target around 50 GB/s, 12 W at full work and 5 mW asleep. The PCIe 8.0 specification itself is projected for ratification around 2028: this is a first-mover package for datacenter operators and storage engineering teams. It holds a working software simulator, HDL, firmware and driver skeletons, a KiCad form-factor stub, and a patent-pending position under U.S. Application 19/710,460, twenty claims. The buyer walks away with the blueprint to be first in line when the bus arrives. The IP stays with the inventor.

Details

Description

50-pcie8-standard — Cri-One PCIe 8.0 SSD (AutoPhi Computational-Storage Chip)

Inventor: Christopher Gabriel Brown

U.S. Patent Application 19/710,460 (filed 2026-06-17; Confirmation No. 3169; Patent Center No. 77534311). Title: “Computational-Storage Apparatus with Inline AES-XTS Encryption Tweaked by Physical-Page Address and a Near-Data Compute Engine Sharing a Single Translation-Layer Command Port.” Related to U.S. Application 18/370,908 (AutoPhi IC family).

Status: Patent-pending. This is a design package — not shipping silicon. The PCI-SIG PCIe 8.0 specification is projected for ratification circa 2028.

Overview

The Cri-One PCIe 8.0 SSD is an AutoPhi computational-storage chip — an AutoPhi compute core fused with a first-mover PCIe 8.0 NVMe solid-state drive on a single die, computing near the data with every stored byte encrypted at rest by WonderPhi AES (AES-256-XTS, keys never readable). It is governed by the WonderPhi Universal Permanent Driver (version 1.0.0, locked by a constitution of 10 Commandments that shall never be updated) and targets a standard M.2 22110 form factor.

PCIe 8.0 doubles PCIe 7.0 to 256 GT/s per lane using PAM4 signalling, yielding approximately 64 GB/s usable per lane per direction after FLIT overhead. An x4 SSD link sustains approximately 256 GB/s — well beyond anything shipping at any price today. The on-die AutoPhi Compute Engine (ACE) enables programmable in-storage computation (VOXEL, SCAN, XFORM) that keeps terabytes of data inside the drive and returns only small answers to the host, achieving bandwidth amplification of approximately 100–1000×.

Product Identity

Field Value

Project number 50

SKU 2081

Slug 50-pcie8-standard

Sector Computing & Semiconductors — Computational Storage

Chip class AutoPhi computational-storage chip (compute + secured storage)

Maturity level L1 — Research / Working Software

Patent status Patent-pending (U.S. App. 19/710,460; related to U.S. App. 18/370,908)

Patent claims 20 claims (15 apparatus + 4 method + 1 means-plus-function)

Inventor Christopher Gabriel Brown

Conception roots 2015–2017 Invent Depositions (ISBN 9781979767897, 1,757 entries)

Three Roles, One Drive

Role How It Works Use Cases

1. Bulk NVMe Storage Host enqueues NVMe Read/Write commands via SQ doorbell; controller runs FTL lookup, DMAs to/from NAND; completion posted to CQ with MSI-X interrupt. File systems, databases, object stores, archives

2. Self-Encrypting Drive (SED) AES-256-XTS engine inline on every read/write; master key wrapped by TCG Opal 2.0 PIN; tweak derived from packed physical-page address (not host LBA), binding ciphertext to physical location. Data-at-rest compliance, instant crypto-erase

3. AutoPhi Compute Engine (ACE) Host issues NVMe vendor opcode 0xC1 carrying an ACE program; engine streams matching pages through the FTL/AES path; only answers return via a single NVMe completion-queue event. Log search, hash verification, database scans, in-storage AI inference

Performance Targets

Metric Target

Host link PCIe 8.0 ×4 = ~256 GB/s usable theoretical

Sustained sequential read (4K LBA) ~50 GB/s (NAND-bound)

Sustained sequential write ~25 GB/s (program-throttled)

Random read 4K IOPS ~5 million

Random write 4K IOPS ~1.5 million

Read latency (mean, end-to-end) ~30 µs

Capacity 4 TB (8 TB stretch with double-density NAND)

Power (PS0, operational max) 12 W

Power (PS4, deep sleep) 5 mW

Endurance ~7.3 PBW (1 DWPD over 5 years)

MTTF 2.5 million hours

Data retention (powered off) 1 year @ 40 °C

ACE bandwidth amplification ~100–1000× (data stays in-storage; only answers cross PCIe)

Controller Architecture

Block Description

PCIe 8.0 PHY PAM4 at 256 GT/s per lane, 4 lanes; LTSSM link training; FLIT framing; DLLP credits + replay buffer; backward-compatible fallback (Gen 7 / 6 / 5 / 4 / 3 / 2.5 GT/s)

NVMe 2.1 Engine 64K queues × 64K depth each; MSI-X completions (up to 2048 vectors); vendor-specific opcodes 0xC0–0xFF (vendor ID 0xC1A1 = Cri-One, device ID 0x0008)

Flash Translation Layer (FTL) Hardware-accelerated LBA-to-PBA mapping; sequential allocator (channel-major); DRAM-resident L2P table with on-NAND checkpoint log (1-second interval)

Garbage Collector Background GC; victim selection by stale-count with PE-cycle bias; maintains ≥10% free-block ratio

LDPC ECC Codeword: 4,096 data + 224 parity = 4,320 bytes; corrects up to 120-bit errors per codeword; RBER −3 → UBER −15

AES-256-XTS (WonderPhi AES) Inline crypto on every read/write; dual 256-bit keys loaded at power-on, never readable; tweak = packed physical-page address (25-bit: 3-bit channel + 2-bit die + 12-bit block + 8-bit page); GF(2 128 ) alpha-multiply chain across sector; verified against NIST FIPS-197 + IEEE 1619 test vectors

AutoPhi Compute Engine (ACE) Programmable near-data core; VOXEL (histogram reduction), SCAN (predicate filter), XFORM (checksum/compress/inference); reads via ACE-to-FTL bridge with reserved CID range 0xE000–0xEFFF (4,096 CIDs); host invokes via vendor opcode 0xC1 through a single NVMe doorbell write

ONFI 5.1 NAND Interface 8 channels × CE; 2,400 MT/s per channel = 19.2 GB/s aggregate raw

LPDDR5-7500 Controller 4 GB FTL metadata cache; ×32 data bus; 1,875 MHz (DDR doubled)

Memory Map (Host-Visible via PCIe BAR0)

Region Offset Size Purpose

NVMe controller regs 0x0000 4 KB NVMe 2.1 standard: CAP, VS, CC, CSTS, AQA, ASQ, ACQ

Doorbells 0x1000 60 KB SQT[0..N], CQH[0..N] doorbell registers

Vendor registers 0x10000 64 KB AutoPhi telemetry, debug, GC controls, FTL inspection, ACE program/result registers

MSI-X table 0x80000 64 KB Up to 2,048 MSI-X vectors

Form Factor & Mechanical

Dimension Value

Form factor M.2 22110 (22.00 ± 0.15 mm × 110.00 ± 0.25 mm)

Edge connector M-key, 75 pins; ENIG gold finish; 30° chamfer

Component side Single-sided (top only, D5 host class)

PCB thickness 1.50 mm (production) / 0.80 mm (prototype)

PCB layers 6-layer impedance-controlled (production) / 4-layer (prototype)

Total Z height 3.58 mm (1.50 PCB + 1.50 components + 0.58 spreader)

Copper spreader C110 alloy, 22 × 100 × 0.58 mm, bonded with 3M 8810 thermal tape (1.0 W/m·K)

Mounting Single M2 × 3 mm screw at 110 mm end

Combined R θJA

Junction temperature (at 12 W, 25 °C ambient) ~70 °C (datacenter chassis with 1 m/s airflow)

Solder Lead-free SnAg3.0Cu0.5; 260 °C reflow rated (3× IPC reflow cycles)

Operating range Commercial: 0 to +70 °C ambient; Industrial v2: −40 to +85 °C

Power Architecture

Single 3.3 V input from M.2 slot (pins 7, 9, 11, 13) through a Bourns MF-MSMF150-2 polyfuse (1.5 A hold). Five derived rails:

Rail Voltage Max Current Regulator Load

+3V3 3.3 V 3.5 A peak M.2 slot (passthrough) All buck inputs + NAND VCC

VDDC 0.85 V 3.5 A TPS62810-Q1 (buck) Controller core

VDDIO 1.05 V 2.0 A TPS62086 (buck) Controller PHY + LPDDR5 VDD2

VDDNAND_IO 1.8 V 1.5 A TPS62085 (buck) NAND I/O ring + LPDDR5 logic

VDDQ_DRAM 0.5 V 1.5 A TLV741P (LDO) LPDDR5 VDDQ only

Power Budget

Block Voltage Current Power

Controller core 0.85 V ~3.0 A ~2.6 W

PHY I/O + aux 1.05 V ~1.5 A ~1.6 W

PCIe SerDes (×4 active) 0.85 V ~1.0 A ~0.9 W

LPDDR5 VDD2 1.05 V ~0.6 A ~0.6 W

LPDDR5 VDDQ 0.5 V ~1.0 A ~0.5 W

8× NAND active 3.3 V + 1.8 V ~150 mA each peak ~4.0 W combined

Buck regulator losses (~10%) — — ~1.0 W

Total worst-case — — ~11.2 W

NVMe Power States

PS Description Active Power Entry Latency Exit Latency

PS0 Operational max 12.0 W 0 µs 0 µs

PS1 Operational mid 6.5 W 10 µs 10 µs

PS2 Operational min 3.0 W 100 µs 100 µs

PS3 Non-operational, light 50 mW 5 ms 50 ms

PS4 Non-operational, deep 5 mW 100 ms 500 ms

Clock Domains

Clock Source Frequency Used By

clk_pcie_ref PCIe REFCLK on M.2 edge 100 MHz PCIe PHY PLL reference

clk_pcie_pma PHY PLL 16 GHz PCIe SerDes (PAM4 at 256 GT/s = 128 GBd)

clk_pcie_pcs PHY divider 1 GHz PCS / FLIT framing

clk_sys PLL from PCIe ref 500 MHz NVMe engine, FTL accelerator

clk_dram LPDDR5 PHY PLL 1,875 MHz LPDDR5-7500 controller (DDR doubled)

clk_nand Divider 200 MHz ONFI 2,400 MT/s (DDR doubled)

NAND Storage Architecture

Parameter Value

Media 8× Micron B58R 232-layer 3D TLC NAND (MT29F4T08EUHBC)

Capacity per chip 512 GB

Total raw capacity 4 TB (8×512 GB)

NAND interface ONFI 5.1, 2,400 MT/s per channel

Channels 8

Aggregate raw NAND bandwidth 19.2 GB/s

Page size 16 KB (host LBA = 4 KB)

Block size 256 pages = 4 MiB

P/E cycles ~3,000 per block (TLC)

ECC LDPC: 4,096 data + 224 parity bytes; corrects up to 120-bit errors

Namespace Raw NVMe namespaces; default NS1 = full 4 TB; host can create multiple via nvme create-ns

Encryption — WonderPhi AES

Every byte stored on the NAND media is encrypted at rest by the WonderPhi AES core — the embodiment of Commandment VIII ( “Thou shalt not steal” ). Key properties:

Property Detail

Algorithm AES-256-XTS (IEEE 1619)

Key size 2 × 256 bits (data key + tweak key)

Key loading Once at power-on; keys never appear on any host-accessible read port ( AUTOPHI_AES_KEY_NEVER_READABLE = 1 )

Tweak derivation Packed physical-page address (PPA), not host LBA — ciphertext at rest is bound to physical location

PPA format 25-bit: 3-bit channel + 2-bit die + 12-bit block + 8-bit page

XTS formula T base = AES-256-enc(Key2, PPA-derived tweak); T j = T base · α j in GF(2 128 ); C j = AES-256-enc(Key1, P j ⊕ T j ) ⊕ T j

Forward-binding When wear leveling relocates plaintext from PPA P1 to PPA P2, ciphertext at P2 differs from P1 even for identical plaintext

Crypto-erase Key destruction only — media becomes unrecoverable

RTL verification NIST FIPS-197 KAT + 3 IEEE 1619 XTS-AES-256 vectors (including non-zero LBA) + full 512-byte sector round-trip (32 blocks, alpha-chain verified across block_idx 0..31) + inline byte-stream pipeline — 15/15 PASS

AutoPhi Compute Engine (ACE)

ACE is the programmable near-data compute core that makes this an AutoPhi computational-storage chip rather than a plain SSD. The host invokes ACE through a single NVMe doorbell write using vendor opcode 0xC1; data reaches ACE already decrypted by WonderPhi AES through the shared FTL/AES path; only the reduced result crosses PCIe back to the host.

Operation Description Typical Use

VOXEL (ace_op = 1) AutoPhi voxel reduction — folds data into a histogram/signature Data profiling, analytics aggregation

SCAN (ace_op = 2) Near-data predicate scan/filter — returns LBAs whose data matches a needle Log search, hash verification, database WHERE clauses

XFORM (ace_op = 3) Streaming transform pipeline — checksum, compressibility estimate, inference SHA-256 verification, compression analysis, in-storage AI

ACE ↔ FTL Bridge & Arbiter

Mechanism Detail

Reserved CID range 0xE000–0xEFFF (4,096 distinct CIDs)

Bridge Translates ACE read requests into NVMe-format READ commands (opcode 0x02) with CIDs in the reserved range; 5-state FSM (IDLE, DRIVE, WAIT, RETURN, HOLD)

Arbiter Host port has priority; ready outputs are functions of FTL ready signal only (no circular dependency through NVMe engine doorbell-pulse semantics)

CID filter NVMe engine suppresses host CQE generation and MSI-X for completions in the reserved CID range — ACE reads are invisible to the host

Vendor SQE layout [7:0] opcode 0xC1; [10:8] ace_op; [31:16] CID; [63:32] NSID; [95:64] ace_count; [231:192] ace_lba; + 128-bit ace_param buffer

The WonderPhi Constitution — 10 Commandments

# Name Enforcement

I One Master One PCIe physical function; one storage authority (vendor 0xC1A1, device 0x0008)

II No Other Drivers Exclusive driver bind; no competing block/NVMe driver shall bind this device

III Valid Commands Only Every NVMe SQE validated; malformed commands rejected with INVALID_OPCODE

IV Power Rest Mandatory PS3/PS4 autonomous transitions (PS3 after 50 ms idle; PS4 after 5 s idle)

V Honour Legacy Backward-compatible to NVMe 1.0; PCIe link auto-downshifts to Gen 2

VI No Destroy Erase-before-program enforced; LDPC ECC; atomic FTL updates; power-loss-consistent on-NAND L2P log

VII Faithful Protocol Strict NVMe 2.1 + PCIe 8.0 + ONFI 5.1 conformance; vendor extensions only in reserved opcode range 0xC0–0xFF

VIII No Steal AES-256-XTS keys never leave silicon; hard caps on DMA bandwidth, queue depth (65,535), namespace count (128)

IX Honest Status SMART telemetry always truthful; bad block count, P/E cycles, temperature, media errors reported accurately

X Self-Contained No floating point in firmware; no dynamic allocation; all FTL metadata persisted on NAND; zero host-resident state

Hardware Layer — Verilog RTL (35 Modules, ~7,344 Lines)

Module Purpose

autophi_pcie8_phy.v PCIe 8.0 PHY abstraction (PAM4 hooks)

autophi_pcie8_mac.v MAC + LTSSM (link training)

autophi_pcie8_tlp.v Transaction Layer Packet encode/decode

autophi_nvme_engine.v NVMe 2.1 SQ/CQ doorbell engine + vendor-opcode ACE dispatch

autophi_nvme_cpl_tlp.v NVMe completion TLP assembly

autophi_ftl_core.v Flash Translation Layer hardware accelerator

autophi_gc_engine.v Garbage collector + wear leveling

autophi_ldpc_ecc.v LDPC ECC encode/decode

autophi_aes_sbox.v FIPS-197 forward + inverse S-box

autophi_aes256_core.v Iterative AES-256 encrypt/decrypt with key expansion (one round per clock)

autophi_aes256_xts.v XTS wrapper: dual-key, LBA tweak, GF(2 128 ) alpha-multiply, two AES sub-cores

autophi_aes_inline.v Byte-stream inline encrypt/decrypt pipeline with valid/ready handshake

autophi_aes_path.v AES datapath integration between FTL and NAND

autophi_sd_crc.v CRC7 + CRC16-CCITT (validated against SD known values)

autophi_sd_spi.v SD-SPI mode controller (CMD0/CMD8/ACMD41/CMD58/CMD17/CMD24)

autophi_sd_native.v Native 4-bit SD controller (CMD + DAT[3:0], 4× parallel CRC16)

autophi_compute_engine.v AutoPhi Compute Engine (ACE): VOXEL / SCAN / XFORM near-data core

autophi_ace_bridge.v ACE-to-FTL bridge (translates ACE reads into NVMe-format commands with reserved CIDs)

autophi_cmd_arb.v FTL command-port arbiter (host priority, no circular dependency)

autophi_nand_model.v Behavioral NAND model (simulation only)

autophi_dram_model.v Behavioral DRAM/L2P model (simulation only)

autophi_pcie8_top.v Top-level: instantiates entire controller spine (PHY → MAC → TLP → NVMe → FTL + GC/LDPC/AES/ACE)

RTL Verification Results

Testbench What It Proves Result

autophi_nvme_e2e_tb Host write → host read round-trip through L2P + behavioral NAND; unmapped LBA returns defined status 5/5 PASS

autophi_walk_encrypted_tb Round-trip with AES-XTS path inserted; NAND holds ciphertext; ciphertexts for different PPAs differ 8/8 PASS

autophi_walk_ace_tb ACE SCAN over 4 LBAs; testbench-serviced near-data read port; correct match count 3/3 PASS

autophi_walk_ace_real_tb Structural SCAN: bridge + arbiter active; reserved-CID filter excludes ACE completions from host CQE stream; matches=2 over visited=4 5/5 PASS

autophi_walk_ace_doorbell_tb Doorbell-invoked SCAN: host invokes ACE via vendor opcode 0xC1; synthesised CQE carries {visited=4, matches=2}; host sees 5 CQEs (4 writes + 1 ACE) 5/5 PASS

autophi_pcie8_testbench Controller-spine power-up: all 13 modules elaborate together; link-up reached; led_activity=1 PASS

autophi_aes256_xts_tb NIST FIPS-197 AES-256 KAT + 3 IEEE 1619 XTS-AES-256 vectors (including non-zero LBA) 6/6 PASS

autophi_aes256_xts_sector_tb Full 512-byte sector (32 blocks): encrypt + decrypt round-trip; alpha-chain across block_idx 0..31 2/2 PASS

autophi_aes_inline_tb Byte-stream inline encrypt pipeline; valid/ready handshake; full sector round-trip 4/4 PASS

autophi_sd_spi_tb SD-SPI bring-up against behavioral card model (CMD0 → CMD8 → ACMD41 → CMD58 → CMD17); SDHC detected; 512B ramp verified 3/3 PASS

Combined total 41 PASS / 0 FAIL

All testbenches pass under Icarus Verilog 12.0 (iverilog -g2012 + vvp).

Firmware Layer — Freestanding C (13 Files, ~722 Lines)

Module Purpose

autophi_fw_core.c / .h Service loop and dispatch

autophi_fw_nvme.c / .h NVMe command set handler

autophi_fw_ftl.c / .h FTL software model (mirror of HW path)

autophi_fw_nand.c / .h NAND ONFI / Toggle command sequencer

autophi_fw_smart.c / .h SMART telemetry collector

autophi_fw_compute.c / .h ACE program dispatch (NVMe vendor-specific commands)

autophi_pcie8_regmap.h Canonical register map

Cross-compiled with arm-none-eabi-gcc targeting Cortex-R5F; flags: -mcpu=cortex-r5 -mthumb -O2 -ffreestanding -nostdlib . No floating point, no dynamic allocation (Commandment X).

Host Software Layer — Linux Driver (5 Files, ~281 Lines)

Module Purpose

wonderphi_drv_core.c / .h Driver core (Linux kernel module skeleton)

wonderphi_drv_pci.c PCI enumeration + BAR mapping

wonderphi_drv_nvme.c NVMe admin/IO submission

wonderphi_ioctl.h ioctl interface for vendor-specific commands

example/wonderphi_example.c Reference user-space tool

Python Simulator (7 Files, ~654 Lines)

Module Purpose

pcie8.py PCIe 8.0 link bandwidth + TLP model (64 GB/s per lane)

nand.py 3D NAND array model (page/block/PE cycles)

autophi.py Controller FTL/GC/wear leveling

driver.py Host driver with NVMe-like queues

ssd.py Assembled PCIe8SSD device

compute.py AutoPhi Compute Engine (ACE) behavioral model

The simulator round-trips real data through the modeled link, controller, and NAND; verifies integrity by SHA-256; exercises trim; provokes garbage collection; and demonstrates the ACE near-data compute with ~4,274× data-movement offload verified regression-clean.

AutoPhi PCB Board Engine (~7,625 Lines Python)

Sub-module Lines Key Exports

rag/routing.py 1,204 50+ citations, 18 net classes, A* routing config, JLCPCB specs

rag/components.py 863 46 parts with BGA pin maps, body sizes, placement zones

rag/netlist.py 576 ALL_NETS dict, get_nets_for_component(), get_components_on_net()

rag/stackup.py 348 STACKUP_6L, STACKUP_8L, STACKUP_12L definitions

rag/placement.py 346 Placement zone rules and constraints

rag/io_configs.py 291 34 bracket connector configurations

rag/ti_knowledge.py 366 TI TIDA-00423 reference design parameters

rag/rules.py 194 PCIe5, VIA, TRACE_WIDTH, MATERIAL, FORM_FACTORS

layout/ — BoardOutline, Router, ViaStitcher, ZoneFiller

output/ — KiCad v7 s-expression emitter, Gerber/drill/SVG export

verify/ — DRC: clearance checks, violation reporting

7-step internal pipeline: Stackup → Board outline → Place components → Route traces (MST-based) → GND stitching → Copper zones → Write PCB. First render: 46 components placed, 488 traces routed, 98 GND vias, 2 zones, 43 real AutoPhi-library footprints.

KiCad Project

Artefact Detail

Schematic 19 components, 96 distinct nets, 434 net-map entries; validated by kicad-cli (KiCad 10)

PCB layout M.2 22110 outline (22 × 110 mm); 4-layer 0.8 mm (prototype) / 6-layer 1.5 mm (production)

Schematic generator build_schematic.py (~2,388 lines); data-driven SD slot count; emits .kicad_sch directly

PCB generator build_pcie8.py with --append-to flag; calls autophi_engine

PCB merger merge_pcb.py; paren/string-aware S-expression walker; net-number remapping

Custom footprints 22 KiCad footprint files in AutoPhi.pretty (DS160PR810, DS280BR810, TPS7A4700, LP3878, TPD4E004, TPS735, BGA-256, PCIe x16 edge, etc.)

Pin maps (JSON) lfe5um5g_25f_pins.json (381 balls), tps65987_pins.json, tps62810_pins.json, tps62085_pins.json, ds80pci800_pins.json, mt41k512m16_pins.json

Pin constraints autophi_ecp5_sd_array.lpf (LOCATE + LVCMOS33 PULLMODE=UP for 28 SD signals)

TI Reference Design Library (487 Reference Documents)

The package includes a comprehensive corpus of ingested Texas Instruments application notes, datasheets, and reference-design documents covering PCIe redrivers, LDO/buck regulators, SD interfaces, AES implementation, and signal-integrity guidelines. Key references include the TIDA-00423 DS80PCI810 PCIe redriver reference design (board file + schematic carried in the tidrd14/ folder).

Bill of Materials (Prototype)

Ref Qty Part Manufacturer Package

U1 1 LFE5UM5G-25F-8BG381C FPGA controller Lattice Semiconductor caBGA-381 17×17 mm, 0.8 mm pitch

U2 1 MT41K512M16HA-125:E DDR3 1 GB Micron FBGA-96 9×14 mm

U3 1 W25Q256JVEIQ SPI boot flash 256 Mbit Winbond SOIC-8

J2–J5 4 DM3D-SF microSD card socket Hirose SMD push-pull

U12 1 TPS65987DDHRSHR USB-PD PMIC Texas Instruments QFN-56 7×7 mm

U13 1 TPS62810-Q1 buck 1.1 V (4 A) Texas Instruments VQFN-9 1.5×1.5 mm

U14 1 TPS62086 buck 2.5 V (3 A) Texas Instruments VSON-7 2×2 mm

U15 1 TPS62085 buck 1.35 V (3 A) Texas Instruments VSON-7 2×2 mm

U16 1 TLV741P LDO 1.35 V Texas Instruments SOT-23-5

U_RX 1 DS80PCI800 PCIe redriver (8 channels) Texas Instruments WQFN-54

U17 1 INA260 current/voltage/power monitor Texas Instruments TSSOP-16

U18 1 TMP1075 temperature sensor Texas Instruments WSON-6

Y1 1 25 MHz crystal (X322512MOB4SI) Yangxing Tech 3225 SMD 2-pin

F1 1 MF-MSMF150-2 polyfuse (1.5 A) Bourns 1812

D1 1 LTST-C190KGKT green LED Lite-On 0603

C_DEC ~70 100 nF X7R decoupling Samsung 0402

C_BULK ~15 10 µF X5R bulk Samsung 0805

C_PCIE_AC 8 200 nF X7R PCIe AC-coupling Murata 0603

L1–L4 4 1.0 µH inductor (SRP3010CA) Bourns 3×3 mm SMD

Spreader 1 C110 copper 22×100×0.58 mm (custom) —

Package Statistics

Metric Count

Total files in package 884

Source code files (.py, .v, .c, .h) 116

Total source lines of code ~23,961

Verilog RTL modules 35 files (~7,344 lines)

Firmware C modules 13 files (~722 lines)

Host driver C modules 5 files (~281 lines)

Python simulator modules 7 files (~654 lines)

AutoPhi PCB engine ~7,625 lines Python

KiCad generator scripts ~2,388 lines Python

KiCad custom footprints 22 .kicad_mod files

TI reference documents 487 files

JSON pin-map / table files 42

RTL verification results 41 PASS / 0 FAIL

Patent claims 20 (15 apparatus + 4 method + 1 means-plus-function)

Acquisition Tiers

Tier What Price

Mathematical Deposition (PDEPO) Formal proof + framework. NDA. Reading material only. $250,000

Evaluation License (EVAL) Hands-on evaluation, 90 days, NDA-gated. Fee credits toward Full Use & Copy. $1,500,000

Full Use & Copy License (ACQ) Commercial source license for the package. IP retained by CRI-ONE. $25,000,000

Full Acquisition Complete IP transfer. Buyer becomes the IP owner. $100,000,000

What Is in the Package

Folder / File Purpose

cri-one-pcie8-ssd/ The product: simulator, driver stack, KiCad PCB skeleton

cri-one-pcie8-ssd/architecture.md Full block diagram, memory map, signal flow, boot sequence, risk register

cri-one-pcie8-ssd/mechanical.md M.2 22110 form factor, copper spreader, component heights, stack-up

cri-one-pcie8-ssd/power.md Power budget, 5 rails, sequencing timeline, NVMe power states, telemetry

cri-one-pcie8-ssd/bom-tentative.csv Full parts list with manufacturer part numbers, packages, and sourcing

cri-one-pcie8-ssd/sim/wonderphi/ Python simulator: link, NAND, FTL, GC, wear leveling, NVMe queues, ACE compute

cri-one-pcie8-ssd/demos/demo_simulator.py End-to-end smoke test (round-trip, trim, GC, integrity check)

cri-one-pcie8-ssd/demos/demo_compute.py ACE near-data compute demonstration (VOXEL/SCAN/XFORM)

cri-one-pcie8-ssd/wonderphi-driver/ Three-layer driver: hardware (Verilog) + firmware (C) + software (Linux driver)

cri-one-pcie8-ssd/wonderphi-driver/commandments.h The WonderPhi Constitution — 10 Commandments (version 1.0.0, permanent)

cri-one-pcie8-ssd/wonderphi-driver/hardware/ 35 Verilog RTL modules (~7,344 lines): full controller from PHY to ACE

cri-one-pcie8-ssd/wonderphi-driver/firmware/ 13 freestanding C files (~722 lines): controller MCU firmware

cri-one-pcie8-ssd/wonderphi-driver/software/ 5 Linux host driver files (~281 lines): PCI enumeration, NVMe submission, ioctl

cri-one-pcie8-ssd/wonderphi-driver/Makefile Three-layer build: make all , make test , make aes-test , make verify

cri-one-pcie8-ssd/kicad/ KiCad 9/10 project: schematic (19 components, 96 nets), PCB, generators, notes

cri-one-pcie8-ssd/kicad/build_schematic.py Data-driven schematic generator (emits .kicad_sch)

cri-one-pcie8-ssd/kicad/build_pcie8.py PCB generator wrapper (calls autophi_engine)

cri-one-pcie8-ssd/kicad/merge_pcb.py Headless PCB merger for scripts / CI

cri-one-pcie8-ssd/kicad/generated/ Pin maps: ECP5 381-ball, DDR3 96-ball, TPS65987, DS80PCI800, etc.

cri-one-pcie8-ssd/kicad/notes/ Schematic block diagram, pin-level netlist, layout guidelines, mechanical notes

autophi_engine/ AutoPhi PCB board engine (~7,625 lines): RAG knowledge base, layout, output, verify

autophi_engine/rag/ti_references/ 487 TI reference documents (application notes, datasheets, design guides)

autophi_engine/footprints/AutoPhi.pretty/ 22 custom KiCad footprints

tidrd14/ TI TIDA-00423 DS80PCI810 PCIe redriver reference design (board + schematic)

part-stock-mcp/ MCP server for part-stock queries

bark/JLCPCB-4LAYER-NOTES.md JLCPCB 4-layer fabrication capabilities distilled

MANIFEST.json Machine-readable package metadata

PLAYBOOK.md Internal playbook: identity, acquisition tiers, milestones

CHANGELOG.md Full session-by-session development history

PATENT_NONPROVISIONAL.md Complete non-provisional utility patent application (20 claims, 8 figures)

WONDERPHI_LINEAGE.md AutoPhi lineage: driver model, WonderPhi AES, computational-storage pivot

INVENT_DEPOSITIONS.md 2015–2017 conception-root depositions (ISBN 9781979767897)

PRIOR_ART_QUERIES.md 9-phase Google Patents query plan for novel claims

LICENSE Proprietary license

CITATION.cff Citation metadata

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

'PHANTOM SPEED' M.2 SSD labelled 'PCIe Gen 8.0 x4' on a dark lab bench, plus a steel plate reading 'PHANTOM PCIe Gen8 Lab / Unit 1 - Auburn, GA'

Footnotes

Product number 8500.
Family: autophi pcie cards.
Purchase: When you buy, you buy the use of that blueprint only.

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