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75-1536-interposer

$7,859.10

In stock

SKU

2106

BGA-1536 Interposer: A* routes draw in with orthogonal steps from the BGA-1536 to the edges, over an exploded 12-layer copper stack, animated picture

Asset valuation: $8,000,000,000. This project now uses a reusable anchor standard for the primary BGA and left-edge IN/OUT connectors. - PCB edge left-bottom corner: (61.100, 114.650) mm - BGA center (U1): (141.500, 95.400) mm - BGA interchange window: 95.0 mm

For the curious

Think of a street laid out for one house that now has to carry a tower. The Texas Instruments TIDA-00423 reference card was drawn around a 256-ball chip twenty millimetres on a side. The AutoPhi BGA-1536 is ninety-five by ninety millimetres, 1,536 balls at two-millimetre pitch. Everything under it has to be laid again: copper, planes, escape routes, the connector at the bracket. This package is that work, done thirty-four times over: one routed board variant for each I/O bracket connector type.

The chip is defined here as a package rather than as fabricated silicon, and the interposer carries no patent filing of its own; what you buy is engineering work: design files, source code and documentation. One hundred and eighty files: fifty-seven Python scripts, twenty-three engineering documents, a 352-component bill of materials and thirty-four KiCad boards. The stackup grows through three scripted stages into twelve copper layers, eight of them routable, every signal layer facing an adjacent reference plane, on Megtron 6 at a standard 1.6 millimetres. The autorouter is custom: an A* grid-maze router grounded in a knowledge base of more than fifty citations, with differential-pair routing, BGA row-to-layer fan-out, congestion heatmaps, target-first routing and cached incremental runs with random retry. Every root script takes a timestamped backup before it touches the board.

It is for the accelerator-card team that wants a PCIe 5.0 carrier for a large package without starting from a blank sheet. The buyer walks away with the boards, the router and the method; the AutoPhi family they belong to stays with Christopher Gabriel Brown.

Details

Description

AutoPhi BGA-1536 Interposer — PCIe 5.0 Accelerator Board Design and Autorouter Package

Patents / Status: This package is part of the AutoPhi semiconductor product family. The BGA-1536 interposer is a design-stage silicon interposer and PCB accelerator-card package. No USPTO patent application has been filed for the interposer itself; the interposer is engineering IP delivered as design files, source code, and documentation. The AutoPhi chip described herein is a fictional IC defined only as a package; no physical silicon has been fabricated. Asset valuation: $40,000,000,000.

Overview

The AutoPhi BGA-1536 Interposer package is a complete PCB design-engineering archive for a high-density PCIe Gen 5.0 accelerator card built around the AutoPhi BGA-1536 ball-grid-array IC. The project forks the Texas Instruments TIDA-00423 PCIe Gen 3 x8 repeater/retimer reference design into 34 routed product variants , one per I/O bracket connector type, and upgrades the central processor package from BGA-256 (20×20 mm, 1.0 mm pitch) to BGA-1536 (95×90 mm, 2.0 mm pitch). The archive ships 180 files (6.0 MB) comprising 57 Python scripts (totalling approximately 14,000+ lines of code), 23 engineering-documentation Markdown files , 11 JSON data files , netlist and schematic outputs, shell scripts, Allegro import scripts, EasyEDA conversion data, and cached routing metrics. The package includes a fully custom A* grid-maze PCB autorouter grounded in a 50+ citation Retrieval-Augmented Generation (RAG) knowledge base, a 12-layer copper stackup engineering pipeline, a 352-component BOM, 34 KiCad board variants, and comprehensive routing-technique documentation covering differential-pair routing, BGA row-to-layer fan-out, congestion heatmap analysis, target-first routing, and cached incremental routing with random-retry.

BGA-1536 Interposer Specifications

Parameter Value

Package designator U1 (formerly BGA-256; upgraded to BGA-1536 via generate_schematic.py --bga-pinmap )

Package type BGA-1536 (Ball Grid Array, 1,536 balls)

Die / package size 95 × 90 mm

Ball pitch 2.0 mm

KiCad footprint AutoPhi:BGA-1536_95x90mm_P2.0mm

KiCad symbol AutoPhi_BGA1536_working.kicad_sym

Pinmap (template) pinmaps/AUTOPHI_BGA1536_pinmap_template.csv

Pinmap (working) pinmaps/AUTOPHI_BGA1536_pinmap_working.csv

BGA center placement (141.500, 95.400) mm from PCB origin

BGA interchange window 95.0 mm

Surface finish requirement ENIG (Electroless Nickel Immersion Gold) — required for BGA pads at 1.0 mm pitch and above

Breakout strategy Via-in-pad (POFV) — free on JLCPCB 6–20 layer boards

Row-to-layer fan-out 16 BGA rows pre-assigned across 5 signal layers (3 rows per layer)

PCB Stackup — 12-Layer Copper (Final Configuration)

The board progresses through three stackup evolution stages, each implemented by a dedicated Python script. The final configuration is a 12-layer stack with 8 routable signal layers and 4 reference/power planes, every signal layer referenced by at least one adjacent plane.

Layer KiCad Name Type User Name Cu Weight Purpose

L1 F.Cu Signal TOP 1.0 oz Top components, fan-out, stubs (microstrip, ref’d to GND1)

L2 In1.Cu Power GND1 0.5 oz Solid GND reference plane for L1/L3

L3 In2.Cu Signal SIG1 0.5 oz PCIe TX stripline (ref’d to GND1 above)

L4 In3.Cu Signal SIG2 0.5 oz PCIe RX stripline (ref’d to POWER1 below)

L5 In4.Cu Power POWER1 0.5 oz +3.3V plane

L6 In5.Cu Signal SIG5 0.5 oz Additional signal routing (ref’d to POWER1 above) — added by stackup_12layer.py

L7 In6.Cu Signal SIG6 0.5 oz Additional signal routing (ref’d to POWER2 below) — added by stackup_12layer.py

L8 In7.Cu Power POWER2 0.5 oz 1V0 core rail plane

L9 In8.Cu Signal SIG3 0.5 oz I2C, SPI, JTAG, sideband routing (ref’d to POWER2 above)

L10 In9.Cu Signal SIG4 0.5 oz Spare routing, LEDs (ref’d to GND2 below)

L11 In10.Cu Power GND2 0.5 oz Solid GND reference plane for L10/L12

L12 B.Cu Signal BOTTOM 1.0 oz Bottom components, decoupling (microstrip, ref’d to GND2)

Material: Megtron 6 (Dk=3.15, Df=0.002) with HVLP2 copper foil. Total board thickness: 1.6 mm (standard JLCPCB). Dielectric thickness: 0.10 mm per layer pair.

Stackup Evolution Scripts (Root-Level)

The root directory contains 8 Python scripts that operate directly on the BGA-1536 board file ( autophi-pcie5-qsfp28-optical-1536-FILLED.kicad_pcb ). Each script creates a timestamped backup before modifying the board.

Script Lines Purpose

add_signal_layers.py 107 Adds 4 inner signal layers (In5–In8, SIG1–SIG4) to expand from 6 copper layers (2 routable) to 10 copper layers (6 routable). Inserts layers before B.Cu. Preserves all existing tracks, zones, vias, and footprint layer assignments.

interleave_stackup.py 167 Reorders the 10-layer stack so every signal layer has an adjacent reference plane. Executes a two-phase rename through placeholders to handle permutation overlaps (e.g., In2→In4 while In4→In8). Only safe on boards with zero tracks and zero vias.

stackup_12layer.py 162 Expands from 10 to 12 layers by inserting two additional signal layers (SIG5, SIG6) at positions L6/L7 between POWER1 and POWER2. Takes routable signal count from 6 to 8. Remaps In5→In7, In6→In8, In7→In9, In8→In10 with two-phase placeholder substitution.

set_plane_layer_types.py 107 Declares four inner copper layers (In1–In4) as power type in the KiCad board file. Fixes the Freerouting 2.2.4 NullPointerException at DsnFile.adjustPlaneAutorouteSettings(DsnFile.java:88) which crashes on any DSN containing (plane ...) entries while no layer is declared (type power) .

patch_dsn_planes.py 88 Patches an exported Specctra DSN file to mark the four plane-bearing inner layers (GND1, POWER1, POWER2, GND2) as (type power) instead of (type signal) . Includes Freerouting command-line invocation template with -Xmx16g -XX:+UseG1GC JVM flags.

fix_power2_net.py 109 Repoints the POWER2 copper pour (In3.Cu) from the 8-pad +1V0 net to the 192-pad 1V0 core rail. Corrects a named-net mismatch artifact from the Allegro conversion.

fix_empty_refs.py 129 Assigns reference designators to 5 unnamed footprints (3 dimension annotations → DIM1–DIM3; 2 mounting holes → MH3/MH4) that block Specctra DSN export with “empty reference designator” errors.

delete_empty_keepouts.py 103 Removes 4 keepout zones with zero-vertex polygons (degenerate leftovers from Allegro conversion) that cause Freerouting winding-number warnings.

fix_3d_model_paths.py 122 Repoints 26 stale 3D model references from a dead D: drive path to ${KIPRJMOD}/../../../autophi_engine/footprints/AutoPhi.3dshapes/ . Rebuilds each footprint’s FP_3DMODEL list via the pcbnew Python API. Affected parts: DS80PCI810 retimers, DDR3 ICs, regulators, ESD arrays, test points.

dsn_roundtrip.py 83 Headless Specctra DSN export and SES import via KiCad’s pcbnew Python API ( ExportSpecctraDSN / ImportSpecctraSES ). Requires KiCad 10 bundled Python interpreter.

Fabrication Design Rules (JLCPCB-Grounded)

Rule Design Value JLCPCB Minimum RAG Citation

Trace width 0.127–0.500 mm 0.09 mm [21][22]

Trace space 0.090–0.300 mm 0.09 mm [21][22]

Via drill 0.20 mm 0.20 mm [21][22]

Via pad 0.45 mm 0.45 mm [21][22]

Annular ring 0.15 mm 0.15 mm [21][22]

Via-to-via clearance 0.127 mm 0.127 mm [21][22]

Soldermask dam 0.10 mm 0.10 mm [22]

Silkscreen line width 0.15 mm 0.15 mm [22]

Max hole aspect ratio 8:1 (0.20 mm drill / 1.6 mm board) 10:1 [21]

Impedance Targets

Signal Type Target Z Tolerance Routing Layers

PCIe Gen 5 differential 85 Ω ±10% L3 (In2.Cu), L4 (In3.Cu) — stripline

Single-ended signals 50 Ω ±10% L1 (F.Cu), L12 (B.Cu) — microstrip

DDR3 differential 100 Ω ±10% L3 (In2.Cu), L5 (In4.Cu)

Chiplet Integration — Component Inventory (352 Parts)

Ref Device Package Side Role

U1 AutoPhi BGA-1536 BGA-1536, 95×90 mm, 2.0 mm pitch Front Central processor / accelerator IC

U2–U5 DS160PR810 QFN-64, 8×8 mm Front PCIe Gen 5 retimers (4 channels)

U6–U7 LP3878 SOT-23-5 Front Low-dropout voltage regulators

U8 DS80PCI810 QFN-64 Front Additional PCIe retimer

U12–U14 Power management ICs Various Back Power tree / telemetry

U20 iCE40UP5K QFN Front Lattice FPGA for sideband logic

U21–U24 Telemetry / clock ICs Various Back Current sense, clock generation

U25–U28 Optical / thermal controllers Various Back Laser drivers, TEC controllers

U30 SPI flash SOIC-8 Front Configuration storage

U40–U41 PCIe retimer / redriver Various Front Signal conditioning

U42–U44 Power / compute ICs Various Front/Back MSP430, power sequencing

U45–U52 ESD protection arrays SOT-23 Back 8-channel ESD clamping

U53–U60 Optical / telemetry support Various Back Photodiodes, TIAs, clock buffers

U63–U66 DDR3 SDRAM FBGA-96, 11×15 mm Front DDR3-1600 memory bank (4 devices)

J1 PCIe x16 edge connector 164-pin edge fingers Bottom Host interface

J2, J3 I/O bracket connectors Variant-specific (34 types) Front External I/O (QSFP28, SFP+, USB-C, HDMI, etc.)

J4 WonderPhi expansion Header Front Auxiliary expansion connector

J10, J11, J14 Auxiliary connectors Various Back Power input, debug, SoM interface

SW1–SW8 DS80PCI810 strap switches Various Back Retimer configuration straps

MH1–MH6 Mounting holes 3.2 mm plated — Mechanical mounting (3 mm keepout zones)

C1–C331 Decoupling capacitors 0201–0805 Both 128 caps in rings around U2–U5 (32 each), 20 around U1, 8 bulk around U6/U7

R1–R34 Resistors 0402–0805 Both Pull-ups, pull-downs, termination. RT9–RT34: 26× 49.9 Ω 0402 terminators under U1 BGA on back side

RT1–RT8 NTC thermistors 0402 Front Temperature sensing at inter-chip gaps

FB1–FB10 Ferrite beads 0402–0805 Both Power rail filtering

D1–D4 Power LEDs 0805 Front Status indicators at (143, −40/−35/−30/−25)

CE1–CE4 Bulk capacitors Radial Both Bulk energy storage

CS1–CS4 Supercapacitors Various Both Holdup power

TEC1–TEC2 TEC modules Custom Front Thermoelectric cooling (post-reflow manual placement)

LED1 High-power LED Custom Front Optical emitter

TP1–TP6 Test points Pad Front Debug probe access in left corridor between J2/J3

Placement Standard

Parameter Value

PCB edge left-bottom corner (61.100, 114.650) mm

BGA center (U1) (141.500, 95.400) mm

BGA interchange window 95.0 mm

U1 → edge vector (80.400, −19.250) mm

J2 offset from U1 (−75.817, −12.461) mm

J3 offset from U1 (−75.817, +15.539) mm

Front-side clearance 4.0 mm edge-to-edge minimum

Back-side clearance 2.0 mm edge-to-edge minimum

A* Grid-Maze Autorouter ( auto_route.py — 1,749 lines)

A fully custom PCB autorouter built from scratch, using A* pathfinding on a rasterized grid. The router is grounded in a RAG knowledge base ( autophi_engine/rag/routing.py , 1,204 lines, 50+ citations from Sierra Circuits, Altium, JLCPCB, NXP, UltraLibrarian, Howard Johnson’s “High-Speed Digital Design,” and others).

Router Parameter Value

Grid cell size 0.12 mm (best run) / 0.15 mm (default)

Grid dimensions 1,642 × 602 cells

Connectivity 4-connected (orthogonal only — DRC-safe; diagonals disabled after 10,333 violation analysis)

State key (cell_x, cell_y, layer)

Per-net timeout 8–20 s (configurable)

Max A* queue size 1,000,000 entries

Retry budget 1,500 s (with 2× timeout and random pad order shuffling)

GND via stitching 5.0 mm grid, ~200 stitch vias per board

Route cache Persistent JSON per board directory; warm re-run ~30 s vs ~20 min cold

A* Cost Model (Per Net Class)

Move Type Cost Notes

Straight (same direction) 1 Orthogonal only

Turn (direction change) 1–5 Class-dependent; reduced to 1 for minimum-length paths

Via (layer change) 4–20 Span-scaled: short-hop vias cost 60% of full-span; encourages nearby layers

Via-in-pad (at BGA start/goal) 1 POFV free at JLCPCB on 6L+

Other-net cell 999 Effectively blocked

Net Class Definitions (19 Classes, Priority-Ordered)

Priority Class Trace Width Clearance Key Parameters

0 pcie_diff 0.127 mm (5 mil) 0.127 mm P–N gap 0.127 mm; intra-pair skew max 0.127 mm; inter-pair skew 1.27 mm; guard 0.508 mm (5W); max 4 TX / 2 RX via pairs; 85 Ω diff impedance

1 refclk 0.127 mm 0.127 mm P–N gap 0.127 mm; inter-pair skew 0.508 mm (tighter); diff coupled

2 ddr_strobe 0.152 mm 0.09 mm Diff pair; diff_gap 0.152 mm; intra skew 0.127 mm; inter skew 0.635 mm

3 ddr_clock 0.152 mm 0.09 mm Diff pair; inter skew 0.381 mm vs strobes

4 ddr_data 0.152 mm 0.09 mm Single-ended; intra lane skew 0.508 mm; 8-bit byte lanes

5 ddr_addr 0.152 mm 0.09 mm Intra skew 1.27 mm

6 ddr_ctrl 0.152 mm 0.09 mm CAS/RAS/WE/CS/CKE/ODT/RESET; intra skew 1.27 mm

7 io_ingress 0.152 mm 0.09 mm SmartNIC offload bus; 100 mil loose skew

8 pcie_sb 0.200 mm 0.09 mm PERST/PRSNT/SM/WAKE sideband; loose skew

9 strap 0.200 mm 0.09 mm DS80PCI810 config straps

10 jtag 0.200 mm 0.09 mm IEEE 1149.1 JTAG debug

11 spi 0.200 mm 0.09 mm SPI flash + config

12 i2c 0.200 mm 0.09 mm I2C sideband

13 uart 0.200 mm 0.09 mm UART console

14 sdio 0.200 mm 0.09 mm SD card bus

15 thermal_hv 0.500 mm 0.300 mm TEC + LED high-current paths

16 analog 0.200 mm 0.09 mm Current sense + thermistors

17 usb_pd 0.200 mm 0.09 mm USB-PD CC lines

100 default 0.200 mm 0.09 mm Everything else

Routing Techniques (6 Documented Methods)

Technique Document Description

DRC-Safe Mechanism ROUTING_DRC_MECHANISM.md Orthogonal-only routing + clearance halos + cache replay. Discovered through 8 failure iterations reducing violations from 76,643 to ~348. Clearance halo formula: trace_halo_cells = max(1, ceil((trace_width/2 + min_clearance) / grid_mm)) .

Differential Pair ROUTING_TECHNIQUE_DIFF_PAIR.md P routes first via A*, N immediately follows on same layer with P’s cells blocked, guaranteeing impedance match, skew match, and adjacent coupling. 65–71 diff pairs detected per board via *_P / *_N pattern matching.

Row-to-Layer Fan-Out ROUTING_TECHNIQUE_ROW_LAYER_FANOUT.md BGA-256 rows (A–T) pre-assigned to dedicated signal layers (~3 rows per layer). Via-in-pad drops net to assigned layer immediately. Improved routing from 66.8% to 83.2%.

Cached Incremental ROUTING_TECHNIQUE_CACHED_INCREMENTAL.md Persistent JSON route cache per board. Cache hit replays path + marks halos instantly. Cache miss runs A*. Warm re-run: ~30 s vs ~20 min cold. Self-healing: stale entries silently invalidated. Random-retry recovers 30–70% of first-pass failures.

Target-First ROUTING_TECHNIQUE_TARGET_FIRST.md Reorders pad list so non-BGA pads come first. Routes INTO the congested BGA breakout zone from periphery while channels are still available, rather than competing for limited escape channels.

Congestion Heatmap ROUTING_TECHNIQUE_CONGESTION_HEATMAP.md Records A* failure points in a congestion map. Reports top-10 hotspot cells with coordinates, hit counts, and blocker net names. Primary hotspot: DDR address bus corridor at x=243.7 mm.

34 I/O Bracket Variants

All 34 boards share the same core PCB (TI TIDA-00423 outline, identical IC/retimer/DDR layout). They differ only in the I/O bracket connector at J2/J3. Core routes propagate from board 01 to all variants via propagate_routes.py .

# Key Connector Protocol Market

01 qsfp28-optical QSFP28 cage 100G Ethernet Data center

02 sfp-optical SFP+ cage 10G Ethernet Telecom

03 usb-c USB-C receptacle USB 3.2 / USB4 Consumer

04 rj45-ethernet RJ-45 jack 1G Ethernet General

05 hdmi HDMI Type-A HDMI 2.1 Display

06 microsd microSD slot SD 4.0 Storage

07 uart-serial DB-9 / header RS-232 UART Debug

08 rs485-industrial Terminal block RS-485 Industrial

09 sma-rf SMA female DC–18 GHz RF Test/measurement

10 i2c-spi-exp 2x10 header I2C + SPI Expansion

11 qsfp-dd-400g QSFP-DD cage 400G Ethernet Hyperscale DC

12 osfp-800g OSFP cage 800G Ethernet Next-gen DC

13 lc-duplex-fiber LC duplex Multimode fiber Campus LAN

14 cwdm4-100g QSFP28 CWDM4 100G WDM Metro WAN

15 usb4-40g USB4 Type-C USB4 40 Gbps Thunderbolt

16 thunderbolt4 Thunderbolt 4 TB4 40 Gbps Pro workstation

17 rj45-10gbaset RJ-45 10G 10GBASE-T Enterprise

18 m12-x-ethernet M12 X-coded Industrial Ethernet Factory floor

19 displayport2 DP 2.0 DisplayPort 2.0 8K display

20 mipi-csi2 FPC connector MIPI CSI-2 Camera/vision

21 rs232-db9 DB-9 male RS-232 Legacy serial

22 can-bus-db9 DB-9 CAN 2.0B / CAN-FD Automotive

23 bnc-dual Dual BNC Video / sync Broadcast

24 n-type-rf N-type female DC–11 GHz High-power RF

25 jtag-20pin 2x10 header IEEE 1149.1 JTAG Debug

26 swd-10pin 2x5 header ARM SWD Debug

27 dc-barrel-12v 5.5×2.1 mm barrel 12V DC power Standalone

28 xt60-power XT60 connector High-current DC Robotics/drones

29 lemo-b-medical LEMO B-series Medical I/O Medical devices

30 mil38999-aerospace MIL-38999 Mil-spec I/O Aerospace/defense

31 dsub25-gpio DB-25 female 25× GPIO General purpose

32 iolink-m12 M12 A-coded IO-Link Smart sensors

33 sma-diff-clock Dual SMA Diff clock I/O Clock distribution

34 audio-trs 3.5 mm TRS + 6.35 mm Analog audio Audio processing

Pipeline Scripts — Blueprints Directory (57 Python Scripts)

Core Pipeline

Script Lines Purpose

auto_route.py 1,749 A* maze router: grid routing, diff-pair, row-to-layer, DRC halos, cache, retry, GND via stitching

fork_ti_board.py 2,087 Fork TI TIDA-00423 into 34 .kicad_pcb variants; flatten top edge; zone-pack 37 extra RAG-canonical parts

build_all.py ~200 Master pipeline orchestrator: fork → place → route → DRC → export. One-command build

drc_check.py 349 Post-route clearance verification: trace-to-trace, via-to-via, via-to-trace distance checks

render_board_svg.py 657 Direct SVG renderer: front/back split, ratsnest, layer colors (gold=front, cyan=back)

Placement

Script Lines Purpose

place_passives_clustered.py 311 Picture-frame bypass capacitor placement around ICs

resolve_collisions.py 229 Force-directed iterative collision resolution

auto_place.py ~300 Automatic component placement using pinned coordinates from placement.json

snap_passives.py ~150 Snap passives to grid

fix_placement.py ~200 Placement validation and repair

build_placer_v2.py ~300 Second-generation placement builder

apply_bga_io_standard.py ~200 Apply canonical BGA + I/O connector anchor standard to all variants

tetris_slot_finder.py ~200 Tetris-style slot-finding algorithm for component packing

Routing Support

Script Lines Purpose

propagate_routes.py ~200 Copy core routes from board 01 to all 34 variants

route_until_complete.py ~150 Iterative retry wrapper with convergence tracking

kicad_to_dsn.py 667 KiCad .kicad_pcb → Specctra DSN exporter (for Freerouting/TopoR/Allegro interop)

ses_to_kicad.py ~400 Specctra SES → KiCad importer

ti_trace_importer.py ~300 Import TI TIDA-00423 reference traces

autophi_live_router.py ~300 Live/interactive routing mode

add_via_wall.py ~200 Add via stitching walls for isolation

Netlist and Schematic

Script Lines Purpose

generate_schematic.py ~400 Generate .kicad_sch from templates with --bga-pinmap override for BGA-1536

skidl_autophi_v3.py ~500 SKiDL-based schematic generation from live PCB inventory; emits 16,624-line netlist, XML, 352-row BOM

extract_board_netlist.py ~200 Extract netlist from .kicad_pcb to board_inventory.json (352 parts, 323 nets, 2,390 pads)

fix_netlist.py ~200 Netlist validation and repair

ti_net_mapping.py ~300 TI TIDA-00423 ↔ AutoPhi net name translation tables

dsn_to_netlist.py ~200 Extract netlist from Specctra DSN

refresh_schematic_from_pcb.py ~200 Refresh schematic from PCB state

recover_schematic_from_history.py ~200 Recover schematic from version history

kicad_net_names.py ~100 Net name extraction and mapping utilities

DRC and Verification

Script Lines Purpose

autophi_drc_report.py ~200 Parse KiCad DRC JSON and generate summary reports

drc_platform/kicad_drc_json.py ~200 KiCad DRC JSON parser

drc_platform/text_report.py ~150 Text-format DRC report generator

drc_platform/aggregate.py ~100 DRC result aggregation

board_logical_audit.py ~200 Logical-level board audit

check_airwires_34.py ~100 Check unrouted airwires across all 34 variants

Output and Export

Script Lines Purpose

build_magento_34_boards.py ~300 Magento CSV with SKU mapping for all 34 board variants

domino_pipeline.py ~200 End-to-end product packaging pipeline

make_interactive_editor.py ~400 Generate HTML drag-and-drop placement editor

make_schematic_viewer.py ~200 Generate HTML schematic viewer (14 functional sections, color-coded nets)

package_boards.py ~200 Package board files for distribution

package_schematics.py ~200 Package schematic files

package_v18_v20.py ~200 Version 18/20 packaging

push_to_magento.py ~200 Push product data to Magento store

kicad_to_eagle.py ~300 KiCad → Eagle conversion

fix_ipc2581.py ~200 Fix IPC-2581 export data

Utilities

Script Lines Purpose

add_body_outlines.py ~150 Add component body silkscreen outlines

silkscreen_cleanup.py ~100 Optimize silkscreen placement

generate_pcb.py ~400 34 IO_CONNECTOR_DEFS + IO_BOARD_NAMES definitions

one_click_connector_variants.py ~200 One-click variant switching

profile_switch.py ~150 Profile switching between board configurations

make_airwire_copies.py ~100 Generate airwire display copies

run_34_one_shot.py ~100 Single-shot build of all 34 variants

easyeda_to_kicad.py ~200 EasyEDA format → KiCad conversion

extract_bga_footprint_to_pretty.py ~200 Extract BGA footprint to .pretty library

create_device_files.py ~200 Create device description files

generate_allegro_skill.py ~200 Generate Cadence Allegro SKILL import scripts

bom_csv_from_board_inventory.py ~150 Generate BOM CSV from board inventory JSON

compare_board_bom_to_reference.py ~150 Compare board BOM against TI reference

part_sourcing_fields.py ~100 Part sourcing field definitions

KiCad Action Plugin Suite (7 Plugins)

Seven KiCad 10.0 action plugins for interactive use in the PCB editor. Source: blueprints/kicad_plugin/autophi_router/__init__.py .

Plugin Function

Route Board Dialog-launched routing with configurable grid, timeout, diff-pair, POFV, row-to-layer, MH keepout, and target-first settings

Via Cascade Distance-based via layer-pair assignment:

DRC Check Post-route via-to-via clearance verification (0.09 mm min), capped at 1,000 violations

Smart Place Moves bypass caps near connected IC power pins (targets 0201, 0402, 0805 passives, 2.0 mm offset)

Unroute All Strips all tracks and vias from the board for clean re-routing

Party Grid Place Grid-placement helper with configurable pitch (14 mm default), 22 columns, row/spiral mode, origin filter (30 mm)

Fancy Silk Outline Adds halo strokes around board-level silk text (8- or 16-way ring, offset + stroke-width control)

RAG Knowledge Base (50+ Citations)

The routing knowledge base ( autophi_engine/rag/routing.py , 1,204 lines) cites 50+ sources including:

Category Citations Sources

Online design guides [1]–[18] Sierra Circuits, PCBway, Altium, Eremex, AllPCB, Quilter.ai, FS-PCBA, UltraLibrarian, NXP AN10373, Toradex, Wikipedia, Advanced PCB

Textbooks [19]–[20] Johnson & Graham “High-Speed Digital Design: Black Magic” (1993); Zhang/Krooswyk/Ou “High-Speed Digital Design” (2015)

JLCPCB specifications [21]–[31] Manufacturing capabilities, design rules, impedance, copper weight, castellated PCBs, surface finish, BGA 0.4 mm pitch

TI reference design [32]–[33] TIDA-00423 PCIe x8 Gen3 repeater/retimer reference design (tidrd13.pdf)

Internal / local [47]–[50] AutoPhi DRC-Safe Mechanism (8 failure iterations); Geometry textbook (176 MB); Advanced Calculus (31 MB); Printed Circuit Boards 2005 (6.5 MB)

Documentation Files (23 Markdown Documents)

Document Subject

README.md Pipeline overview, script reference, command cheatsheet

HANDOFF.md Pipeline handoff guide: 6 architectural decisions, 8 bug fixes, 6 open TODOs

MANUFACTURING.md JLCPCB 10-layer fab specification (stackup, design rules, impedance, via policy, assembly)

VARIANTS.md 34-board I/O variant catalog with connector categories and build commands

BGA_IO_STANDARD.md Reusable BGA + I/O connector anchor coordinate standard

RULES_DDR_PCIE.md DDR3 and PCIe routing rules with per-class parameters

SCHEMATIC_PROCESS.md Three-stage schematic generation pipeline (extract → SKiDL → HTML viewer)

ROUTING_PROCESS.md 8-stage routing pipeline overview with cost model and grid configuration

ROUTING_RECURRING_PROCESS.md Repeatable session runbook for QSFP28 board routing with 7-step loop

ROUTING_CHECKPOINT_v7.md Router evolution history (v2–v7), 22-citation RAG architecture, JLCPCB constraints

ROUTING_DRC_MECHANISM.md DRC-safe mechanism documented through 8 failure iterations (76,643 → ~348 violations)

ROUTING_TECHNIQUE_DIFF_PAIR.md P+N differential pair routing: detection, flow, DDR byte lane grouping

ROUTING_TECHNIQUE_ROW_LAYER_FANOUT.md BGA row-to-layer pre-assignment (16 rows across 5 signal layers)

ROUTING_TECHNIQUE_CACHED_INCREMENTAL.md Route cache, random-retry, GND via stitching reservoirs, short-path optimization

ROUTING_TECHNIQUE_TARGET_FIRST.md Route from periphery toward BGA for better channel utilization

ROUTING_TECHNIQUE_CONGESTION_HEATMAP.md Congestion map construction, hotspot analysis, retry strategy

KICAD_PLUGIN.md 7 KiCad action plugin descriptions, installation, API notes

rag-pcb-knowledge-base.md Full RAG citation index (50+ sources)

TI_TIDA00423_COMPLETE_NETLIST.md Complete TI TIDA-00423 reference netlist documentation

Data Files

File Format Content

placement.json JSON Fixed-part coordinates (U1, J1–J3, U2–U7, MH1–MH6) with placement standard metadata

board_inventory.json / board_inventory_qsfp28.json JSON 352-part, 323-net, 2,390-pad board inventory extracted from live PCB

ti_netlist.json JSON TI TIDA-00423 original netlist data

TI_TIDA00423_COMPLETE_NETLIST.json JSON Complete reference netlist from TI design

TI_TIDA00423_NETLIST_EASYEDA.json / .csv / .net Multiple TI netlist in EasyEDA format for conversion

route_cache/run_metrics.jsonl JSONL Per-run routing metrics (routed/failed counts, timing)

autophi_netlist_v3.net KiCad NET 16,624-line netlist generated by SKiDL v3

autophi_netlist_v3.xml XML Structured netlist data (any EDA tool can read)

What Is in the Package

Category Count

Python scripts (.py) 57

Python bytecode cache (.pyc) 18

Engineering documentation (.md) 23

Data files (.json, .jsonl) 11

Netlist / ERC / schematic (.net, .erc, .log, .txt, .csv) 18

Shell scripts (.sh) 1

EDA interchange (.scr) 1

Backup files (.bak) 1

Total files 180

Total size 6.0 MB

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

Angled close-up of a large BGA package ball grid on a dark surface

Footnotes

Product number 8525.
Family: autophi pcie cards.
Purchase: When you buy, you buy the use of that blueprint only.

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