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76-qbeam-transfer

$6,876,712,500.00

In stock

SKU

2107

QBeam Transfer Card: two PCIe host bus adapters; bytes stripe across four QBeam lanes from Host A to Host B, animated picture

Asset valuation: $7,000,000,000. Project 76 · cri-one.com portfolio · Author: Christopher Gabriel Brown Quantum PHY is a PCIe host bus adapter that uses the patented QBeam physical layer as a plain wire — moving classical bytes (files, RDMA payloads, NVMe-oF, model weights, ledger writes) between e

For the curious

Imagine the link between your accelerator boards being a card you slide into an ordinary PCIe slot, with four QBeam lanes on the bracket. That is the Quantum PHY QBeam Transfer Card. QBeam was filed as a wireless quantum send-and-receive layer, and this card runs it in classical mode, as a plain wire: files, RDMA payloads, NVMe-oF, model weights and ledger writes move between AutoPhi boards in the same chassis, rack or row. No qubits go on the wire and nothing is teleported. The card borrows QBeam for what it does well with ordinary bytes. It stays operable from minus 40 to plus 85 degrees Celsius without active cooling, it absorbs lane-to-lane board skew without retraining, and it fits four lanes on a single-slot half-height bracket. The design target is 400 GB/s in both directions with a 400 ns cut-through budget from one host's doorbell to the other host's memory, and the host sees one PCIe function carrying 64 virtual functions.

This is for datacenter operators and the engineering buyers who build their fabric. The line is thirteen SKUs: twelve silicon generations from 7 nm to 2 nm, each with its own foundry hand-off, plus the reference board. On file are the full spec, bill of materials, 12-layer stackup, wire protocol, driver ABI, RTL scaffolding, link firmware in C, a host daemon in Rust and an SDK in C, Python and Rust. The buyer takes a foundry-ready package to a contract manufacturer for schematic capture, layout, fab, bring-up and compliance; the filed patent stays with the inventor.

Details

Description

76 — Quantum PHY QBeam Transfer Card (SKU 2107)

SKU: 2107 | Product slug: 76-qbeam-transfer | Categories: Quantum PHY, AutoPhi Boards / Interconnect / Silicon | Inventor: Christopher Gabriel Brown

Patent dependency (filed, non-provisional utility, pro se): USPTO Application 19/722,805 — INTEGRATED WIRELESS DATACENTER FABRIC WITH PHASED-ARRAY COOLING ANTENNA, ORDER-PRESERVING ANTENNA SERIES, AND QUANTUM-TELEPORTATION PROTOCOL ATOP A SHARED CLASSICAL CHANNEL (ExitPhi). Filed 2026-06-27 4:14:28 PM ET. 30 claims. Confirmation 4017. Patent Center 77974071. Canonical source for QBeam, CoolBeam, and PipeBeam technologies used in this card. Additional normative reference: USPTO Application 19/717,706 (UniPhi Retroactive Wireless Adapter, filed 2026-06-24) — endpoint adapter framing reference.

Status: Foundry-ready (L4). Full SPEC + BOM + 12-layer STACKUP + wire-protocol specification + host-driver ABI contract on file. Physical-design flow output present for all 12 silicon generations (APM01-D-QPHY through APM12-D-QPHY). Each generation ships a canonical 44-line FOUNDRY_HANDOFF.md. QBeam is a filed non-provisional USPTO utility patent. Patent alignment verified against ExitPhi patent text. ASIC RTL scaffolding, link firmware (C), host daemon scaffolding (Rust), and SDK source (C + Python + Rust) included. Reference-board BOM drafted to hand off to a contract manufacturer for schematic capture and layout. KiCad schematic capture, PCB layout, Gerber generation, prototype fab, bring-up, PCIe 5.0 PCI-SIG compliance, FIPS 140-3 crypto-module certification, and interop testing against AutoPhi endpoint boards are buyer/CM/cert-lab scope.

Overview

The Quantum PHY QBeam Transfer Card is a single PCIe 5.0 x16 half-height half-length (HHHL) host bus adapter (HBA) that presents the patented QBeam physical layer as a plain byte-oriented fabric interface. The card carries classical payloads only — files, RDMA, NVMe-oF, model weights, ledger writes, and control traffic — between AutoPhi accelerator boards housed in the same chassis, rack, or row. No qubits are placed on the wire. No teleportation is performed. The QBeam PHY silicon is reused for its classical-modulation properties (density, thermal integrity, cable-freeness) and nothing else.

The card sits in a standard PCIe 5.0 x16 slot. On the bracket side it exposes four QBeam lanes in SFF-8674 cages; on the host side it enumerates as a single PCIe function with SR-IOV support for up to 64 virtual functions . Design-target aggregate bandwidth is 400 GB/s bidirectional (4 lanes × 100 GB/s per lane) with a 400 ns cut-through latency budget from Host A doorbell write to Host B DMA write.

The product line comprises 13 purchasable SKUs : 12 silicon configurations (APM01-D-QPHY through APM12-D-QPHY, one per AutoPhi Modern generation, spanning 7 nm to 2 nm) plus the umbrella reference HBA board design. The reference HBA ships with the APM07-D-QPHY (3 nm, IFS 18A) as the mid-generation shipping baseline; any variant APM04 through APM12 drops in mechanically compatible.

Scientific Basis

The QBeam physical layer, invented and filed as part of the ExitPhi patent application (USPTO App# 19/722,805), was originally shown to modulate a quantum carrier for wireless quantum-to-quantum teleportation. Two invariants of the invention — CoolBeam thermal integrity and PipeBeam temporal alignment — are carrier-agnostic . When the classical-mode strap on the qbeam_lane macro is asserted, the analog front-end delivers a byte-oriented modulation with three measurable properties superior to copper-serdes or optical-fiber alternatives:

Property QBeam Classical-Mode Advantage Conventional Alternative

Thermal envelope Operable −40 °C to +85 °C without active cooling (CoolBeam) Copper-serdes PHYs in the same PCIe CEM 5.0 slot budget typically require active cooling above +55 °C ambient

Length-mismatch tolerance PipeBeam re-aligner absorbs ±8 mil PCB skew across parallel lanes without lane-to-lane retraining Optical alternatives are more tolerant but at 10× cost

Cable-free density 4 lanes on a single-slot HHHL bracket, each carrying 100 GB/s (design target) Comparable InfiniBand HBA requires 4× QSFP-DD or 8× QSFP+ cages

System Context

The card connects AutoPhi accelerator boards (PCIe5-256, BGA256, PCIe5-1536, and related V19 catalog SKUs) across a QBeam fabric. Each host runs Linux or Windows. The fabric is defined as the collection of Quantum PHY HBAs plus the QBeam wire runs connecting them. Routing is fabric-local; each HBA knows its own Local Identifier (LID) and the peer LIDs on each of its 4 QBeam ports.

Mechanical Specifications

Parameter Value

Form factor PCI-SIG CEM 5.0 HHHL (half-height half-length), single-slot bracket

Card outline 167.65 mm × 68.90 mm (per CEM 5.0 §3.2)

PCIe finger edge Standard x16 gold fingers

Bracket contents 4× SFF-8674 QBeam cages (J1–J4), 4× bicolor green/red bracket status LEDs (LED1–LED4)

Mounting 2 mounting holes (MH1–MH2) per CEM 5.0 §3.4

Heatsink Custom passive aluminium heatsink (HS1), 35×35×15 mm fin, with 3 W/mK thermal interface material (PAD1, 0.5 mm)

Custom bracket Single-slot HHHL bracket (BR1) with LED windows + SFF-8674 pass-through

Host Interface

Parameter Value

Standard PCI Express Base 5.0 (r5.0 v1.0)

Link width x16

Bandwidth per direction 63 GB/s

Virtualization SR-IOV, 64 Virtual Functions (VFs)

Queue pairs (PF) 16 (16 Submission Queues + 16 Completion Queues)

Queue pairs (per VF) 16 × 64 VFs = 1,024 VF QPs; plus 16 PF QPs = 1,040 total

Queue depth Buyer-configurable: 64 to 65,536 entries per queue

SQE size 64 bytes

CQE size 32 bytes

Interrupt model MSI-X: 32 vectors on PF, 4 per VF. Coalescing: 0–255 completions or 0–65,535 µs. Poll mode supported.

PCIe Vendor ID 0x1CE1 (allocated to cri-one; TBD upon PCI-SIG allocation)

PCIe Device ID 0x76CA (Quantum PHY QBeam Transfer Card, FCBGA-1024 flagship)

Class code 0x028000 (Network Controller / Other)

BAR Layout

BAR Size Purpose

BAR 0 64 KiB Control MMIO: registers, doorbells, event ring, VC configuration, counters

BAR 2 2 MiB (64-bit) Per-VF doorbell pages (32 KiB × 64 VF)

BAR 4 16 MiB (64-bit) Per-queue MMIO windows

QBeam Fabric Interface

Parameter Value

Bracket ports 4× QBeam lanes in SFF-8674 cages (J1–J4), inventor-defined pinout

Aggregate bandwidth (design target) 400 GB/s bidirectional (4 lanes × 100 GB/s per lane)

Cut-through latency budget 400 ns (Host A doorbell → Host B DMA write)

Byte striping 8-byte granularity across 4 QBeam lanes, PipeBeam-aligned

ESD protection 16× TPD4EUSB30 (uQFN-10) on J1–J4 cages

Bracket LED Behaviour

LED State Meaning

Green solid Link up, no FEC corrections

Green blinking Link up, active traffic

Amber FEC correcting frames

Red Link down or PHY reset

Wire Protocol (QPHY-P1)

Parameter Value

Protocol name QPHY-P1 (inventor-defined; not InfiniBand, RoCE, NVLink, or CXL compatible at the wire level)

Frame format 32-bit header + 16-byte payload prefix + variable payload body (64 B–4,096 B) + 128-bit trailer

Header fields dst_lid (16 bits) + src_lid (16 bits)

Payload prefix fields opcode (1 B), vc (1 B), flags (2 B), seq (4 B), xid (4 B), length (4 B)

Trailer 128-bit AES-256-GCM authentication tag over (header || prefix || body)

FEC Reed-Solomon RS(255, 239) per lane — corrects up to 8 symbol errors per 239 data symbols; block boundary aligned to frame boundaries

Encryption AES-256-GCM at link-layer; per-fabric key provisioned out-of-band via MMIO; nonce = (src_lid || dst_lid || seq) padded to 12 bytes

Key rotation Host-driven atomic KEY_EPOCH control write; drain-and-switch; no frames encrypted under two keys simultaneously

Flow control Credit-based: 64 credits per virtual channel per direction; 1 credit = 1 frame (any payload size)

Virtual channels 8 VCs, head-of-line independent; VC 0 reserved for control

Sequence numbers 32-bit per-VC per-direction, monotonically increasing; no wrap at 400 GB/s for ~112 hours

Ordering In-order within each VC; no ordering across VCs

Retransmission No on-wire ARQ; retransmission is above-SDK (application-layer)

Encoding Little-endian; least-significant-lane-first striping

Wire Opcodes

Opcode Value Meaning

DATA 0x01 Application payload transfer

CREDIT_GRANT 0x02 Credit replenishment (8 bytes: vc + reserved + new_credits)

LINK_HELLO 0x03 Sent on link up; 16-byte LID negotiation record

LINK_ACK 0x04 Reply to LINK_HELLO with accepted LID and initial credit grant

EVENT 0x05 32 bytes: code(4) + vc(1) + reserved(3) + data(24)

FLR_BARRIER 0x06 Both ends drain, reset state, resume with fresh credit grant

Virtual Channel Assignments (Recommended Defaults)

VC Suggested Traffic

0 Control (reserved)

1 High-priority latency-sensitive (small RDMA, doorbells)

2 RDMA WRITE / READ payload

3 NVMe-oF I/O

4 Bulk copy (file replication)

5 Model-weight broadcast

6 Ledger writes (Super Dome integration)

7 Best-effort / user-defined

SQE Opcodes (Host-Side)

Opcode Value Meaning

DATA 0x01 Generic data transfer

RDMA_WRITE 0x10 RDMA write to peer remote address

RDMA_READ 0x11 RDMA read from peer remote address

NVMEOF_IO 0x20 NVMe-over-Fabrics I/O command

CONTROL 0x30 Control-plane operation

Silicon — APM01-D-QPHY Link Controller

The APM01-D-QPHY is a variant of the APM01-D Nexus Core (Data Processing Unit) from the AutoPhi Modern family. The variant swaps the Nexus Core’s baseline 2× 400 GbE MACs for 4× QBeam classical-mode PHY lanes , adds a PCIe 5.0 x16 endpoint , and upgrades the AES-256-GCM crypto engine to per-lane parallel. All other Nexus Core features are retained: 8 Light Trigger cores, 32 programmable packet processors, hardware compression (LZ4, Zstd), regex/pattern-matching engine, NVMe-oF target/initiator (32 queues), RAID/erasure-coding engine, RDMA (RoCEv2-shim) queue pairs, and a 512-neuron anomaly-detection co-processor.

No third-party ISA licenses. American Made. Nine Ultimate Technologies present per AutoPhi Modern family contract.

On-Chip Block Diagram

Block Function

PCIe Gen5 x16 Endpoint Host bus interface, SR-IOV (64 VF)

DMA Engine 16 SQ / 16 CQ per PF; scatter-gather; 16 queues

Doorbell Host-writable MMIO; 32-bit write = new SQ tail

MAC Framing, CRC, RS(255,239) FEC per lane

Crypto AES-256-GCM per-lane parallel encryption/decryption

PipeBeam Aligner Stripe/de-stripe across 4 QBeam lanes at 8-byte granularity

QBeam PHY (4× TX+RX) Physical-layer modulation, CoolBeam-clocked for thermal integrity

Boot ROM Boots from on-card SPI flash (U3)

Event Ring + Counters 16 × 8-byte event ring; frames TX/RX, credits, FEC, auth counters

Silicon Generational Fade (12 Configurations)

SKU Gen Process Foundry Die Side (mm) Thickness (mm) Active Layers Peak GB/s (Design Target) Fade vs APM01

APM01-D-QPHY 01 7 nm IFS 7nm / TSMC N7 9.75 1.0 50–125 100 1×

APM02-D-QPHY 02 7 nm IFS 7nm / TSMC N7 — 1.0 — 200 10×

APM03-D-QPHY 03 7 nm IFS 7nm / TSMC N7 — 2.0 — 300 30×

APM04-D-QPHY 04 5 nm IFS 5nm / TSMC N5P — 2.5 — 400 80×

APM05-D-QPHY 05 5 nm IFS 5nm / TSMC N5P — 3.5 — 500 150×

APM06-D-QPHY 06 4 nm IFS 20A — 4.0 — 600 350×

APM07-D-QPHY 07 3 nm IFS 18A 7.25 5.0 700–1,000 400 700×

APM08-D-QPHY 08 3 nm IFS 18A — 6.0 — 800 1,000×

APM09-D-QPHY 09 2 nm IFS 14A — 7.0 — 1,200 3,000×

APM10-D-QPHY 10 2 nm IFS 14A — 8.0 — 1,600 5,000×

APM11-D-QPHY 11 2 nm IFS 14A — 10.0 — 2,400 10,000×

APM12-D-QPHY 12 2 nm IFS 14A 6.75 12.0 2,400–3,430 4,000 18,000×

APM07-D-QPHY (bold) is the shipping baseline of the reference HBA. Package: FCBGA-1024, 35×35 mm. Any variant APM04 through APM12 drops in mechanically compatible. Package families across the line: QFN-56 (single-lane variant), BGA-324 (dual-lane variant), FCBGA-1024 (flagship 4-lane variant).

Reference HBA Board (QPHY_HBA_BOARD)

Bill of Materials — Active Components

Ref Qty Part Package Vendor Function

U1 1 APM07-D-QPHY [custom] FCBGA-1024, 35×35 mm Intel Foundry Services (IFS 18A) Link controller: 4× QBeam PHY + MAC + DMA + PCIe5 x16 EP + AES-GCM

U2 1 MCP2517FD QFN-14 Microchip I²C ↔ CAN bridge (BMC sideband)

U3 1 W25Q128JW WSON-8 Winbond 128 Mbit SPI NOR — APM01-D-QPHY boot flash

U4 1 24AA256 SOIC-8 Microchip 256 kbit I²C EEPROM — board serial + Vital Product Data

U5–U6 2 TPS53681 VQFN-40 TI 2-phase controller — VCC_CORE (0.85 V, 24 A max)

U7 1 TPS53819A QFN-16 TI Single-phase controller — VCC_MAC (0.95 V, 9 A max)

U8 1 TPS53819A QFN-16 TI Single-phase controller — VCC_PHY (1.10 V, 12 A max)

U9 1 TPS62130 QFN-16 TI Buck converter — VDDIO (1.80 V, 3 A max)

U10 1 LP38853S DDPAK-5 TI LDO — VDDA (3.30 V, 1.5 A max)

U11 1 LP5907 SOT-23-5 TI LDO — VBMC (3.30 V, 0.2 A max)

U12 1 INA260 TSSOP-16 TI Power monitor on VCC_CORE rail

U13 1 TMP1075 SOP-8 TI Temperature sensor near U1

Power System

Rail Voltage Current (typ / max) Regulator Purpose

VCC_CORE 0.85 V 18 A / 24 A 2× TPS53681 (2-phase) APM01-D-QPHY core logic

VCC_MAC 0.95 V 6 A / 9 A TPS53819A MAC + DMA subsystem

VCC_PHY 1.10 V 8 A / 12 A TPS53819A PHY analog front-end

VDDIO 1.80 V 2 A / 3 A TPS62130 PHY digital I/O

VDDA 3.30 V 1.5 A / — LP38853S PHY reference / bandgap

VBMC 3.30 V 0.2 A / — LP5907 BMC + flash + LEDs

Power source: Slot-only (12 V + 3.3 V from the PCIe slot). No external power connector. Total board dissipation: 42 W typical, 68 W max (within the 75 W CEM 5.0 slot budget). U1 core dissipation: 38 W typical.

Clock Architecture

Source Frequency Consumer Notes

PCIe REFCLK (from slot) 100 MHz APM01-D-QPHY PCIe SerDes From host slot

Y1 (Rakon RPT7050A) 156.25 MHz APM01-D-QPHY MAC ±25 ppm

Y2 (Rakon RTX0100 LVDS) 312.5 MHz APM01-D-QPHY PHY reference ±0.5 ppm jitter (low jitter)

Y3 (Rakon TCXO) 25 MHz BMC + flash ±2 ppm

Connectors

Ref Qty Part Package Purpose

J0 1 PCIe 5.0 x16 finger Card edge Host interface (per CEM 5.0)

J1–J4 4 Amphenol SFF-8674 cage Bracket QBeam lanes 0–3 (inventor-defined pinout)

J5 1 Molex 22-28-4053 5-pin THT I²C sideband (unpopulated by default)

J6 1 Samtec FTSH-105-01-L-DV 10-pin SMT JTAG debug (unpopulated by default)

SW1 1 Omron B3W-4155 THT Recovery / factory-reset button (protrudes through bracket cutout)

Passive Components Summary

Type Qty Value Package Purpose

Ceramic X7R 384 0.1 µF 0402 Per-BGA-pin decoupling on U1

Ceramic X5R 24 22 µF 0805 Bulk on each power rail

Ceramic X5R 8 470 µF 1210 High-cap bulk on VCC_CORE

Ferrite bead 12 600 Ω @ 100 MHz 0402 Rail isolation between analog and digital

Resistors ~200 various 0402 Terminations, pull-ups, sense resistors

Diff-pair ESD 16 TPD4EUSB30 uQFN-10 On J1–J4 QBeam cages

ORing FET 2 CSD87381P SON Slot-power isolation

Thermal probes 4 LM45CIM3 SOT-23-3 At board corners (RN1–RN4)

Bracket LEDs 4 LTST-C171KGKT 0603 Bicolor green/red status (LED1–LED4)

Picture-frame bypass 20 0.1 µF 0402 Around U1

PCB Stackup (12-Layer)

# Layer Name Type Copper (oz) Dielectric (mil) Er Purpose

1 F.Cu Signal ½ 3.5 4.1 PCIe TX/RX diff pairs, top-side SMD

2 GND1 Plane 1 4.5 4.1 Reference plane for L1

3 Sig_In1 Signal ½ 4.5 4.1 QBeam TX/RX diff pairs (lanes 0–1)

4 GND2 Plane 1 4.5 4.1 Reference plane for L3 + L5

5 Sig_In2 Signal ½ 4.5 4.1 QBeam TX/RX diff pairs (lanes 2–3)

6 PWR_CORE Plane 1 4.5 4.1 VCC_CORE (0.85 V), heavy copper for 24 A

7 PWR_MAC_PHY Plane 1 4.5 4.1 VCC_MAC (0.95 V) + VCC_PHY (1.10 V) split-plane

8 GND3 Plane 1 4.5 4.1 Reference plane for L7 + L9

9 Sig_In3 Signal ½ 4.5 4.1 Control, sideband, low-speed signals

10 GND4 Plane 1 4.5 4.1 Reference plane for L9 + L11

11 Sig_In4 Signal ½ 4.5 4.1 MAC-DMA-Crypto internal routing, IO fanout

12 B.Cu Signal ½ — 4.1 Bottom-side SMD, MMIO decoupling caps under U1

Total thickness: 1.60 mm (±10%). Material: FR-4 Tg170, halogen-free. Surface finish: ENIG (0.05 µm Au over 3 µm Ni min). Solder mask: LPI green, both sides. Silkscreen: white epoxy, both sides. Flammability: UL 94V-0. Manufacturing class: IPC-6012 Class 6 (signal layers), IPC-A-600 Class 3 (finished appearance).

Impedance Targets

Signal Class Layer Trace / Space Impedance

PCIe 5.0 diff pair F.Cu (L1) 5 / 5 / 5 mil 85 Ω differential

QBeam diff pair Sig_In1 (L3), Sig_In2 (L5) 4 / 4 / 4 mil 100 Ω differential

Control single-ended Sig_In3 (L9) 4 mil 50 Ω

SPI + I²C + JTAG B.Cu (L12) 6 mil 50 Ω

Length Matching

Signal Group Match Tolerance

PCIe TX+ / TX− within a pair ±0.5 mil

PCIe RX+ / RX− within a pair ±0.5 mil

PCIe TX pair-to-pair (all 16 lanes) ±5.0 mil

QBeam TX+ / TX− within a pair ±0.2 mil (critical for PipeBeam alignment)

QBeam RX+ / RX− within a pair ±0.2 mil

QBeam lane 0/1/2/3 pair-to-pair ±2.0 mil (PipeBeam re-aligner handles up to ±8 mil)

DFM Constraints

Parameter Value

Minimum trace width 3.5 mil (85 µm)

Minimum trace spacing 3.5 mil

Minimum via drill 8 mil (200 µm)

Minimum drill-to-copper 6 mil (150 µm)

Minimum drill-to-drill 12 mil (300 µm)

Maximum aspect ratio (drill:board) 10:1

Back-drilling Required on all PCIe and QBeam vias; stub

Thermal Design

Parameter Value

U1 typical dissipation 38 W

Total board dissipation (typical / max) 42 W / 68 W

Heatsink Passive aluminium, 35×35×15 mm fin (HS1)

TIM 3 W/mK, 0.5 mm pad (PAD1)

Design airflow 200 LFM slot airflow at 55 °C ambient

Operating envelope (CoolBeam) −40 °C to +85 °C ambient without active cooling

Thermal probes 4× LM45CIM3 at board corners (RN1–RN4); 1× TMP1075 near U1

MMIO Register Map (BAR 0)

Offset Size Name R/W Function

0x0000 4 QPHY_ID R Magic 0x51504859 (“QPHY”)

0x0004 4 QPHY_VER R major(8) | minor(8) | patch(16)

0x0008 4 QPHY_CFG_ID R Configuration ID (01–12)

0x000C 4 QPHY_STATUS R bit 0 = ready, bits 1–4 = per-lane link, bit 5 = key loaded, bit 6 = fabric joined

0x0010 4 QPHY_CTRL W bit 0 = enable, bit 1 = FLR, bit 2 = link-retrain, bits 3–6 = per-lane reset

0x0014 4 QPHY_LID R/W Local Identifier (16 bits used)

0x0018 32 QPHY_KEY W AES-256-GCM link key (write-only; host cannot read back)

0x0038 4 QPHY_KEY_EPOCH W Atomic key-rotation trigger

0x0040 64 QPHY_LANE_STATUS R 16 bytes × 4 lanes: FEC corrects, uncorrectable, retrain count, LOS count

0x0100 32 QPHY_COUNTERS R Frames TX, frames RX, credits granted, credits consumed

0x0200 128 QPHY_EVENT_Q R/W 16 × 8-byte event ring; host writes back read pointer

0x0400 512 QPHY_VC_CFG R/W 8 VCs × 64 bytes: credit window, priority, backpressure threshold

0x1000 4,096 QPHY_SQ_DB W 16 PF submission-queue doorbells (32-bit write = new tail)

0x2000 4,096 QPHY_CQ_DB W 16 PF completion-queue doorbells (32-bit write = new head)

Error Codes (QPHY_ERR_*)

Code Name Meaning

0 QPHY_OK Success

1 QPHY_ERR_UNCORRECTABLE_FEC Frame dropped by MAC (uncorrectable FEC)

2 QPHY_ERR_AUTH_FAIL AES-GCM tag mismatch

3 QPHY_ERR_CREDIT_EXHAUSTED Long-term credit stall

4 QPHY_ERR_LANE_LOSS Lane lost signal mid-frame

5 QPHY_ERR_PEER_NOT_FOUND Destination LID not present on fabric

6 QPHY_ERR_KEY_UNSET Frame sent before AES-GCM key provisioned

7 QPHY_ERR_FLR_BARRIER Card was FLR’d mid-transaction

8 QPHY_ERR_INVALID_SGL Scatter-gather list length or address invalid

9 QPHY_ERR_QUEUE_OVERFLOW Submission Queue overflow

10 QPHY_ERR_OPCODE Unknown opcode

Event Codes (On-Wire)

Code Event

0x01 Uncorrectable FEC

0x02 AES-GCM authentication-tag failure

0x03 Credit exhausted

0x04 PipeBeam re-alignment

0x05 Lane loss of signal

0x06 Lane restored

0x07 Key epoch in (key rotation acknowledgement)

Reset Domains

Reset Scope

PERST# (from PCIe) Resets entire APM01-D-QPHY including PHY and MAC

Function-level reset (FLR) Resets PCIe endpoint and DMA state; PHY stays up

Link retrain (software-initiated) Cycles all four QBeam lanes; PCIe stays up

PHY-only reset Cycles a single QBeam lane for debug; other three lanes stay up in degraded mode

Failure Modes

Failure Detection Surface

Uncorrectable FEC MAC RX Event queue + counter increment

AES-GCM tag mismatch Crypto RX Event queue + counter increment; frame dropped

Lane loss of signal PHY RX Automatic retrain; if retrain fails, link marked degraded

PipeBeam misalignment Aligner RX Automatic re-align; if 3 consecutive attempts fail, link retrain

Credit exhaustion MAC TX Backpressure to DMA; host-visible via counter

Doorbell overrun DMA Return code in CQE; Submission Queue paused

Link State Machine

The on-chip firmware (running on Light Trigger cores) implements a 10-state link state machine:

State Description

RESET All lanes marked down; transition to LANE_TRAIN

LANE_TRAIN Poll each lane for lock; when all 4 locked, transition to FEC_LOCK

FEC_LOCK Wait for RS-FEC decoder lock on all lanes; then PIPEBEAM_ALIGN

PIPEBEAM_ALIGN Wait for PipeBeam temporal alignment across all 4 lanes

HELLO_SENT Broadcast LINK_HELLO with LID and per-VC credit grants (64 credits per VC)

HELLO_RECV Awaiting peer’s LINK_HELLO

ACK_SENT LINK_ACK sent; awaiting confirmation

UP Steady-state: data transfer, credit replenishment, event polling

DEGRADED One or more lanes lost; data path operational on remaining lanes; retrain attempted

DOWN Link failed; retrain from LANE_TRAIN

Host Driver

Platform Details

Linux Upstream-style character device ( /dev/qphy0 ) + libqphy userspace shim + optional ib_qphy module (Verbs/RDMA provider). Debug via /sys/class/qphy/qphyN/lane_status , /sys/class/qphy/qphyN/counters , /sys/class/qphy/qphyN/event_ring .

Windows WDM driver with SR-IOV support; exposes raw fabric API + NDIS shim for RDMA-capable NIC presentation. Device path: \\.\qphyN .

Driver Bring-Up Sequence

PCIe enumeration; BARs mapped.
Read QPHY_ID , QPHY_VER , QPHY_CFG_ID . Refuse to attach if magic wrong or version incompatible.
Write QPHY_CTRL.enable = 1 . Wait for QPHY_STATUS.ready = 1 .
Register with the qphyd daemon; receive LID assignment.
Write QPHY_LID and QPHY_KEY ; assert QPHY_STATUS.key_loaded and .fabric_joined .
Configure QPHY_VC_CFG per operator policy.
Allocate SQ/CQ memory; program per-queue MMIO windows (BAR 4).
Enable MSI-X vectors.
Driver ready; expose /dev/qphyN and (optional) ib_qphy verbs provider.

SDK Families

SDK Language Details

C SDK ( sdk/c/ ) C11 Reference libqphy client. One header ( qphy_sdk.h ) + sources. Builds as libqphy.so (shared library). API: qphy_open , qphy_close , qphy_queue_create , qphy_queue_destroy , qphy_submit , qphy_poll , qphy_wait , qphy_rdma_write , qphy_rdma_read , qphy_get_counters , qphy_strerror . SDK version: 0.1.0.

Python bindings ( sdk/python/qphy/ ) Python pip-installable wrapper over the C SDK via cffi.

Rust crate ( sdk/rust/ ) Rust Idiomatic Rust bindings, no_std friendly for embedded hosts.

Firmware Families

Firmware Language Target Details

Link firmware ( firmware/link/ ) C11 (bare-metal) APM01-D-QPHY Light Trigger cores Link-layer state machine: PHY bring-up, RS-FEC lock, PipeBeam alignment, credit accounting, doorbell dispatch, MSI-X delivery. Cross-compiles via autophi-lightrigger-gcc (on-chip target) or gcc (POSIX host simulator). No libc, no dynamic allocation, no float. Build: make TARGET=on-chip or make TARGET=host-sim .

Host daemon ( firmware/host/ ) Rust Host OS (Linux/Windows) Fabric discovery, LID assignment, virtual-channel policy, per-tenant metering, telemetry export to operator observability stack. Communicates with link firmware via MMIO registers.

EDA Flow

Path Scope Tools Output

Path A — Open Source (OpenLANE) APM01, APM02 evaluation builds on SkyWater sky130 Yosys (synthesis), OpenROAD (P&R), Magic (DRC/GDSII), Netgen (LVS) GDSII, LEF, DEF, gate-level netlist; submit to SkyWater MPW/shuttle

Path B — Commercial (Synopsys / IFS) APM03–APM12 production builds Synopsys Design Compiler (synthesis), IC Compiler II (P&R), Mentor Calibre (DRC/LVS/ERC) GDSII, foundry-signoff netlist; submit to IFS production tape-out

APM03 runs both flows for cross-validation: sky130 evaluation build feeds an IFS N7-equivalent risk build before production.

Verification Plan

Level Method Coverage Target

Unit tests Per-block Verilog testbench ( dv/unit/ ) 95% line, 90% branch, 85% condition

Integration tests Two-instance loopback ( dv/integration/ ) —

Formal verification Protocol-conformance proof for MAC flow control (LTL: “no credit is ever spent twice”); AES-GCM tag-verification safety property —

Continuous integration OpenLANE regression on APM01/02 sky130 build in CI —

Fabric Topologies

Each HBA exposes 4 QBeam ports on the bracket. Recommended topologies:

Topology Scale (HBAs) Diameter Single-Cable-Cut Resilience

Point-to-point 2 1 hop Full disconnect (or degraded with redundant cables)

Star (passive patch panel) Up to 16 2 hops One HBA disconnected; patch panel is SPOF

Ring Up to 32 N/2 hops Degraded chain; 2 cuts to partition

2D Torus (K×K) 16–64 K hops Slightly longer routes; survives many cuts

Dragonfly (G×A) 16–256 3 hops Alternate routing; survives many cuts

Facility ceiling (dragonfly-of-dragonflies) >256 5 hops Alternate routing; partition-resistant

Beyond one facility, the recommended product is AeroPhi (Project 55) with its six-tier fractal mesh.

Sideband and Debug

Interface Details

I²C sideband J5 header (2.54 mm 5-pin, board edge, unpopulated by default). On-board BMC (U2) or host BMC via slot sideband can read link status, temperature, and error counters without touching PCIe.

JTAG J6 header (2.54 mm 10-pin, board edge, unpopulated by default).

Recovery button SW1 (tactile, Omron B3W-4155, board edge, protrudes through bracket cutout).

Host-side debug (Linux) /sys/class/qphy/qphyN/lane_status , /sys/class/qphy/qphyN/counters , /sys/class/qphy/qphyN/event_ring (read-only ring dump, drain-on-read). qphyd local Unix socket for topology dumps and per-VF metering.

Reference-Board Bring-Up Plan

Power-only bring-up: Populate power stage only; verify all rails come up in sequence.
Boot-flash bring-up: Load APM01-D-QPHY boot ROM into U3 (SPI flash); apply PERST# release; verify UART banner.
PCIe link-training: Insert into a compliance host; verify Gen5 x16 link at PCIe LTSSM L0.
PHY loopback: Cable J1↔J2; run BIST; verify BER Peer link: Cable to a second HBA; verify LINK_HELLO / LINK_ACK exchange, credit grant, traffic loopback.
Compliance: Submit to PCI-SIG for Gen5 compliance workshop.

Sibling Product Families

Sibling Project Relationship

ExitPhi IC 54 The ExitPhi patent itself, sold as an IP wrap with the WFA silicon family (WFA-Node / WFA-Hub / WFA-Mesh)

AeroPhi 55 Six-tier fractal mesh consumer of QBeam; T1–T6 board reference designs; 20 silicon configurations

QPHY PCIe Card 77 Cable-free PCIe add-in card hosting a QBeam-enabled chip; antenna handles chip-to-chip wirelessly; PCIe fingers handle only host↔chip

Source, RTL, revenue, and contracts do not co-mingle across families. Each buyer signs their own LICENSE with the inventor.

Compliance and Export

Item Details

US Export Configurations at 5 nm and below subject to US EAR / BIS export controls; buyer responsible for compliance

DFARS 252.204-7012 IFS handles under standard DFARS trusted-foundry framework; buyer’s tape-out contract inherits

America First restriction License permits deployment only in the USA; foundries outside the USA (e.g. TSMC N7 secondary) require inventor written consent case-by-case

PCIe compliance Deferred; submit to PCI-SIG for Gen5 compliance workshop (buyer/CM scope)

FIPS 140-3 Deferred; crypto-module certification is buyer/cert-lab scope

Approximate BOM Cost (Production Volume ≥ 10k Units, Excluding U1)

Category Cost (USD, target)

Passives + power regulators ~$22

Rakon clocks (Y1, Y2, Y3) ~$14

Connectors (SFF-8674 × 4) ~$18

Bracket + heatsink + TIM ~$9

PCB fab (12-layer, IPC-6012 Class 6) ~$16

SMT assembly ~$14

BOM excluding U1 silicon ~$93

U1 (APM07-D-QPHY) cost is inventor-set and included in the finished-card list price. Sample lead time from tape-out: 20 weeks; production lead time: 26 weeks.

Trademarks

The following marks are used but not registered as of this document’s date: “Quantum PHY,” “QPHY,” “QBeam,” “CoolBeam,” “PipeBeam,” “ExitPhi,” “AeroPhi,” “AutoPhi,” “cri-one.” “QPHY” is a downstream product name coined at cri-one.com; the canonical patent term is “QBeam.”

What Is in the Package

File / Directory Purpose

SPEC.md Top-level technical specification: scope, system context, wire protocol summary, hardware families, firmware families, host driver, SDK families, deliverables, deferred items, revision history

IP_REFERENCES.md Filed IP dependency chain, product-name derivation trail, sibling product families, trademark list

docs/ARCHITECTURE.md On-card block diagram, TX/RX data paths, boot path, control path, reset domains, failure modes, thermal design

docs/QPHY_PROTOCOL.md Full QPHY-P1 wire protocol: frame format, header/prefix/trailer fields, FEC, encryption, flow control, virtual channels, sequence numbers, ordering, control opcodes, encoding

docs/HOST_DRIVER_CONTRACT.md Host driver ABI: PCIe enumeration (Vendor/Device/Class IDs), BAR layout, register map, queue-pair model, SQE/CQE formats, error codes, interrupt model, driver bring-up sequence, suspend/resume, debug interfaces

docs/FABRIC_TOPOLOGIES.md Fabric topology catalog: point-to-point, star, ring, 2D torus, dragonfly, facility ceiling; wiring costs, failure envelopes, wiring-bill generator placeholders

hardware/QPHY_HBA_BOARD/SPEC.md Reference PCIe HBA board specification: mechanical, silicon, power rails, clocks, QBeam bracket ports, sideband, passives, DFM constraints, DRC, bring-up plan

hardware/QPHY_HBA_BOARD/BOM.md Full bill of materials: 13 active ICs (U1–U13), ~640+ passives (capacitors, ferrites, resistors, ESD, ORing FETs), clocks (Y1–Y3), connectors (J0–J6), LEDs, bracket, heatsink, TIM, recovery button, with vendors and approximate costs

hardware/QPHY_HBA_BOARD/STACKUP.md 12-layer PCB stackup: layer-by-layer copper weights, dielectric thicknesses, Er values, impedance targets (85 Ω PCIe, 100 Ω QBeam, 50 Ω control), length-match tolerances, via structure, manufacturing class (IPC-6012 Class 6, ENIG, UL 94V-0)

hardware/APM-D-QPHY/SPEC.md APM01-D-QPHY silicon specification: lineage from APM01-D Nexus Core, scientific claim, block diagram, 12-generation configuration table, foundry-ready deliverables, EDA flow (Path A + Path B), verification plan, compatibility with AutoPhi Modern

hardware/APM-D-QPHY/FOUNDRY_STANDARDS.md Foundry-selection matrix for all 12 configurations: primary/secondary foundry, PDK, EDA flow, submission mode, NRE and per-die cost estimates, compliance and export notes

parts/APM01-D-QPHY/ through parts/APM12-D-QPHY/ 12 per-generation directories, each containing: FOUNDRY_HANDOFF.md (44-line canonical AutoPhi handoff), manifest.json (machine-readable per-SKU manifest), STORE_LISTING.md (store copy), store_description.html (live store HTML), synth.sdc (synthesis constraints), floorplan.tcl (die floorplan), pnr_config.tcl (P&R config), openlane_config.json (OpenLANE config for APM01/02 sky130 evaluation)

firmware/link/qphy_link.h Link-layer state machine header: state definitions, event codes, wire opcodes, per-VC credit structures, public API declarations

firmware/link/qphy_link.c Link-layer state machine implementation: bare-metal C, no libc, no dynamic allocation, portable to on-chip and POSIX host simulator

firmware/link/Makefile Build system for link firmware: on-chip ( autophi-lightrigger-gcc ) and host-sim ( gcc ) targets

firmware/host/ Host-side daemon scaffolding (Rust): fabric discovery, LID assignment, VC policy, metering, telemetry

sdk/c/qphy_sdk.h C SDK header: opaque handles, error codes, SQE/CQE structures, card discovery, queue-pair management, submit/poll/wait, RDMA convenience, telemetry counters

sdk/c/qphy_sdk.c C SDK reference implementation: Linux ( /dev/qphyN ) and Windows ( \\.\qphyN ) device access, doorbell ringing, CQ polling, RDMA write/read

sdk/c/Makefile Builds libqphy.so (shared library, -fPIC , C11, -O2 )

sdk/python/qphy/ Python bindings over the C SDK (pip-installable)

sdk/rust/ Rust crate: idiomatic bindings, no_std friendly

figures/qphy_product_art.py Python (PIL/Pillow) script generating the hero product image

figures/qphy.png Generated product hero image

figures/apm01-d-qphy.png through figures/apm12-d-qphy.png 12 per-generation silicon product images

Deferred / Open Items (Buyer or CM Scope)

Silicon tape-out of any QPHY configuration through the AutoPhi Day-One production stack
KiCad schematic capture (buyer/CM scope; the inventor package delivers SPEC + BOM + STACKUP)
PCB layout and Gerber generation (buyer/CM scope)
Prototype fab and bring-up
PCIe 5.0 compliance passes at PCI-SIG
FIPS 140-3 certification for the crypto module
Interop tests against AutoPhi PCIe5-256, BGA256, and PCIe5-1536 endpoint boards

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

Green PCIe add-in card with two QSFP cages and a large heat-spreader chip package, on white

Footnotes

Product number 8526.
Family: qbeam.
Purchase: When you buy, you buy the use of that blueprint only.

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