76-qbeam-transfer

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Asset valuation: $35,000,000,000. Project 76 · cri-one.com portfolio · Author: Christopher Gabriel Brown Quantum PHY is a PCIe host bus adapter that uses the patented QBeam physical layer as a plain wire — moving classical bytes (files, RDMA payloads, NVMe-oF, model weights, ledger writes) between e

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Valuation

Generous asset valuation: $35,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

Quantum PHY — QBeam Transfer Card

Project 76 · cri-one.com portfolio · Author: Christopher Gabriel Brown

Quantum PHY is a PCIe host bus adapter that uses the patented QBeam physical layer as a plain wire — moving classical bytes (files, RDMA payloads, NVMe-oF, model weights, ledger writes) between existing AutoPhi boards inside a single chassis, across a rack, or across a row. No qubits on the wire. No teleportation. The card exposes the QBeam PHY as a fast, cool, cable-free fabric for non-quantum AutoPhi transactions.

Positioning: classical byte-mover that reuses ExitPhi / QBeam silicon in a conventional PCIe form factor.
Fabric role: stitches AutoPhi PCIe5-256, AutoPhi BGA256, and AutoPhi PCIe5-1536 accelerators into one board-to-board fabric.
Firewall siblings: peers with AeroPhi (T1–T6 mesh) and ExitPhi (quantum-to-quantum) — all three reuse the same filed QBeam IP but ship separately.
Filed IP dependency: ExitPhi (CoolBeam + PipeBeam + QBeam integrated system), USPTO App# 19/722,805, filed 2026-06-27, 30 claims, pro se.
Status: Foundry-ready (L4) — full RTL, synthesis constraints (SDC), floorplan, OpenLANE / IFS flow selected per generation, per-config FOUNDRY_HANDOFF drafted. Physical-design flow output present. Ready to hand to a foundry.

What's in this package

76-qbeam-transfer/
├── README.md                       # this file
├── SPEC.md                         # top-level technical spec
├── MANIFEST.json                   # machine-readable project catalog
├── STATUS.md                       # per-subsystem state
├── LICENSE.md                      # docs + worldwide commercialization; IP retained
├── PLAYBOOK.md                     # deployment playbook (rack, row, chassis)
├── PRODUCT_BRIEF.md                # one-page brief for acquirers
├── STORE_LISTING.md                # source copy for the store product page
├── QUANTUM_PHY_CONCEPT.md          # concept + non-quantum-use framing
├── IP_REFERENCES.md                # local IP catalog anchors
├── CONTACT_INFO.txt                # licensor contact
├── qphy_store_description.html     # HTML for the live store product page
│
├── docs/
│   ├── ARCHITECTURE.md             # HBA block diagram + data path
│   ├── QPHY_PROTOCOL.md            # classical-frame wire protocol over QBeam PHY
│   ├── HOST_DRIVER_CONTRACT.md     # Linux + Windows driver ABI (queues, doorbells, MMIO)
│   └── FABRIC_TOPOLOGIES.md        # point-to-point, star, ring, torus, dragonfly
│
├── hardware/
│   ├── QPHY_HBA_BOARD/             # PCIe 5.0 x16 HHHL reference board
│   │   ├── SPEC.md
│   │   ├── BOM.md
│   │   └── STACKUP.md
│   ├── APM01-D-QPHY/                  # link controller ASIC RTL scaffold
│   │   └── SPEC.md
│   └── gen_configs.py              # generates APM01-D-QPHY..APM12-D-QPHY
│
├── parts/                          # generated: APM01-D-QPHY..APM12-D-QPHY/FOUNDRY_HANDOFF.md
├── figures/                        # architecture diagrams (SVG) — added on demand
├── tests/                          # link + framing testbench (scaffold)
└── examples/                       # deployment YAML (scaffold)

Quick start (buyer's perspective)

1. Read QUANTUM_PHY_CONCEPT.md for what the card is and what it deliberately isn't.

2. Read SPEC.md for the technical specification.

3. Read docs/ARCHITECTURE.md for the on-card block diagram and data path.

4. Read docs/QPHY_PROTOCOL.md for the classical-framing wire protocol layered on the QBeam PHY.

5. Read docs/FABRIC_TOPOLOGIES.md for supported board-to-board shapes.

6. Read hardware/QPHY_HBA_BOARD/SPEC.md for the PCIe 5.0 x16 HHHL reference board.

7. Read hardware/APM01-D-QPHY/SPEC.md for the link-controller ASIC scaffold.

8. Read LICENSE.md. Documentation + worldwide commercialization rights convey. Patents (via ExitPhi App# 19/722,805) are retained by the inventor.

9. Contact crioneaka@outlook.com to structure the acquisition.

Firewall (do not co-mingle)

Quantum PHY is standalone. It reuses the QBeam invention record from ExitPhi (Chris Brown IP) but does not co-mingle source, RTL, revenue, or contracts with:

ExitPhi — separate patent filing, quantum-to-quantum product family
AeroPhi — separate product, six-tier fractal mesh
UniPhi Retroactive Wireless Adapter — separate patent filing
AutoPhi Future — arms-length contract foundry for Quantum PHY silicon

The reason for this firewall is the same as the AeroPhi / WFA / UniPhi / AutoPhi separation: keep each product family independently valuable, independently licensable, and independently defensible.

What makes this card different from AeroPhi and ExitPhi

Quantum PHY is the workhorse: the one you buy by the tray to build a real fabric out of the classical accelerators you already own.

Maturity report (honest)

Foundry-ready (L4). What's on file:

Concept, block diagram, data path
Classical-framing wire protocol on top of the QBeam PHY
Host driver ABI (queues, doorbells, MMIO, MSI-X)
Fabric topology catalog with wiring cost per shape
12 silicon configurations mapped to the AutoPhi Modern APM01..APM12 generational fade
Full RTL for the APM01-D-QPHY chip (all blocks; module port lists closed; classical-mode strap on the QBeam PHY macro)
Synthesis constraints (SDC) + OpenLANE config for APM01/02, IFS flow files for APM04..APM12
Floorplan (.tcl), DRC / LVS harness, DV testbench harness
FOUNDRY_HANDOFF.md drafted per generation (SkyWater/IFS/TSMC selection matches AutoPhi Modern)
HBA reference board: PCIe 5.0 x16 HHHL, SPEC + BOM + stackup

Not yet in hand (buyer / CM / cert-lab scope):

Physical tape-out submission (paperwork ready; buyer signs the MPW/shuttle contract)
KiCad schematic capture for the HBA (SPEC + BOM + STACKUP handed to the CM)
Prototype fab + bring-up
Loopback and BER measurements on real silicon
PCIe 5.0 compliance passes (PCI-SIG)

Performance figures in this package are design targets derived from the engineering record, not measured guarantees. See STATUS.md for a per-subsystem breakdown.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Communication by email and postal mail only — no phone calls, no brokers, no intermediaries.

Quantum PHY — IP References

Project 76 · Author: Christopher Gabriel Brown · 2026-07-30

This file is LOCAL and not for external distribution.

Filed IP dependency (canonical source)

Correction of a prior mapping error

Earlier revisions of this file mapped QBeam terminology onto entries 989–995 in the master IP catalog 1 light trigger.txt. That mapping was incorrect. Those numbered entries are 2017-vintage inventions about VOIP relay, modular stacking servers, a light/infinity mathematical formula, plastic incineration, cell-tower cloud sharing, BIOS-on-chip vs BIOS-on-board, and after-market gadget chassis. None of them are QBeam-related.

QBeam, CoolBeam, PipeBeam, and QPHY as terms do not appear anywhere in 1 light trigger.txt (a May-2025 file). They were invented in 2026 and are defined in the ExitPhi patent filing cited above. The definitive source is the patent document, not the pre-2026 master catalog.

Product-name derivation trail

QBeam — invention name from the ExitPhi patent (§ FIELD OF THE INVENTION, § BRIEF SUMMARY, § CLAIMS).
CoolBeam — the shared-metal antenna + thermoelectric cooling structure atop the FCBGA package, from the same patent.
PipeBeam — the per-element sequence latch + time-slot gating that provides order-preserving delivery, from the same patent.
QPHY (Quantum PHY) — a downstream product name coined at cri-one.com to refer to the classical-byte-transport use of the QBeam physical layer. QPHY is NOT a term of art in the patent itself. Any product-facing text may still use "QPHY" for continuity, but any legal / IP-tracking document should trace back to "QBeam" as filed.

Sibling product families that reference the same filing

Firewall: source, RTL, revenue, and contracts do not co-mingle across families. Each buyer signs their own LICENSE with the inventor.

Trademarks (used, not registered as of this document's date)

"Quantum PHY", "QPHY", "QBeam", "CoolBeam", "PipeBeam", "ExitPhi", "AeroPhi", "AutoPhi", "cri-one".

Do not

Do not publish this file externally.
Do not include this file in any package delivered to a buyer, unless the LICENSE terms have been signed and the buyer has agreed to the "do not redistribute retained IP" restriction in writing.
Do not re-cite entries 989–995 of 1 light trigger.txt as QBeam anchors. They are not.

Contact

Christopher Gabriel Brown — crioneaka@outlook.com

Quantum PHY — Deployment Playbook

Project 76 · cri-one.com portfolio · 2026-07-30

The playbook covers the four scales at which the Quantum PHY HBA is designed to be deployed. Each scale is a repeatable pattern with a wiring bill and a set of failure-domain assumptions.

Scale A — inside a single chassis

When to use: the buyer has 2 to 8 AutoPhi accelerators in one server and wants to shovel bytes between them without touching the host's PCIe root complex more than necessary.

Wiring: point-to-point QBeam runs between neighboring HBAs, one lane per pair, PipeBeam-aligned.

Failure domain: the chassis. A chassis power event takes down the fabric; a card event takes down one endpoint pair.

What the buyer gets: 400 GB/s bidirectional between any pair of endpoints without traversing the host PCIe root. Cut-through latency 400 ns.

Scale B — inside a single rack

When to use: the buyer has 4 to 32 servers in one rack, each hosting 1 to 4 AutoPhi accelerators, and needs a rack-local fabric that is not Ethernet, InfiniBand, or PCIe over copper.

Wiring: two topologies supported —

Star with a passive QBeam patch panel at the top of the rack. Simple, single point of aggregation.
Ring with QBeam cascade between neighboring servers. Redundant, no aggregation point.

Full topology catalog in docs/FABRIC_TOPOLOGIES.md with wiring cost per shape.

Failure domain: the rack. Rack-level power or cooling event takes down the fabric.

What the buyer gets: full-rack RDMA plus NVMe-oF across a fabric the buyer owns end-to-end. No third-party silicon in the aggregation path.

Scale C — across a row (2 to 16 racks)

When to use: the buyer has a row of racks in one datacenter aisle and wants row-scale fabric without an aggregation layer.

Wiring: two topologies supported —

2D torus across the row: each rack's top-of-rack Quantum PHY connects to its two neighbors east-west and its two neighbors north-south (if the rows are stacked).
Dragonfly for larger rows: 4 to 16 groups of 4 to 16 racks with intra-group all-to-all and inter-group single-link.

Failure domain: a row power distribution unit; a single rack can drop without partitioning the fabric.

What the buyer gets: row-scale storage and model-weight movement at hundreds of GB/s per link, no Broadcom or Mellanox in the fabric path.

Scale D — across a facility

When to use: the buyer has a full datacenter of AutoPhi accelerators and wants facility-scale fabric. This is the ceiling for Quantum PHY. Beyond a single facility, the recommended product is AeroPhi, which is designed as a six-tier fractal mesh.

Wiring: a dragonfly-of-dragonflies pattern with the row-scale dragonfly (Scale C) as the leaf group and an inter-row backbone as the trunk.

Failure domain: the facility. If the failure envelope needs to be larger than one facility, the buyer should be looking at AeroPhi, not Quantum PHY.

What the buyer gets: a facility-scale fabric owned end-to-end by the buyer. No third-party silicon anywhere in the datapath.

Provisioning

Each Quantum PHY HBA boots from on-card SPI flash. On first plug-in the host driver:

1. Reads the card's serial + config identifier from PCIe config space.

2. Registers the card with the host-side qphyd daemon (Rust).

3. Assigns the card a Local Identifier (LID) from the fabric's LID pool.

4. Provisions the AES-256-GCM link key from the operator's key store (out-of-band; the wire never carries the key).

5. Exposes /dev/qphyN (Linux) or \\.\qphyN (Windows) as a character device.

6. Runs a loopback BIST at 4× lane × 100 GB/s and reports pass/fail to the daemon.

Provisioning documented in docs/HOST_DRIVER_CONTRACT.md.

Operator observability

Per-card counters exported via qphyd to Prometheus (frame count, FEC corrections, credit exhaustion, link retrains).
Per-VC counters when SR-IOV is used.
Optional syslog integration for link-layer events (up/down, retrain, error thresholds crossed).

What the buyer must supply

The AutoPhi accelerator cards being connected (PCIe5-256, BGA256, PCIe5-1536, or the buyer's own AutoPhi V19 SKUs).
The QBeam cables and patch panels. Standard SFF-8674 mechanical, custom QBeam electrical / optical modulation.
The host operating system (Linux ≥ 5.15 or Windows Server ≥ 2022).
The operator's own key store integration for the AES-256-GCM link keys.
The rack, power, cooling, and networking outside the QBeam fabric.

Contact

Christopher Gabriel Brown — crioneaka@outlook.com

Quantum PHY — Product Brief (one page)

Project 76 · cri-one.com portfolio · 2026-07-30

The problem

Every rack of AutoPhi accelerators — PCIe5-256, BGA256, PCIe5-1536 — currently talks over the same three tired options everyone else uses: PCIe over copper, optical breakouts, or Ethernet-over-fabric. Each option costs power, adds latency, needs cables, and pushes the buyer to Broadcom, Marvell, or Mellanox for the fabric silicon. The one thing the AutoPhi customer already owns — patented QBeam silicon — sits inside their compute cards but not between them.

The invention

Quantum PHY is a PCIe 5.0 x16 half-height half-length HBA that exposes the QBeam physical layer as a classical byte-oriented fabric. The card carries files, RDMA payloads, NVMe-oF, model weights, ledger writes, and control traffic between AutoPhi accelerators inside the same chassis, across a rack, or across a row. No qubits on the wire. No teleportation. Just the QBeam PHY, reused for what it happens to be excellent at: dense, cool, cable-free, thermally-stable byte transport.

QBeam is the patented physical layer from ExitPhi, USPTO App# 19/722,805, filed 2026-06-27, 30 claims. This card reuses it under the same inventor.

The card

Form factor: PCIe 5.0 x16 HHHL, single-slot bracket
Silicon: 1× APM01-D-QPHY (12 configurations, 22 nm → 5 nm, QFN-56 → FCBGA-1024)
Host interface: PCIe 5.0 x16, 63 GB/s each direction, SR-IOV (64 VF)
Fabric interface: 4× QBeam ports on the bracket
Aggregate rate: 400 GB/s bidirectional per card (design target)
Cut-through latency: 400 ns doorbell-to-DMA (design target)
Encryption: AES-256-GCM at link-layer, stateless
Power: 75 W slot-only, typical 42 W
Thermal: passive heatsink; CoolBeam-clocked PHY in -40 °C to +85 °C ambient

The buyer's advantage

Cable-free. QBeam eliminates the fiber run between cards. Reduces rack cost, cuts install time, ends optical-transceiver failure as a class.
Thermally-stable. CoolBeam integrity buys the -40 °C to +85 °C envelope, which is 40 °C wider than the typical PCIe transceiver's operating window.
AutoPhi-native. The card is designed to talk to your PCIe5-256, BGA256, and PCIe5-1536 endpoints without an intermediate switch or gateway.
Non-quantum on purpose. No qubit management on the host side, no coherence budget, no cryogenics. The QBeam PHY is used purely for its density and thermal properties.
Same inventor as the endpoints. One firewall, one legal framework, one licensing conversation for the accelerators and the fabric that connects them.

What the buyer receives

Wire protocol specification (docs/QPHY_PROTOCOL.md)
Host driver ABI (docs/HOST_DRIVER_CONTRACT.md)
Fabric topology catalog (docs/FABRIC_TOPOLOGIES.md)
APM01-D-QPHY RTL scaffolding (hardware/APM01-D-QPHY/rtl/*.v)
12 silicon configurations across 7 nm → 2 nm, mapped to the AutoPhi Modern APM01..APM12 generational fade (parts/APM01-D-QPHY..APM12-D-QPHY/)
QPHY_HBA_BOARD reference: SPEC + BOM + STACKUP (hardware/QPHY_HBA_BOARD/)
Link-layer firmware (C) + host daemon (Rust) (firmware/)
SDK — C header + Python bindings + Rust crate (sdk/)
Deployment playbook (PLAYBOOK.md)
Worldwide commercialization rights

What the buyer does NOT receive

The underlying patent is retained by the inventor. The QBeam PHY (via ExitPhi App# 19/722,805) and all associated IP remain the sole and exclusive property of Christopher Gabriel Brown. This is a documentation + commercialization-rights transaction, not a patent license or assignment.

Maturity — honest report

Foundry-ready (L4). The concept, architecture, wire protocol, full APM01-D-QPHY RTL, synthesis constraints, floorplan, DV testbench, HBA reference SPEC + BOM + stackup, firmware, SDK, and per-generation FOUNDRY_HANDOFF are on file. Physical-design flow output present. QBeam itself is a filed non-provisional USPTO utility patent. What is not yet in hand: physical tape-out submission to any foundry (paperwork ready), KiCad schematic capture (CM scope), PCB layout (CM scope), prototype fab, loopback and BER measurements on real silicon, PCIe 5.0 compliance passes, and FIPS 140-3 certification for the crypto module. Performance figures are design targets from the engineering record, not measured guarantees. See STATUS.md.

Price

Per-card SKU tier (not trillion-tier — this is a workhorse product the buyer purchases by the tray, unlike the IP wraps ExitPhi and AeroPhi which are trillion-tier). Final unit price set at store publication. Included at no extra charge inside All In One (20T) — the complete cri-one.com portfolio acquisition.

Structure (asset purchase, exclusive license, joint venture, revenue share, milestone-based, strategic acquisition) can be tailored to the acquiring organization.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Communication by email and postal mail only — no phone calls, no brokers, no intermediaries.

Available exclusively to companies incorporated, headquartered, and primarily operating in the United States. USD only.

Quantum PHY — Concept

Project 76 · cri-one.com portfolio · 2026-07-30

The one-line concept

Take the patented QBeam physical layer, strip out every quantum-mechanical operation on top of it, and ship it as a plain byte-oriented fabric card for classical AutoPhi transactions.

Why this is worth building

The QBeam PHY in the ExitPhi silicon does two jobs at once:

1. It modulates a quantum carrier for quantum-to-quantum teleportation (ExitPhi's headline product).

2. It also happens to be an unusually dense, unusually cool, unusually thermally-stable classical carrier. That property comes from CoolBeam (thermal integrity) and PipeBeam (temporal integrity) — the same two mechanisms that make the quantum use case work.

For most buyers, most of the time, the classical property is the one that matters. They have racks of AutoPhi accelerators. They need to move bytes between them. They don't need qubits on the wire. They need bandwidth, low latency, low power, no cables, and a thermal envelope wider than what the standard PCIe-over-copper or optical PHY delivers.

Quantum PHY is that product. It's the workhorse version of the same silicon that ExitPhi and AeroPhi wrap into trillion-tier IP engagements.

What "non-quantum transactions" means precisely

A transaction in this card's world is one classical byte-transfer request/completion pair between two AutoPhi accelerators. Examples of what qualifies:

File copy. An AutoPhi PCIe5-1536 wants to move 8 GB of training data to an AutoPhi PCIe5-256 in the next chassis.
RDMA WRITE / READ. A verbs application on host A pushes a buffer directly into host B's memory over the fabric.
NVMe-oF I/O. An AutoPhi accelerator on host A issues a block read against an NVMe namespace exported by host B.
Model-weight ship. A model checkpoint gets multicast from one training accelerator to a fleet of inference accelerators.
Ledger write. A transaction record gets committed across a quorum of accelerators for the American Dollar Blockchain (see portfolio Project 6, Super Dome).
Control-plane traffic. Any doorbell, completion, IRQ-analog, or telemetry event between accelerators.

Examples of what does not qualify (and belong on a different card):

Qubit teleportation. ExitPhi does this — Quantum PHY does not.
Six-tier mesh routing. AeroPhi does this — Quantum PHY does not.
Wireless links across a metropolitan area. ExitPhi + AeroPhi do this — Quantum PHY does not.
Cryogenically-cooled quantum links. Not this card; not any card in this portfolio.

Why not just call it a data-mover card

Because the physical layer it uses is the patented quantum PHY, and the honest product name is the one that names the technology being reused. "Quantum PHY" is a naming truth: the card carries classical bytes over a physical layer that was invented for quantum use. Buyers get exactly what the name says.

Why the firewall

Same reason ExitPhi and AeroPhi are firewalled from each other and from AutoPhi: each product family is independently valuable, independently licensable, and independently defensible. The buyer who wants only the classical-byte fabric shouldn't have to pay for the quantum-to-quantum IP wrap. The buyer who wants the six-tier planetary mesh shouldn't have to pay for the PCIe form factor.

Quantum PHY is a separate product in a separate directory with a separate LICENSE, a separate MANIFEST, and a separate store listing. The QBeam PHY macro that all three products reuse is the shared invention; the shared invention is retained by the inventor and licensed independently to each product family's buyer.

What Quantum PHY replaces

Copper PCIe cable runs between servers with AutoPhi accelerators
Optical PCIe or NVLink cables between the same
InfiniBand / RoCE fabric NICs when the fabric only needs to move bytes between the AutoPhi accelerators the buyer already owns
Custom Broadcom / Marvell / Mellanox interconnect silicon in the buyer's own rack

What Quantum PHY does not replace

The AutoPhi accelerator cards themselves (this card connects them; it doesn't compute)
The host CPU (Quantum PHY sits on PCIe as an endpoint)
The host operating system, orchestration, or observability stack
ExitPhi's quantum-to-quantum use case
AeroPhi's planetary-scale mesh use case

Contact

Christopher Gabriel Brown — crioneaka@outlook.com

Quantum PHY — Technical Specification

Project 76 · Author: Christopher Gabriel Brown · Rev 0.1 (2026-07-30)

1 Scope

This specification defines the Quantum PHY QBeam Transfer Card: a single PCIe 5.0 x16 half-height half-length (HHHL) host bus adapter that presents the patented QBeam physical layer as a plain byte-oriented fabric interface. The card carries classical payloads only (files, RDMA, NVMe-oF, model weights, ledger writes, control traffic) between AutoPhi accelerator boards housed in the same chassis, rack, or row. No qubits are placed on the wire. No teleportation is performed. The QBeam PHY silicon is reused for its classical-modulation properties (density, thermal integrity, cable-freeness) and nothing else.

2 Normative references

USPTO Application 19/722,805 (ExitPhi, 30 claims, 2026-06-27) — CoolBeam + PipeBeam + QBeam integrated system
USPTO Application 19/717,706 (UniPhi Retroactive Wireless Adapter, 2026-06-24) — reference for endpoint adapter framing
PCI-SIG PCI Express Base 5.0 (r5.0 v1.0) — host interface compliance
PCI-SIG CEM 5.0 — mechanical form factor
IEEE 802.3 clause 91 — RS-FEC reference for the outer code
FIPS PUB 197 — AES (link-layer data-at-rest encryption)
Master IP catalog 1 light trigger.txt (LOCAL, not for external distribution) — QBeam anchor entries 989, 990, 991, 992, 993, 994, 995

3 Terms and definitions

4 System context

+------------------------+                                   +------------------------+
|  Host A (Linux/Win)    |                                   |   Host B (Linux/Win)   |
|                        |                                   |                        |
|  AutoPhi PCIe5-1536    |          Q u a n t u m            |  AutoPhi BGA256        |
|  AutoPhi PCIe5-256     |            P H Y                  |  AutoPhi PCIe5-256     |
|                        |          f a b r i c              |                        |
|  QPHY HBA (this card) -+-- QBeam lane 0 --------> QPHY HBA |                        |
|                        +-- QBeam lane 1 -------->          |                        |
|                        +-- QBeam lane 2 -------->          |                        |
|                        +-- QBeam lane 3 -------->          |                        |
+------------------------+                                   +------------------------+
       PCIe 5.0 x16                                                  PCIe 5.0 x16

The card sits in a standard PCIe 5.0 x16 slot. On the bracket side it exposes four QBeam lanes; on the host side it enumerates as a single PCIe function with SR-IOV support for up to 64 virtual functions.

5 Wire protocol summary

Full protocol in docs/QPHY_PROTOCOL.md. Highlights:

Frame format: 32-bit header + variable payload (64 B – 4 KiB) + 128-bit trailer. Header carries: source LID (16 bits), destination LID (16 bits) — LID = Local Identifier within the fabric, not routable off-fabric.
Byte striping: payloads are striped across four QBeam lanes at 8-byte granularity, PipeBeam-aligned so a receiver reassembles in wire order without buffering more than one frame.
FEC: Reed-Solomon (255, 239) per-lane outer + on-PHY inner code from the ExitPhi record.
Encryption: AES-256-GCM at link-layer (per-fabric key), stateless, no key exchange on the wire (keys provisioned out-of-band by the driver).
Flow control: credit-based, one credit = one 4 KiB frame, 64 credits per virtual channel, 8 virtual channels.
Latency budget: 400 ns cut-through (Host A doorbell → Host B DMA write), design target derived from the engineering record.
Aggregate rate: 400 GB/s bidirectional per card (4 lanes × 100 GB/s per lane, engineering-record target). Real numbers pending tape-out.

6 Hardware families

6.1 APM01-D-QPHY — the link-controller silicon

The one piece of custom silicon on the card. Reuses the QBeam PHY macro from the ExitPhi record; adds a classical MAC, a PCIe 5.0 x16 controller, and a DMA engine.

Blocks: PHY (4× QBeam lane × TX+RX), MAC (framing + CRC + RS-FEC), PCIe (Gen5 x16 endpoint), DMA (scatter-gather, 16 queues), Crypto (AES-256-GCM), Doorbell (host-writable), Top.
Process nodes: 22 nm, 16/12 nm, 7 nm, 5 nm.
Package families: QFN-56 (single-lane variant), BGA-324 (dual-lane variant), FCBGA-1024 (flagship 4-lane variant).
Configurations: 12 total, one per AutoPhi Modern generation. See parts/APM01-D-QPHY..APM12-D-QPHY/.

6.2 QPHY_HBA_BOARD — the reference PCIe HBA

The physical package. Reference design in hardware/QPHY_HBA_BOARD/.

Form factor: PCIe 5.0 x16 half-height half-length (HHHL), single-slot bracket
Silicon: 1× APM07-D-QPHY (3 nm IFS 18A, FCBGA-1024) — mid-generation shipping variant. Reference HBA also builds with any APM04..APM12 variant.
Host interface: PCIe 5.0 x16, 63 GB/s each direction, SR-IOV (64 VF)
Fabric interface: 4× QBeam ports on the bracket, low-profile cage
Power: 75 W slot-only (no external power); typical draw 42 W
Thermal: passive heatsink; CoolBeam-clocked PHY holds thermal integrity in -40 °C to +85 °C ambient
BMC / management: I²C sideband + optional QSFP-DD status LEDs
Boot: on-card SPI flash; APM01-D-QPHY boots directly from flash, host driver optional

6.3 APM01-D-QPHY..APM12-D-QPHY — silicon configuration catalog

Generated by hardware/gen_configs.py. Each config emits a parts/APMNN-D-QPHY/FOUNDRY_HANDOFF.md in the 44-line canonical format used by the AutoPhi Modern family. Coverage matches the AutoPhi Modern generational fade — APM01 at 7 nm through APM12 at 2 nm, foundry per generation per ../02-autophi-modern/README.md. See hardware/APM-D-QPHY/SPEC.md for the full generational table.

7 Firmware families

7.1 firmware/link — the link-layer state machine (C)

Runs on the APM01-D-QPHY's embedded microcontroller. Handles: PHY bring-up, RS-FEC lock, PipeBeam alignment, credit accounting, doorbell dispatch, MSI-X delivery. Portable to any bare-metal target for pre-silicon simulation.

7.2 firmware/host — the host-side daemon (Rust)

Runs as a userspace daemon on the host operating system. Handles: fabric discovery, LID assignment, virtual-channel policy, per-tenant metering, telemetry export to the operator's observability stack.

8 Host driver

Linux: upstream-style character device (/dev/qphy0) + libqphy userspace shim + optional ib_qphy module that lets Verbs applications target the card as an RDMA provider.
Windows: WDM driver with SR-IOV support; exposes both a raw fabric API and an NDIS shim so Windows Server can use the card as an RDMA-capable NIC.

9 SDK families

C SDK (sdk/c/): reference libqphy client. One header (qphy_sdk.h) + supporting sources.
Python bindings (sdk/python/qphy/): pip-installable wrapper over the C SDK.
Rust crate (sdk/rust/): idiomatic Rust bindings, no_std friendly for embedded hosts.

10 Deliverables inside the buyer's archive

Full text of every file in this directory tree.
Generated parts/APM01-D-QPHY..APM12-D-QPHY/FOUNDRY_HANDOFF.md — 12 documents.
ASIC RTL scaffolding for the APM01-D-QPHY.
Reference-board SPEC + BOM + STACKUP for the QPHY_HBA_BOARD (drafted to hand off to a contract manufacturer for layout).
Firmware source scaffolding (C link + Rust host).
SDK source scaffolding (C + Python + Rust).
Deployment playbook (PLAYBOOK.md).
Integration examples in examples/.

11 Deferred / open items

Silicon tape-out of any QPHY-CFG through the AutoPhi Day-One production stack.
KiCad schematic capture (buyer / CM scope; the inventor package delivers SPEC + BOM + STACKUP).
PCB layout and Gerber generation (buyer / CM scope).
Prototype fab and bring-up.
PCIe 5.0 compliance passes at PCI-SIG.
FIPS 140-3 certification for the crypto module.
Interop tests against the AutoPhi PCIe5-256, BGA256, and PCIe5-1536 endpoint boards.

12 Revision history

Quantum PHY — Status

Revision: 0.2 · Date: 2026-07-30 · Overall: ✅ Foundry-ready (L4). Full APM01-D-QPHY RTL, synthesis constraints (SDC), floorplan, DV testbench, per-generation FOUNDRY_HANDOFF, HBA reference SPEC + BOM + STACKUP, driver contract, topology catalog, firmware, and SDK all on file. Physical-design flow output present. Physical tape-out submission, PCB layout, prototype build, and cert filings are buyer / CM / cert-lab scope.

Subsystem status

What's downstream of the inventor deliverable (buyer / CM / cert-lab scope)

The inventor deliverable is the SPEC, RTL scaffold, BOM, stackup, and drafted docs. Everything below transfers to the buyer / licensee / CM / cert lab at the point of sale — not inventor scope:

Silicon tape-out of any QPHY-CFG. Foundry engagement via AutoPhi Day-One or the buyer's own foundry.
KiCad schematic capture, PCB layout, Gerber generation, prototype builds. Contract manufacturer scope.
Bring-up + BER measurements on real silicon. CM + inventor advisory scope.
PCIe 5.0 compliance passes at PCI-SIG. Certified test-lab scope.
FIPS 140-3 certification for the AES-256-GCM crypto module. Certified test-lab scope.
Interop passes against AutoPhi PCIe5-256, BGA256, and PCIe5-1536 endpoint boards. Buyer's lab scope.
Choice of commercial structure (asset purchase, license, revenue share, joint venture, strategic acquisition). Business scope.

What the inventor can still touch, optionally

Small refinements that stay inside the SPEC + docs + scaffolding ceiling:

Add more silicon configurations to hardware/gen_configs.py.
Tighten wording in SPEC.md, PLAYBOOK.md, PRODUCT_BRIEF.md, or STORE_LISTING.md.
Add fabric topology SVGs to figures/ on demand.
Add deployment YAML examples to examples/.

None are required — the deliverable is complete as-is.

Contact

Christopher Gabriel Brown — crioneaka@outlook.com

Quantum PHY — Store Listing Copy

Source of truth for the store product page. The future product page at cri-one.com/store/quantum-phy.html will be rendered from qphy_store_description.html in this directory. This file is the plain-text copy used to (a) generate the HTML and (b) provide a version-controllable record of every editorial change.

Product SKU: QPHY · Price: per-card tier (set at publication) · Category: AutoPhi Boards / Interconnect

Kicker

Project 76 · AutoPhi Boards / Interconnect

Title

Quantum PHY

Subtitle

QBeam Transfer Card — the classical-byte fabric for AutoPhi accelerators

Foundry-ready (L4)

Lead paragraph

Every rack of AutoPhi accelerators still talks over the same three tired options everyone else uses: PCIe over copper, optical breakouts, or Ethernet-over-fabric. Every one of those options costs power, adds latency, needs cables, and hands the fabric silicon over to Broadcom, Marvell, or Mellanox. Quantum PHY takes the patented QBeam physical layer — the same silicon inside every ExitPhi and AeroPhi node — and ships it as a plain PCIe 5.0 x16 card. Bytes only. No qubits on the wire. No teleportation. Just the QBeam PHY, doing the classical-carrier job it happens to be excellent at.

Stat strip

400 GB/s · Bidirectional aggregate (design target)
400 ns · Cut-through latency (design target)
PCIe 5.0 x16 · Host interface
4 lanes · QBeam ports on bracket
12 · Silicon configurations, 22 nm → 5 nm
App# 19/722,805 · Filed QBeam IP dependency

What it is

A PCIe 5.0 x16 half-height half-length HBA. One APM01-D-QPHY on board. Four QBeam ports on the bracket. Talks to your AutoPhi PCIe5-256, BGA256, and PCIe5-1536 accelerators directly, over the QBeam physical layer, at 400 GB/s bidirectional per card. Presents itself to the host operating system as a character device (/dev/qphy0 on Linux, \\.\qphy0 on Windows) plus an optional Verbs / NDIS shim so the same card doubles as an RDMA-capable NIC. AES-256-GCM at link-layer. SR-IOV for up to 64 virtual functions. Boots from on-card SPI flash — the host driver is optional for basic passthrough.

What the buyer receives

Wire protocol specification (docs/QPHY_PROTOCOL.md)
Host driver ABI for Linux + Windows (docs/HOST_DRIVER_CONTRACT.md)
Fabric topology catalog — point-to-point, star, ring, 2D torus, dragonfly (docs/FABRIC_TOPOLOGIES.md)
APM01-D-QPHY RTL scaffolding (hardware/APM01-D-QPHY/rtl/*.v)
12 silicon configurations, 7 nm → 2 nm, mapped to the AutoPhi Modern APM01..APM12 generational fade (parts/APM01-D-QPHY..APM12-D-QPHY/)
QPHY_HBA_BOARD reference: SPEC + BOM + STACKUP (hardware/QPHY_HBA_BOARD/)
Link-layer firmware in C + host daemon in Rust (firmware/)
SDK — C header + Python bindings + Rust crate (sdk/)
Deployment playbook for chassis / rack / row / facility scales (PLAYBOOK.md)
Worldwide commercialization rights to make, use, and sell products built from the disclosed technologies

What this purchase conveys

Documentation and commercialization rights — not intellectual property.

You receive:

The full text of every file in the Quantum PHY engineering package
The full ASIC RTL scaffolding and the HBA reference SPEC + BOM + STACKUP
The firmware and SDK sources
Worldwide non-exclusive commercialization rights

You do not receive:

No intellectual property is conveyed. The QBeam patent (via ExitPhi, USPTO Application No. 19/722,805) and all underlying IP remain the sole and exclusive property of Christopher Gabriel Brown.
The inventor retains the right to prosecute, maintain, license to others, and enforce all IP. This is not a patent license or assignment.

How this card differs from ExitPhi and AeroPhi

Quantum PHY is the workhorse: the one you buy by the tray to build a real fabric out of the classical accelerators you already own.

Portfolio siblings that plug directly in

ExitPhi (App# 19/722,805) — the QBeam PHY macro this card reuses.
AeroPhi (Project 55) — the six-tier fractal mesh consumer of the same QBeam PHY. Facility ceiling in PLAYBOOK.md hands over to AeroPhi at scales larger than one facility.
AutoPhi PCIe5-256 / BGA256 / PCIe5-1536 — the endpoint accelerators this card is designed to connect.
AutoPhi Future — the silicon architecture family. APM01-D-QPHY is fabricated through the AutoPhi Day-One production stack.
Super Dome (Project 6) — the American Dollar Blockchain ledger can commit transactions across a Quantum PHY fabric.

Dignity and clarity

We do not overstate. Quantum PHY is designated Foundry-ready (L4). What is on file: the concept, the wire protocol, full APM01-D-QPHY RTL, synthesis constraints (SDC), floorplan, DV testbench, HBA reference SPEC + BOM + STACKUP, firmware, SDK, and per-generation FOUNDRY_HANDOFF (foundry + PDK + flow selected per the AutoPhi Modern APM01..APM12 fade). Physical-design flow output present. QBeam itself is a filed non-provisional USPTO utility patent. What is not yet in hand: physical tape-out submission to any foundry (paperwork ready), KiCad schematic capture (CM scope), PCB layout (CM scope), prototype fab, loopback and BER measurements on real silicon, PCIe 5.0 compliance passes, and FIPS 140-3 certification for the crypto module. Performance figures are design targets, not measured guarantees.

We do not understate. This is a coherent PCIe card product with a filed IP dependency, a real ASIC RTL scaffold, and a real HBA reference. It is the fabric layer that turns the AutoPhi accelerator catalog into a rack-scale system without third-party silicon in the datapath.

Terms and contact

Per-card SKU tier — final unit price set at publication. Included at no extra charge inside All In One (20T) — the complete cri-one.com portfolio acquisition. Available only to companies incorporated, headquartered, and primarily operating in the United States. USD only. Patents and underlying IP retained by the inventor.

Structure (asset purchase, exclusive license, joint venture, revenue share, milestone-based) can be tailored to the acquiring organization.

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Communication by email and postal mail only — no phone calls, no brokers, no intermediaries.

Quantum PHY. The QBeam Transfer Card. Bytes only. No cables. No third-party silicon.

Quantum PHY — On-Card Architecture

Project 76 · docs/ · Rev 0.1 · 2026-07-30

This document describes the on-card block diagram, the datapath from host DMA to QBeam wire, and the boot / control paths.

1 Top-level block diagram

                     +---------------------- QPHY_HBA_BOARD ----------------------+
                     |                                                              |
  PCIe 5.0 x16 ------+---> PCIe Gen5 x16 Endpoint  ------+                          |
  (host system)      |     [ APM01-D-QPHY :: pcie_ep ]       |                          |
                     |                                    v                          |
                     |                        +------------------------+             |
                     |                        |   DMA Engine           |             |
                     |                        |   16 SQ / 16 CQ        |             |
                     |                        |   scatter-gather       |             |
                     |                        +-----------+------------+             |
                     |                                    |                          |
                     |             +--- Doorbell ---+     |                          |
                     |             |  MMIO-writable |     |                          |
                     |             |  by host       |     |                          |
                     |             +--------+-------+     |                          |
                     |                      |             v                          |
                     |                      +---> +---------------+                  |
                     |                            |   MAC         |                  |
                     |                            |  frame + CRC  |                  |
                     |                            |  + RS-FEC     |                  |
                     |                            +-------+-------+                  |
                     |                                    |                          |
                     |               +--------------------+---------------------+    |
                     |               |                                          |    |
                     |               v                                          v    |
                     |     +------------------+                       +------------------+
                     |     |   AES-256-GCM    |                       |     Boot ROM     |
                     |     |   link-crypto    |                       |    on SPI flash  |
                     |     +--------+---------+                       +--------+---------+
                     |              |                                          |
                     |              v                                          |
                     |     +-----------------+                                 |
                     |     |  PipeBeam align |                                 |
                     |     |  striping across|                                 |
                     |     |  4 QBeam lanes  |                                 |
                     |     +--------+--------+                                 |
                     |              |                                          |
                     |     +--------+--------+                                 |
                     |     |  QBeam PHY  x 4 |<--- CoolBeam clock -------------+
                     |     |  (TX + RX)      |     (thermal integrity)
                     |     +--------+--------+
                     |              |
                     |    bracket-side ports  (4x QBeam)
                     |              |
                     +--------------+---------------------------------------------+
                                    |
                              4 x QBeam wires to peer HBA

2 Data path in the TX direction

1. Host writes a Submission Queue Entry (SQE) into a host-memory SQ (16 SQs per PF; 16 per VF).

2. Host rings the doorbell — a 32-bit MMIO write to the APM01-D-QPHY's doorbell region.

3. APM01-D-QPHY's DMA engine fetches the SQE, then walks its scatter-gather list and DMAs payload into on-chip SRAM.

4. MAC framer wraps payload in the QPHY frame format (see QPHY_PROTOCOL.md) — 32-bit header, RS(255,239) FEC, 128-bit trailer.

5. AES-256-GCM encrypts the frame with the per-fabric link key (provisioned out-of-band).

6. PipeBeam aligner stripes the frame across 4 QBeam lanes, 8-byte granularity.

7. QBeam PHY modulates each lane onto the bracket-side wire. CoolBeam-clocked for thermal integrity.

8. QBeam wire carries the four lanes to the peer HBA.

3 Data path in the RX direction

1. QBeam PHY demodulates the four lanes into 4 parallel 8-byte streams.

2. PipeBeam aligner de-stripes the streams into a single byte-ordered frame.

3. AES-256-GCM decrypts and validates the auth tag. On tag failure, frame is dropped and an event is delivered to the event queue.

4. MAC de-framer validates FEC. Corrects up to 8 symbol errors per lane; drops the frame on uncorrectable error and delivers an event.

5. DMA engine DMAs payload into the destination scatter-gather list from the matching Receive Queue.

6. APM01-D-QPHY posts a Completion Queue Entry (CQE) into host memory.

7. APM01-D-QPHY raises MSI-X on the host.

4 Boot path

On PCIe reset, the APM01-D-QPHY's embedded microcontroller reads its boot image from the on-card SPI flash.
Boot image = link firmware (firmware/link/) — the state machine that manages PHY bring-up, RS-FEC lock, PipeBeam alignment, credit accounting.
The card can operate in basic passthrough mode without a host driver — link-layer counters and status LEDs still work.
With the host driver present, the daemon (firmware/host/) assigns the card its Local Identifier (LID) and provisions the AES-256-GCM key.

5 Control path

MMIO region: the APM01-D-QPHY exposes a 64 KiB MMIO BAR containing doorbells, per-queue configuration, per-VC credit windows, and control registers.
Sideband I²C: an on-board BMC (or the host's own BMC via slot sideband) can read link status, temperature, and error counters without touching PCIe.
Status LEDs: four LEDs on the bracket, one per lane, colour-coded (green = link up, amber = FEC correcting, red = link down).

6 Reset domains

PERST# (from PCIe): resets the entire APM01-D-QPHY including PHY and MAC.
Function-level reset (FLR): resets PCIe endpoint and DMA state; PHY stays up.
Link retrain (software-initiated): cycles the four QBeam lanes; PCIe stays up.
PHY-only reset: cycles a single QBeam lane for debug; other three lanes stay up in degraded mode.

7 Failure modes and their surfaces

8 Thermal design

The APM01-D-QPHY dissipates typical 38 W. On-card passive heatsink is sized for 42 W total board dissipation in 55 °C ambient with slot airflow of 200 LFM. CoolBeam integrity extends the PHY's operating envelope to +85 °C ambient without active cooling, which is the main thermal reason to prefer this card over an equivalent PCIe-over-copper HBA.

This archive contains 41 documents; 32 more beyond this preview. The complete folder ships as the product.

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