77-qphy-pcie-card

Valuation

Generous asset valuation: $28,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

QPHY PCIe Card — Cable-Free QBeam Endpoint

QPHY PCIe Card — Cable-Free QBeam Endpoint

Project 77 · cri-one.com portfolio · Author: Christopher Gabriel Brown

A PCIe 5.0 x16 half-height half-length add-in card that hosts a QBeam-enabled chip on-board. Aligned with the ExitPhi patent filing (USPTO App# 19/722,805): the chip's FCBGA package-top metallic structure serves simultaneously as the RF phased-array antenna for chip-to-chip data AND as the cold-side terminal array of a vertical thermoelectric cooling pump. There are no data cables on the bracket. PCIe fingers carry only the host↔chip control and DMA path; chip-to-chip traffic goes wirelessly through the package-top antenna to peer QBeam chips in nearby cards, chassis, or racks.

• Positioning: the patent-canonical PCIe form factor for QBeam. Sits alongside — not inside — the Quantum PHY 13-SKU product line, which describes a cabled-bracket variant.
• Filed IP dependency: ExitPhi (INTEGRATED WIRELESS DATACENTER FABRIC…), USPTO App# 19/722,805, filed 2026-06-27, 30 claims, pro se.
• Status: Foundry-ready (L4). SPEC + BOM + STACKUP on file; buyer signs the CM contract for schematic capture + layout + fab.

What sits in the package

77-qphy-pcie-card/
├── README.md                              # this file
├── SPEC.md                                # top-level technical spec
├── MANIFEST.json                          # machine-readable catalog
├── STATUS.md                              # subsystem state
├── LICENSE.md                             # docs + commercialization; IP retained
├── PRODUCT_BRIEF.md                       # one-page pitch
├── STORE_LISTING.md                       # store copy source
├── CONTACT_INFO.txt                       # licensor contact
├── qphy_pcie_card_store_description.html  # HTML for the live product page
├── hardware/
│   └── CARD/
│       ├── SPEC.md                        # card-level spec
│       ├── BOM.md                         # bill of materials
│       └── STACKUP.md                     # 12-layer stackup
└── figures/
    └── qphy-pcie-card.png                 # hero image

What makes this card different from the Quantum PHY 13-SKU line (project 76)

The 13 QPHY line SKUs continue as-is for buyers who prefer the cabled form factor.

Contact

Christopher Gabriel Brown — crioneaka@outlook.com · crioneaka@outlook.com

Communication by email and postal mail only.

QPHY PCIe Card — Product Brief (one page)

QPHY PCIe Card — Product Brief (one page)

Project 77 · cri-one.com portfolio · 2026-07-30

The problem

Every rack of AutoPhi accelerators — and every rack of anyone else's accelerators — still bristles with QSFP-DD, InfiniBand, PCIe-over-copper, and optical cages. Cables cost power, add latency, and force the rack designer to plan cable dressing around every card. **The one thing the ExitPhi patent already invented — a chip where the package-top metal is simultaneously an RF phased-array antenna and a thermoelectric cooling cold-side — has never shipped as a mainstream PCIe form factor.** Until now.

The invention

QPHY PCIe Card is a PCIe 5.0 x16 half-height half-length HBA that hosts a QBeam-enabled chip. Chip-to-chip data goes wirelessly, straight through the chip's package-top antenna to peer QBeam chips in nearby cards, chassis, or racks. The bracket has no cages, no cables — only a status LED and a service-only USB-C port. PCIe fingers carry only host↔chip traffic.

This is the patent-canonical form. The invention is filed as ExitPhi, USPTO App# 19/722,805, filed 2026-06-27, 30 claims, non-provisional utility, pro se. The card is the mainstream commodity embodiment of the same wireless-datacenter-fabric premise.

The card at a glance

• Form factor: PCIe 5.0 x16 HHHL, single-slot bracket, PCI-SIG CEM 5.0
• Silicon: APM07-D-QPHY-W (reference; any APM04..APM12 QPHY-W variant drops in)
• Host interface: PCIe 5.0 x16, 63 GB/s each direction, SR-IOV
• Chip-to-chip: wireless via package-top phased-array antenna (per patent §D–F)
• Package-top metal: simultaneously the antenna array AND the thermoelectric cooling cold-side
• Bracket: 1× status LED, 1× service USB-C, unpopulated by default
• Power: 75 W slot-only; typical 45 W
• Cooling: CoolBeam integrated on-chip; no host thermal accessory required

Why this ships alongside — not instead of — the Quantum PHY line (project 76)

The 13 Quantum PHY SKUs describe a cabled HBA variant (4× SFF-8674 QBeam cages on the bracket). Some buyers will prefer that shape — deterministic wired topology, easier to trace failures, sits in existing structured-cable racks. Some will prefer this shape — no cables, denser rack fill, aligned with the patent. This project adds one new product; it does not delete or modify any of the 13.

What the buyer receives

• Card-level SPEC + BOM + 12-layer STACKUP (drafted for one-pass KiCad capture by a CM)
• Reference silicon: APM07-D-QPHY-W (die = project 76's APM07-D-QPHY, new FCBGA-196 antenna package per patent §G)
• By reference: project 76's host driver ABI, C/Python/Rust SDK, wire-protocol framing, fabric topology catalog
• By reference: ExitPhi patent text (project 54)
• Deployment playbook (chip-to-chip line-of-sight considerations, rack layout notes)
• Worldwide commercialization rights

What the buyer does NOT receive

The underlying patents are retained by the inventor. QBeam / CoolBeam / PipeBeam (via ExitPhi App# 19/722,805) remain the sole property of Christopher Gabriel Brown. This is a documentation + commercialization-rights transaction, not a patent license or assignment.

Maturity — honest report

Foundry-ready (L4). SPEC + BOM + STACKUP on file. Physical-design flow output present. QBeam is a filed non-provisional USPTO utility patent. What is not yet in hand: KiCad schematic capture (CM scope), PCB layout (CM scope), prototype fab, PCIe 5.0 compliance, FCC / ETSI RF-emissions compliance, QPHY-W silicon tape-out. Performance figures are design targets from the ExitPhi patent record.

Price

USD $3,000,000,000 per card at inventor-set list. Sits above APM12-D-QPHY silicon-only ($2B, project 76) because this is a finished card SKU with integrated antenna+cooling silicon variant. Included at no extra charge inside All In One (20T).

Contact

Christopher Gabriel Brown — crioneaka@outlook.com · crioneaka@outlook.com

Communication by email and postal mail only.

QPHY PCIe Card — Technical Specification

QPHY PCIe Card — Technical Specification

Project 77 · Author: Christopher Gabriel Brown · Rev 0.1 (2026-07-30)

1 Scope

This specification defines the QPHY PCIe Card: a PCIe 5.0 x16 half-height half-length (HHHL) host bus adapter that hosts a single QBeam-enabled chip on-board. The card's chip-to-chip data path is wireless, delivered by the chip's FCBGA package-top phased-array antenna structure. There are no data cables on the bracket. This spec is faithful to the ExitPhi patent (USPTO Application 19/722,805) which specifies that "the only persistent physical attachment to a chip or to a rack-unit so equipped is an electrical power conductor."

2 Normative references

• USPTO Application 19/722,805 (ExitPhi, 30 claims, filed 2026-06-27, non-provisional utility, pro se) — the canonical source for QBeam, CoolBeam, and PipeBeam. Full text at ../54-exitphi-accelerators/PATENT_NONPROVISIONAL.md.
• PCI-SIG PCI Express Base 5.0 (r5.0 v1.0) — host interface compliance.
• PCI-SIG CEM 5.0 — mechanical form factor.
• FIPS PUB 197 — AES (for link-layer classical crypto over the wireless channel).

3 Terms and definitions

4 System context

Host chassis                                Other chassis / rack neighbors
+-----------------------+                   +--------------------------+
|                       |                   |                          |
|  +----- PCIe 5.0 x16 slot -----+          |     +----------------+   |
|  |                              |  wireless      |                |   |
|  |    QPHY PCIe Card            | <=================> Peer QPHY   |   |
|  |    (this card)               |    QBeam       |   PCIe Card   |   |
|  |                              |    (package-   |                |   |
|  |    +----------------+        |     top        +----------------+   |
|  |    | QPHY-W chip on |        |     antenna)                        |
|  |    | FCBGA-196      | . . . . . . . . . . . . . . . . . . .        |
|  |    | (antenna + TE  |        |                                     |
|  |    |  cooling top)  |        |                                     |
|  |    +----------------+        |                                     |
|  |                              |                                     |
|  |    Bracket: LED + service    |                                     |
|  |    port only. No cables.     |                                     |
|  +------------------------------+                                     |
|                                                                       |
+-----------------------------------------------------------------------+
    PCIe fingers = host <-> chip only

5 Physical / mechanical

• Form factor: PCIe 5.0 x16 HHHL, single-slot bracket per PCI-SIG CEM 5.0.
• Bracket contents: 1× status LED, 1× service port (USB-C, service-only, unpopulated by default per the patent's "service-port physical attachment used solely during manufacturing" clause). No SFP cages. No optical cages. No copper data connectors.
• Card outline: 167.65 mm × 68.90 mm.
• Line of sight: the chip's package-top antenna must not be blocked. Card is oriented so the package top faces up out of the slot (away from the motherboard); intra-chassis neighbors' cards must respect the antenna's radiation pattern (see PLAYBOOK for datacenter installation notes).

6 Silicon

The -W suffix marks the QPHY-W (wireless-form) package variant: same die as the corresponding APM-D-QPHY (project 76), packaged in FCBGA-196 per the patent instead of FCBGA-1024, with the metallic top structure implementing the antenna + thermoelectric pump per patent §D–F.

7 Host interface

• PCIe 5.0 x16 endpoint, 63 GB/s each direction, SR-IOV (64 VF).
• Doorbell / DMA / MMIO identical to project 76's driver ABI (../76-qbeam-transfer/docs/HOST_DRIVER_CONTRACT.md).
• Same C SDK / Python bindings / Rust crate (project 76 sdk/) apply verbatim; the host driver does not distinguish cabled QPHY vs wireless QPHY-W — the difference is entirely below the driver's abstraction line.

8 Wireless chip-to-chip data path (per patent)

• Frequency band: as defined in patent § BRIEF SUMMARY.
• Modulation: order-preserving antenna series per patent § C ("Order-preserving antenna series").
• Classical throughput target: per-pair chip-to-chip design target consistent with the ExitPhi WFA silicon family. Actual rate is a function of ambient RF environment, distance, and shielding.
• Quantum teleportation option: the chip's on-die entanglement pool (patent § E "Quantum-teleportation protocol") allows the same wireless channel to carry teleported qubits at 2 classical bits per qubit, when the deployment provisions a pre-distributed entanglement source.
• Range: intra-chassis (few cm) to intra-rack (< 1 m). Cross-rack via a peer chip that acts as a relay, per AeroPhi T5/T6 architecture (../55-aerophi-fractal-qbeam/).

9 Power

• Rail budget: 75 W slot-only (no external power connector).
• Typical draw: 45 W (mostly the QPHY-W silicon plus the thermoelectric pump).
• CoolBeam pump: integrated on-chip; requires no host thermal accessory beyond standard slot airflow (200 LFM at 55 °C ambient sufficient).

10 Deliverables inside the buyer's package

Full text of every file in this directory tree, plus by-reference:

• hardware/CARD/SPEC.md — card-level PCB spec sufficient for a CM to capture in KiCad/Cadence.
• hardware/CARD/BOM.md — full BOM.
• hardware/CARD/STACKUP.md — 12-layer PCB stackup.
• Project 76's RTL, host driver contract, SDK, wire protocol, fabric topology catalog, and 12-generation FOUNDRY_HANDOFF apply verbatim; this project reuses them and only adds the wireless-form card + antenna-native silicon variant.

11 Deferred / open items (buyer / CM / cert-lab scope)

• KiCad schematic capture for the card (SPEC + BOM + STACKUP are drafted to be sufficient for a one-pass capture without inventor involvement).
• PCB layout, Gerber generation, prototype fab, and bring-up.
• QPHY-W silicon tape-out (variant of the existing APM-D-QPHY die + new FCBGA-196 package with antenna metal top).
• PCI-SIG PCIe 5.0 compliance workshop.
• FCC / ETSI RF-emissions compliance filings (the wireless chip-to-chip band is subject to the same regulatory regime as the ExitPhi WFA family; see project 54 for details).

12 Revision history

QPHY PCIe Card — Status

QPHY PCIe Card — Status

Revision: 0.1 · Date: 2026-07-30 · Overall: ✅ Foundry-ready (L4). Full SPEC + BOM + STACKUP for the card, patent-faithful cable-free framing, silicon reuses project 76 die with a new FCBGA-196 antenna package. Layout, tape-out, and RF-cert filings are buyer / CM / cert-lab scope.

Subsystem status

What's downstream of the inventor deliverable

Same handoff boundary as project 76: SPEC + BOM + STACKUP + docs are the inventor deliverable. Everything below transfers at point of sale — not inventor scope:

• KiCad schematic capture and PCB layout (12-layer, PCIe TX/RX at 85 Ω, no controlled-impedance chip-to-chip runs since chip-to-chip is wireless).
• Gerber generation, prototype fab, DFM review, first-article inspection.
• Silicon tape-out of the FCBGA-196 QPHY-W package variant through the AutoPhi Day-One production stack or the buyer's own foundry.
• PCIe 5.0 compliance workshop at PCI-SIG.
• FCC / ETSI RF-emissions compliance filings for the wireless chip-to-chip band (subject to the same regulatory regime as the ExitPhi WFA family).
• Interop testing against ExitPhi WFA-Node / WFA-Hub / WFA-Mesh silicon.

Contact

Christopher Gabriel Brown — crioneaka@outlook.com

QPHY PCIe Card — Store Listing Copy

QPHY PCIe Card — Store Listing Copy

Source of truth for the store product page. The planned live page at cri-one.com/store/qphy-pcie-card.html renders from qphy_pcie_card_store_description.html in this directory.

SKU: QPHY-PCIE-CARD · Price: $3,000,000,000 · Category: Quantum PHY (id 3414) + Space & Defense (id 145)

Kicker

Project 77 · Cable-Free PCIe · The patent-canonical QBeam form factor

Title

QPHY PCIe Card

Subtitle

Cable-free PCIe 5.0 x16 endpoint · package-top antenna does the chip-to-chip

Foundry-ready (L4)

Lead paragraph

Every rack of AutoPhi accelerators — and every rack of anyone else's accelerators — still bristles with QSFP-DD, InfiniBand, PCIe-over-copper, and optical cages. The one thing the ExitPhi patent already invented — a chip where the package-top metal is simultaneously an RF phased-array antenna and a thermoelectric cooling cold-side — has never shipped as a mainstream PCIe form factor. Until now. QPHY PCIe Card hosts a QBeam-enabled chip on a standard PCIe 5.0 x16 HHHL bracket. Chip-to-chip goes wirelessly through the package-top antenna. The bracket has no cages, no cables — only a status LED and a service-only USB-C port. PCIe fingers carry only host↔chip traffic.

Stat strip

• PCIe 5.0 x16 · Host interface (63 GB/s per direction)
• 0 · Cables on the bracket
• FCBGA-196 · Package top = antenna + cooling (per patent §G)
• 75 W · Slot-only, no external power connector
• APM07-D-QPHY-W · Reference silicon (any APM04..APM12 W-variant drops in)
• App# 19/722,805 · Filed QBeam IP dependency

What it is

A PCIe 5.0 x16 HHHL add-in card that hosts a QBeam-enabled chip. Faithful to the ExitPhi patent (USPTO App# 19/722,805): the chip's FCBGA package-top metallic structure is simultaneously the RF phased-array antenna for chip-to-chip data AND the cold-side terminal array of a vertical thermoelectric cooling pump. Chip-to-chip data is wireless — no data cables anywhere. Sits in any standard PCIe 5.0 slot.

How this card differs from the Quantum PHY line (project 76)

Both product families are supported. Some buyers want a wired topology (project 76); some want the patent-faithful wireless form (this project). Choose whichever fits your rack.

What the buyer receives

• Card-level SPEC + BOM + 12-layer STACKUP (drafted for one-pass KiCad capture by a CM)
• Reference silicon spec (APM07-D-QPHY-W = APM07-D-QPHY die + FCBGA-196 antenna package per patent §G)
• By reference: project 76's host driver ABI, C/Python/Rust SDK, wire-protocol framing, fabric topology catalog
• By reference: full ExitPhi patent text (project 54)
• Deployment playbook (chip-to-chip line-of-sight, rack layout)
• Worldwide commercialization rights

Terms and contact

USD $3,000,000,000 per card. Included at no extra charge inside All In One (20T). Available only to companies incorporated, headquartered, and primarily operating in the United States. USD only. Patents and underlying IP retained by the inventor.

Christopher Gabriel Brown — crioneaka@outlook.com · crioneaka@outlook.com. Communication by email and postal mail only.

QPHY PCIe Card. Zero cables on the bracket. The QBeam antenna is on the package top, where the patent puts it.

QPHY PCIe Card — Bill of Materials

QPHY PCIe Card — Bill of Materials

Project 77 · hardware/CARD/ · Rev 0.1 · 2026-07-30

Active

Passives (summary)

Sparser than the cabled counterpart in project 76 because there are no bracket cages (16 ESD arrays gone), no chip-to-chip diff-pair terminations, and no length-match support networks.

Specific critical parts

Mechanical

Note: No HS1 heatsink — the CoolBeam thermoelectric pump on the U1 package top replaces it. U1's package top must be free-air (unobstructed) so the antenna radiates and the pump vents.

Sourcing notes

• U1 (APM07-D-QPHY-W) is fabbed on IFS 18A. Package is FCBGA-196 with a metallic top implementing the CoolBeam antenna+cooling structure per the ExitPhi patent §D–G. Sample lead time from tape-out: 20 weeks; production 26 weeks.
• All commercial parts are dual-sourced except U1 and the Rakon clocks.

Approximate BOM cost (production volume ≥ 10k units)

Meaningfully cheaper than project 76's cabled counterpart (~$93 excluding U1) because 4 SFF-8674 cages, 16 ESD arrays, and their support passives are gone.

QPHY PCIe Card — Board Reference

QPHY PCIe Card — Board Reference

Project 77 · hardware/CARD/ · Rev 0.1 · 2026-07-30

1 Mechanical

• Form factor: PCI-SIG CEM 5.0, HHHL, single-slot bracket.
• Card outline: 167.65 mm × 68.90 mm.
• PCIe finger: standard x16 gold fingers per CEM 5.0 §3.2.
• Bracket contents:
• 1× status LED (bicolor green/red)
• 1× service USB-C port (unpopulated by default; used only during manufacturing per the ExitPhi patent's clause on "service-port physical attachment used solely during manufacturing")
• No SFP cages. No optical cages. No copper data connectors.
• Package orientation: U1's package top (with the antenna+CoolBeam metal) must face away from the motherboard so its radiation pattern is not blocked. This puts U1 on the front side of the card, near the bracket edge, with the heatsink omitted (the CoolBeam pump replaces it).

2 Silicon

Note the sparse BOM compared to project 76's cabled HBA — the wireless approach removes 4 SFF-8674 cages, 16 ESD arrays, all the diff-pair terminations, and their supporting passives.

3 Power

Slot-only. No external power connector.

Total board dissipation: 45 W typical, 68 W max (within CEM 5.0's 75 W slot budget).

4 Clocks

The wireless PHY's carrier clock is generated inside U1 from the on-die PLL; no external RF reference on the card.

5 What the CM does not need to route

Because chip-to-chip is wireless:

• No length-matched 100 Ω differential pairs to bracket connectors
• No PCB-level shielding for the chip-to-chip channel
• No via-back-drilling on the chip-to-chip pairs (there are no chip-to-chip pairs to route)

Result: the card's high-speed routing burden is limited to PCIe 5.0 x16 to the fingers. Layout complexity is significantly lower than a comparable cabled HBA of the same throughput.

6 Bring-up plan (for the CM)

1. Power-only bring-up: all rails come up in sequence; no U1 populated yet.

2. Boot-flash bring-up: load U1 boot ROM, apply PERST# release, verify UART banner on service USB-C.

3. PCIe link-training: insert into a compliance host, verify Gen5 x16 at LTSSM L0.

4. Antenna self-test: U1's built-in antenna BIST radiates a test pattern and measures its own back-reflection (return-loss). Verify RL < -10 dB across the operating band.

5. Chip-to-chip link: bring up two cards in the same chassis, run LINK_HELLO / LINK_ACK exchange, verify credit-based flow control.

6. PCIe compliance: submit to PCI-SIG for Gen5 workshop.

7. RF compliance: submit to certified test lab for FCC / ETSI emissions on the QBeam band.

7 Layer stackup

12 layers, standard FR-4 Tg170. Details in STACKUP.md.

8 DFM constraints

• Minimum trace width: 3.5 mil (85 µm)
• Minimum drill: 8 mil (200 µm)
• Class 6 fab tolerances per IPC-6012
• ENIG surface finish

QPHY PCIe Card — Layer Stackup

QPHY PCIe Card — Layer Stackup

Project 77 · hardware/CARD/ · Rev 0.1 · 2026-07-30

12-layer FR-4 stackup. Simpler than project 76's cabled counterpart because there are no chip-to-chip diff-pair layers to reserve; PCIe is the only high-speed signal class on the card.

Layer table

Total thickness: 1.60 mm (±10 %) · Material: FR-4 Tg170, halogen-free.

Impedance targets

No chip-to-chip differential-pair spec — chip-to-chip is wireless.

Length matching

Zero length-match rules for chip-to-chip channels (they don't exist on this card).

Via structure

Manufacturing class

• IPC-6012 Class 6 signal layers
• IPC-A-600 Class 3 finished appearance
• ENIG surface finish (0.05 µm Au / 3 µm Ni min)
• Solder mask: LPI green, both sides
• UL 94V-0 flammability

Notes for the CM

• Back-drill all PCIe vias — stub length must be < 6 mil for the Gen5 bit-time budget.
• Leave the area directly above U1's package top unobstructed by any component, stiffener, or bracket. The antenna radiates upward.
• Split-plane between VCC_CORE and VCC_ANT on L6/L7 must have ≥ 20 mil isolation. No signal crossings.
• Verify Er at 156.25 MHz (MAC clock) and at the QBeam antenna carrier frequency on the impedance coupons.

This archive contains 8 documents. The complete folder ships as the product.