74-bga_library-validate
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74 — BGA Library Validate
74 — BGA Library Validate
Validation harness for the AutoPhi BGA package family, and the home of the
intermediate ladder added on 2026-07-25.
Source of truth remains project 40 (40-autophi-bga256), per
docs/LIBRARY_GOVERNANCE.md: *"These must live in 40-autophi-bga and be treated
as source-of-truth artifacts."* Nothing here forks or duplicates the library —
this project only regenerates and checks it.
Why the ladder exists
The family previously stepped straight from 256 balls to 1536 — a 6× jump with
nothing between. There were eleven body variants (four BGA-256, seven BGA-1536),
but only two ball counts. A design needing roughly 600–1,100 I/O had to take a
package with far more balls and area than it used.
docs/CANONICAL_DIMENSIONS_MATRIX.md lists the canonical AutoPhi V19 Pinnacle
baseline as 32 mm package width, 384..1536 pins across SKUs — so 576, 900 and
1156 sit inside the documented range rather than inventing a new class.
Pad diameters hold the 0.45 × pitch ratio the v19_default profile already uses
(0.9 mm pad at 2.0 mm pitch), landing clearances at 0.55–0.70 mm — comfortable for
standard fabrication rather than aggressive.
BGA-900 is the one to note. A 30 × 30 grid at 1.0 mm pitch gives a 29 mm ball
span inside a 32 mm body, which matches the canonical 32 mm die exactly. Neither
existing package did: BGA-256 spans 15 mm (too small), BGA-1536 spans 95 mm
(roughly three times too large).
Current status — pin assignment pending
Geometry, footprint, symbol and pinmap are consistent and cross-validated for all
three. Signal assignment is not complete. After running the seeding pipeline
the working pinmaps still read:
seed_ab_domains.py and apply_power_policy.py populate the power and domain rows
only. Assigning the remaining signals is an engineering exercise — deciding what
each ball actually does — and was deliberately not auto-filled, because
inventing ~860 signal names would put fiction into a source-of-truth library.
This is the same state the catalog recorded for BGA-1536 before its pinout was
worked out: "scaffolded; pin assignment pending." By contrast, BGA-256 and
BGA-1536 now carry zero TBD entries.
Consequence: validate_bga_library.py fails on all three with
TBD signals remain, and will keep failing until the pinouts are assigned. That
failure is accurate and should not be suppressed.
Reproduce
python regenerate.py # rebuild all three from their profiles
python validate.py # validate the whole family, ladder included
regenerate.py is deterministic — it drives project 40's own generators from the
named profiles, so the geometry can be rebuilt without remembering flags.
Change set (per governance)
For each of BGA-576, BGA-900 and BGA-1156:
1. Footprint — 40/libs/footprints/AutoPhi.pretty/BGA-<n>_<body>_P<pitch>.kicad_mod
2. Pinmap template — 40/pinmaps/AUTOPHI_BGA<n>_pinmap_template.csv
3. Working pinmap — 40/pinmaps/AUTOPHI_BGA<n>_pinmap_working.csv
4. Symbol — 40/libs/symbols/AutoPhi_BGA<n>_working.kicad_sym
5. Catalog entry — 40/docs/BGA_CATALOG.md
6. Profile — 40/scripts/profile_switch.py
Open question this resolves
Project 28 (100 YFlops IC) specifies a 32 mm square chip but named no package, and
the two existing options fitted badly — which is why pairing it to a board was
ambiguous. BGA-900 gives that die a package that actually fits.
Note that CANONICAL_DIMENSIONS_MATRIX.md marks Semiconductor Method Discovery 15
as "Special reference only — do not override board-series defaults", with V19
Pinnacle as canonical. So its 167 × 69 mm HHHL card figure does not bind the
board-series form factor.
BGA Escape on the AutoPhi 1536 Interposer — What Actually Constrains It
BGA Escape on the AutoPhi 1536 Interposer — What Actually Constrains It
*Working record. Every number here was measured on
autophi-1536-interposer.kicad_pcb or derived from its geometry. Where a
prediction was wrong, the wrong prediction is left in.*
The board
Fan-out is a pure 2.5× radial scaling: die pad (i,j) maps to board pad
(i,j), same array, bigger pitch.
1. The per-layer via load is invariant
This is the result worth keeping.
A ball landing on signal layer k needs two vias:
- a microvia spanning TOP → k, which crosses k signal layers
- a blind via spanning k → BOTTOM, which crosses N − k + 1
Add them:
k + (N - k + 1) = N + 1 for every k
The layer choice cancels. Every ball costs exactly N+1 barrel-layer
crossings no matter where it lands.
960 balls × 7 = 6,720 barrel-layers ÷ 6 layers =
1,120 via keepouts per signal layer, invariant under any assignment.
Consequences
- No layer-assignment strategy can reduce via congestion. Not
balancing, not shallow-first, not deepest-first. This is not a heuristic
claim; the quantity does not vary.
- Layer balancing is still worth doing — it balances trace
congestion, which is a different resource. Measured: failures fell from
56 to 37 on a 250-ball sample when layer choice went from shallow-first
to least-loaded-first.
- The observed layer load on the full run came out
160 / 159 / 159 / 160 / 159 / 159 — exactly 960 ÷ 6. The algebra
predicts the measurement.
- More signal layers barely help, because the load scales as
(N+1)/N:
Going from 6 to 12 signal layers — doubling the stackup — buys 7%.
2. Netclass clearance is not the constraint (predicted wrong)
The prediction was that trace pitch was binding, because at 0.200 mm
clearance exactly one 0.075 mm trace fits between two adjacent die pads,
and at 0.100 mm two do. Doubling channel capacity should have paid.
Measured, same board, same router, 250-ball sample:
Identical. The conclusion had been written before the run. Trace pitch
is not what is choking the escape; via placement is.
(Separately: an HDI vendor's published capability confirms 3/3 mil
trace/space is manufacturable, so the 0.075 mm floor is real and the
0.200 mm netclass is self-imposed. It is still not the lever.)
3. What actually binds: the two grids beat against each other
0.8 mm and 2.0 mm on a shared origin, ratio 2.5 — not an integer. The
grids drift in and out of phase.
- 240 board pads land within 0.50 mm of a die pad
- closest pair: 0.283 mm
At 0.283 mm a 0.20 mm microvia pad and a 0.40 mm blind via pad
physically overlap. No clearance rule reaches that.
36 translations of the BGA grid were tested (0 to 1.0 mm in 0.2 mm
steps, both axes). Every one was worse than or equal to the design as
drawn. The board is already at the optimum offset.
The collision is not absolute, though. The microvia spans TOP..L and
the blind via spans L'..BOTTOM; those miss each other whenever L is
shallower than L'. So it is an ordering constraint, not a wall.
4. The fix: dog-bone the blind vias
Stop putting the via in the pad. Offset it, and join the two with a
short neck on BOTTOM.
Sweep of candidate sites around each colliding pad:
dog-bone reach 0.35 mm: 240/240 colliding pads get a legal via site, 0 stuck
A 0.9 mm pad on a 2.0 mm grid has roughly 0.55 mm to give, so 0.35 mm is
comfortably inside the budget.
Applied to the board: 92 of 96 colliding blind vias relocated, 89 of
them needing only 0.25 mm, max 0.60 mm. Four had nowhere legal to go.
DRC unchanged — no new violations.
Constraint set for a relocated via
A new via site must clear, on every layer its barrel passes through:
The neck itself must also clear other pads (0.55 mm) and other vias.
Forgetting the trace row cost a round. Checking a new via site against
pads and other vias but not against traces produced 17 violations, all
Blind via vs Track. This was the third time the same omission
appeared in a different script — see §6.
5. The fix that mattered more: place vias before traces
Diagnosing stuck balls after the dog-bone gave a clean signature:
WHY ring 7 cell (12,7) SIG1 micro ok blind trace@SIG2 SIG2 micro ok blind trace@SIG2 SIG3 micro trace@SIG3 blind ok SIG4 micro trace@SIG3 blind ok
The microvia is legal only on shallow layers, the blind via only on deep
ones, and they must be the same layer. Every blocker is a trace —
copper laid by a ball that happened to route earlier.
So the router became two-phase:
1. Assign every via a layer, with no copper on the board. Feasibility
is purely via-vs-via, which is far less constrained. Once a ball owns
its barrel, no later trace can take it.
2. Route traces around the now-fixed barrels.
The remaining failures became purely "no path", which is an ordinary maze
routing problem rather than a structural dead end.
6. Errors worth not repeating
Every one of these was found by DRC or by instrumentation, never by
reasoning — and two of them were confidently reasoned about wrongly
first.
1. A via is a barrel, not a point. SetLayerPair(TOP, SIG5) puts
copper on SIG1–SIG4 as well. Modelling only the landing layer produced
shorts through four layers.
2. The binding clearance is the netclass, not the board minimum.
0.200 mm, not min_clearance 0.075. Channels sized off the floor route
cleanly and then fail DRC.
3. Vias collide on layers the router never draws on. A die pad
0.283 mm from a board pad meets it on PWR1 — a plane layer. Via
feasibility must be checked across all twelve copper layers.
4. Moving a via invalidates its zone antipad. Refill before saving or
every barrel shorts to the plane it crosses.
5. Clearing traces does not clear via layer pairs. After a wipe, 451
unrouted balls still had microvias parked at TOP–SIG6 while the model
had reserved only TOP–SIG1: 199 shorts. Collapse unrouted vias to
the span actually reserved.
6. Reserve the guaranteed barrel, never the worst case. Reserving
TOP–SIG6 for every waiting ball blocks all six layers at all 1,536 die
pads simultaneously and leaves single-cell channels. Reserve TOP–SIG1
for microvias and SIG6–BOTTOM for blind vias: those are certain.
7. Never block a diagonal by its bounding box. SIG1 read as 64%
occupied when the true figure was 13%. Rasterise the swept area.
8. Keep keepout radii fractional. A diagonal blocked at an integer 5
cells (0.25 mm) where 5.5 (0.275 mm) is required leaks half a cell —
35 clearance violations, all between 0.177 and 0.187 mm.
9. Check new geometry against traces, not just pads and vias. Three
separate scripts, same omission each time.
7. Open
- Microvias are undersized for manufacture. 0.20 mm pad on 0.10 mm
drill = drill + 0.10 mm. A representative HDI vendor wants drill +
0.008" typical, drill + 0.006" advanced. This is what the 199
annular_width + 199 via_diameter DRC entries have been reporting.
Fix: advanced laser drill 0.0025" (0.0635 mm) with a 0.216 mm pad gives
a 3 mil annular ring, meets the advanced spec, and slightly shrinks
the keepout. Growing the pad instead would cost coverage.
- Copper pours on the signal layers are not placed. Planes are poured;
signal layers are not.
- Rip-up and retry. The remaining failures are all "no path". A router
that can rip up a blocking trace and re-route both nets is the standard
next step.
Tools
AutoPhi BGA Library — AUTOPHIBGA900 (v1)
AutoPhi BGA Library — AUTOPHI_BGA900 (v1)
30 x 30 ball grid, 1.0 mm pitch, 32 x 32 mm body. 900 balls.
The intermediate package between AUTOPHI_BGA256 and AUTOPHI_BGA1536.
Contents
library/
AUTOPHI_BGA900_pinmap.csv per-ball bank, signal, domain, direction
AutoPhi.pretty/
BGA-900_32x32mm_P1.0mm.kicad_mod KiCad footprint, 900 pads
AutoPhi_BGA900.kicad_sym single-unit symbol, 900 pins
AutoPhi_BGA900_units.kicad_sym 8-unit symbol for practical schematic use
reference-board/
autophi-bga900.kicad_pcb layout reference (see below)
autophi-bga900.kicad_sch + .net matching schematic and netlist
fp-lib-table / sym-lib-table library paths
Ball allocation
25.0% ground and 12.5% power — the 2:1 ground-to-power split read off the
existing 256 and 1536 packages, so the 900 is consistent with the parts your
boards already consume.
Placement follows normal BGA practice rather than filling rows in order:
- HSIO on the outer rings. High-speed differential pairs get short escape
routes to the board edge instead of long buried vias and layer changes.
- Power and ground in the core, on a checkerboard. Every power ball has an
adjacent return, which is what keeps loop inductance low.
- MGMT in the band between. Low-speed control tolerates longer routes.
Differential pairs sit on horizontally adjacent balls so p/n stay length-matched,
and a pair is never split across a row boundary. Each lane carries both
directions — a transmit-only endpoint could never complete link training.
The 8-unit symbol
900 pins in one symbol is 570 mm tall; an A3 sheet is 297 mm. AutoPhi_BGA900_units.kicad_sym
splits the part into 8 units of at most 120 pins, grouped by bank, so it is
actually usable on a drawing.
About the reference board
This is a layout reference, not a working design. It demonstrates the
footprint escaping to a PCIe x16 edge connector alongside four TI DS80PCI810
retimers, and it is useful for studying escape routing and fanout.
It will not function as built, and specifically:
VDD_COREreaches 112 balls but has no supply — no VRM is present- 499 of 900 balls are unconnected; of the 401 connected, 337 are power or
ground, leaving 64 signal balls
- no component values — 223 capacitors with no capacitance specified
- footprints carry no library identity, so no BOM or pick-and-place
- reference designators are positional, assigned by pad count and order
- board outline is 267.00 x 109.07 mm — full height, but a non-standard length
Schematic and board are verified consistent with each other: 266 components,
377 nets, 1380 pads, every pad agreeing on both pad name and net. Importing the
netlist is a no-op. That makes the board safe to open and edit without KiCad
offering to delete the routing — it does not make it a product.
Licence
Library artifact, v1 frozen. See the store listing for licence terms.
This archive contains 3 documents. The complete folder ships as the product.