74-bga_library-validate
Asset valuation: $3,000,000,000. Validation harness for the AutoPhi BGA package family, and the home of the intermediate ladder added on 2026-07-25. Source of truth remains project 40 (40-autophi-bga256), per docs/LIBRARYGOVERNANCE.md: "These must live in 40-autophi-bga and be treated
A chip should sit in a package that fits it. The AutoPhi family had two packages: a 256-ball one spanning fifteen millimetres and a 1,536-ball one spanning ninety-five, against a canonical die thirty-two millimetres square. One was too small, the other roughly three times too large; a design needing six hundred to eleven hundred I/O took far more package than it used. Project 74 closes that gap.
It is the validation harness for the AutoPhi BGA family and the home of the intermediate ladder, for board and package engineering buyers and licensees of that family. It regenerates footprints, pinmaps, symbols and the reference board from named profiles and measures ball count, grid, pitch and pad-to-pad clearance from the footprint itself rather than trusting the filename. A non-zero exit code on failure makes it an automated gate. The ladder adds BGA-576, BGA-900 and BGA-1156. The centrepiece is BGA-900: a thirty-by-thirty grid at one-millimetre pitch, a twenty-nine millimetre ball span inside a thirty-two millimetre body, matching the canonical die exactly and giving project 28's 100 YFlops IC a package that fits. A nine-hundred-pin symbol stands taller than any sheet, so it ships as eight bank-grouped units sized for A3.
The buyer gets 170 files: thirty-eight Python scripts, forty-nine KiCad schematic sheets, seven boards, a DRC report, and the PCIe 5.0 reference carrier, a layout reference rather than a working design, whose 1,380 pads agree on name and net. The harness and the ladder are yours to build on; the AutoPhi IC and its patent filings remain with Christopher Gabriel Brown.
Description
74-bga_library-validate — AutoPhi BGA Package Family Validation Harness & BGA-900 Engineering Toolkit
Inventor: Christopher Gabriel Brown
Patent coverage: USPTO 18/370,908 (AutoPhi quantum-battery and propulsion IC) and umbrella USPTO 19/540,453 (Integrated Technology Portfolio) — patent value flows through the consuming board projects that depend on this canonical library foundation
Status: v1 frozen · Validator-clean release · BGA-900 pinmap fully assigned · Reference board verified consistent · Product bundle APV19-BGA-0900-V1 assembled and store-ready
Overview
Project 74 is the validation harness for the entire AutoPhi BGA package family and the home of the intermediate ball-count ladder that bridges the gap between BGA-256 (16 × 16, 256 balls) and BGA-1536 (32 × 48, 1,536 balls). Before this project the family stepped directly from 256 to 1,536 — a 6× jump with nothing between. Any design needing roughly 600–1,100 I/O had to take a package with far more balls and area than it used.
The harness regenerates and cross-validates the complete family — footprints, pinmaps, symbols and reference board — deterministically from named profiles. It wraps project 40's own generators so geometry can be rebuilt without remembering flags, and it adds a geometry report the underlying validator does not produce: ball count, grid, pitch and pad-to-pad clearance measured from the footprint itself rather than trusted from the filename. Exit code is non-zero if any entry fails, so it is usable as an automated gate.
The centrepiece is BGA-900 : a 30 × 30 grid at 1.0 mm pitch giving a 29 mm ball span inside a 32 mm body, which matches the canonical 32 mm die exactly. Neither existing package did — BGA-256 spans 15 mm (too small) and BGA-1536 spans 95 mm (roughly three times too large). BGA-900 gives project 28's 100 YFlops IC a package that actually fits its specified 32 mm square chip.
The project comprises 170 files : 38 Python scripts totalling 5,366 lines of code, 49 KiCad schematic sheets, 7 KiCad PCB files, KiCad symbol libraries, reference-design PDFs, a DRC report, a Magento product import CSV, and the assembled product bundle.
AutoPhi BGA Package Family — Complete Ladder
The canonical AutoPhi V19 Pinnacle baseline specifies 32 mm package width, 384–1,536 pins across SKUs. The three intermediate entries (BGA-576, BGA-900, BGA-1156) sit inside the documented range rather than inventing a new class. Pad diameters hold the 0.45 × pitch ratio the v19_default profile already uses (0.9 mm pad at 2.0 mm pitch).
Bank ratios are not invented — they are read off the two packages that are already canonical. BGA-256 and BGA-1536 both land on exactly 25.0% ground (1 ball in 4), 12.5% power (1 ball in 8), and 62.5% signal (HSIO + MGMT). That 2:1 ground-to-power split with a third of the array on power delivery is a conventional high-performance BGA scheme.
Placement follows normal BGA practice. HSIO differential pairs sit on the outer rings for short, clean escape routes. Power and ground interleave on a checkerboard through the core, giving every power ball an adjacent return path — which keeps loop inductance low. Differential pairs sit on horizontally adjacent balls so p/n stay length-matched, and a pair is never split across a row boundary. Every lane carries both directions — a transmit-only endpoint could never complete link training.
Eight-Unit Symbol Architecture
900 pins in a single KiCad symbol stands 570 mm tall . An A3 sheet is 297 mm. The symbol is physically larger than any sheet it could sit on, so no amount of wire generation can produce a workable schematic. The eight-unit symbol solves this by splitting the part into bank-grouped units capped at 120 pins each — about 152 mm tall, comfortable on A3 with room for wires and labels.
Geometry constants: body width 50.8 mm, pin length 2.54 mm, pin pitch 2.54 mm, wire length 5.08 mm. Wiring computes pin positions from the same geometry the symbol builder uses — a 0.01 mm mismatch silently produces no connection in KiCad, and symbol-library Y runs opposite to schematic Y.
Pinout Assignment Engine
The assign_pinouts.py script (219 lines) assigns signals to all three intermediate packages using the canonical ratios and BGA placement conventions.
Signal Class Description Ball Naming
PCIe TX lanes 16 differential pairs, both directions PETp0_BGA–PETp15_BGA / PETn0_BGA–PETn15_BGA
PCIe RX lanes 16 differential pairs, receive direction PERp0_BGA–PERp15_BGA / PERn0_BGA–PERn15_BGA
Management control SMDAT, SMCLK, SPI (MOSI/MISO/SCK/CSn), JTAG (TCK/TMS/TDI/TDO), RESETn, PWRGD Named signals
The reference board demonstrates the BGA-900 footprint escaping to a PCIe x16 edge connector alongside four TI DS80PCI810 retimers. It is a layout reference, not a working design .
Schematic and board are verified consistent: all 1,380 pads agree on both pad name and net. Importing the netlist is a no-op. The board is safe to open and edit without KiCad offering to delete the routing.
Board outline (malformed shape) 2 J1 Edge.Cuts segments — PCIe connector card-edge notch geometry
Footprint library not configured 2 AutoPhi library warnings for U1 and J1
Silkscreen clipped by solder mask 6 Reference field of BGA overlapping solder-mask openings on pads V14–V17, U14–U15
The peripheral schematic is generated in two redriver variants sharing nine of ten sheets. Both carry the same risk-labelling philosophy: the TI variant is buildable today with published test data; the AutoPhi variant has no TI dependency and no test data.
Sheet Section Key Components
10 PCIe Edge + Sideband J1 PCIe x16 (164 pins), REFCLK+/−, PERST#, PRSNT1#/PRSNT2#, CLKREQ#/WAKE#, SMCLK/SMDAT
11 PCIe AC Coupling C1–C64 (220 nF series caps on TX lanes, spec-mandated)
12 Power Tree TPS75725 (12 V), ADP1706-1V0 (VDD_CORE), LDOs for VDDIO_HS, VDDIO_MGMT, VDDA_HSIO_PCIE, VDDA_HSIO_QSFP
19 (TI) PCIe Repeater 4× DS80PCI810 (8 Gbps 8-channel linear redriver), SMA eye-diagram breakouts, VDD_SEL strap
19 (AutoPhi) PCIe Repeater 4× APH_REDRIVER (design target, unbuilt), SMA probe points retained
VDD_CORE VRM Sizing Analysis
The size_vrm.py script (107 lines) sizes the core voltage regulator from the board's own stated policy. Conversion is 12 V to 1.0 V — a 12:1 step-down. Duty cycle lands near 8.3%, where buck converters face very short on-times. Realistic efficiency at this ratio and current is 87%. Switching frequency is 600 kHz per phase; inductor ripple fraction 30%; per-phase ceiling 25 A.
Scenario P out I out Phases A/phase L (nH) P in I 12V A/ball Loss PCIe Budget
Board policy (75 W in) ~49 W 49 A 2 24.4 A ~63 56 W 4.7 A 0.44 A 7 W OK on slot power alone
SMD-15 / 100 YFlops 235 W 235 A 10 23.5 A ~65 270 W 22.5 A 2.10 A 35 W Needs 6-pin + 8-pin aux
112 core-power balls is generous: even at the highest scenario the per-ball current stays modest, so the package is not the limit — the VRM is. Output capacitance is set by transient response, not ripple, at these currents.
Validation Pipeline
The validation harness ( validate.py , 91 lines) wraps project 40's validate_bga_library.py and validates all five BGA family members in a single pass.
The geometry function measures directly from each footprint file: ball count, column/row count, pitch, X/Y span, pad diameter and pad-to-pad gap. The regeneration pipeline ( regenerate.py , 94 lines) is deterministic and mirrors the governance order: footprint → pinmap template → working pinmap → seed → symbol.
Board Back-Annotation Pipeline
A four-stage pipeline converts the reference board into a schematic-verified project.
Stage Script Lines Function
1 extract_board_model.py 124 Extract 266 components, 1,380 pads, 377 nets into board_model.json
2 stamp_refs.py 106 Write reference designators onto 266 footprints (lost in Allegro→KiCad conversion)
3 board_to_schematic.py 233 Generate 9-sheet schematic from board model with per-pad wires and global labels
4 build_board_root.py 74 Tie sheets into hierarchical root, matching sheet-block UUIDs
apply_nets_to_board.py (127 lines) maps BGA signal names to board nets using derived mappings — GND direct, PCIe lanes to the ASIC side of AC coupling caps (the _C suffix matters: mapping to bare names would short the BGA past the caps and redrivers). add_core_rail.py (104 lines) creates the VDD_CORE net and bonds 112 core-power balls, with a Cmts.User documentation note recording the current requirement: 59 A at 58.7 W / 100 A at 100 W / 235 A at 235 W (1.0 V core).
plan_bga900_swap.py 149 Compute label assignment for swapping U16 from BGA-256 to BGA-900 — 169 of 256 balls map by name on first pass; DDR3, charger, and control vocabulary placed on spare MGMT_IO balls
swap_bga256_to_900.py 171 Execute the swap on 01_central_processor.kicad_sch — replace lib_symbols, symbol, and re-emit wires + labels
swap_bga256_to_900_units.py 187 Swap using the eight-unit symbol variant for practical drawing use
wire_bga900_to_qsfp.py 109 Wire BGA-900 to Amphenol U95T151100A QSFP28 cage (J6, 50 netted pads) — lane numbering: cage counts 1–4, library counts 0–3; control signals on spare MGMT_IO balls
wire_refclk_to_bga.py 88 Land Si5351 QSFP_REFCLK on a spare single-ended HSIO ball — placed on HSIO (not MGMT) because a SerDes reference clock on a low-speed ball routes badly
group_sheets.py 193 Group DDR3 and power sheets under parent sheets; safe because all 27 sheets communicate purely through global labels (0 local, 0 hierarchical)
fix_lib_nickname_collision.py 128 Rename footprint library nickname autophi to autophi_ic — KiCad compares case-insensitively on Windows, causing collision with AutoPhi
add_missing_parts.py 147 Add 17 missing ICs via KiCad's Python API (pcbnew) — four unparseable ZQSFP placeholder footprints had poisoned the .pretty library
consolidate.py 104 Gather board, schematic, sheets and netlist into one KiCad project; rewrite library tables with correct relative paths
package_bga900_product.py 212 Assemble APV19-BGA-0900-V1 product bundle with self-resolving library tables and verified sheet references
make_bga900_product_csv.py 239 Build Magento import CSV — price derived from 256/1536 line ($203.125/ball → $250,000 for 900)
Automation and Overnight Pipeline
The _tools/ directory contains 13 files (including 2 failed experiment files) for automated routing and overnight processing.
Tool Lines Function
overnight_pipeline.py 256 One-shot overnight pipeline for 256/900/1536: snapshot, Freerouting attempt (time-limited), escape coverage, fab package rebuild, store description refresh, Magento upload
overnight_pipeline_fix.py 152 Patched pipeline variant
freeroute_overnight.py 124 Freerouting session runner (Freerouting 2.2.4, handles NullPointerException gracefully)
tidrd14.zip / tidrd14/ TI TIDA-00423 reference design — DS80PCI810 PCIe Gen-3 retimer evaluation board; includes OrCAD schematic ( .DSN ), KiCad PCB conversion, and project files
tidrd10.pdf TI reference-design document
tidu796.pdf TI test report covering PCIe Gen-3 Tx equalisation, eye diagrams at 2.5/5/8 Gbps, automatic link equalisation compliance, preset sweeps, and BER against PCI-SIG repeater requirements
Multi-Sheet Schematic Hierarchy (HHHL Carrier)
The eight-sheet carrier schematic matches the structure project 39 uses: a root .kicad_sch holding only sheet references with sheets in a sibling directory. Same file version (20260306), same generator string, same title-block shape.
library/AUTOPHI_BGA900_pinmap.csv Per-ball bank, signal, voltage domain, direction assignments
Library tables inside the bundle are rewritten to use ${KIPRJMOD}/../library/ so the project resolves on any machine. Sheet references are verified to resolve inside the bundle before packaging.
Python scripts (root) 27 Validation, generation, assignment, wiring, board manipulation, packaging, Magento import
Python scripts ( _tools/ ) 11 Freerouting automation, overnight pipeline, recovery, store description builder
Total Python lines 5,366 Across all 38 scripts
KiCad schematic sheets 49 HHHL carrier (8), peripherals TI (10), peripherals AutoPhi (10), wired units (8), board back-annotation (9), root schematics (4)
KiCad PCB files 7 HHHL carrier board, loose-109 board, TIDA-00423 conversion, history snapshots
DRC report 1 10 violations (2 outline, 2 library warnings, 6 silkscreen), 0 unconnected, 0 footprint errors
This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
© 2026 Christopher Gabriel Brown
Photo
Footnotes
- Product number 8524.
- Family: autophi pcie cards.
- Purchase: When you buy, you buy the use of that blueprint only.