45-all-autophi-boards
Asset valuation: $5,600,000,000. Components: U7, U11 (ADS1115 ADCs) + U13 (24LC256 EEPROM) + U18 (BQ25798 charger) Strategy: All four sit on the shared I2C bus (SMCLK/SMDAT). They don't need dedicated BGA pins for the bus itself — only for interrupts and address
Think of a chip the way you think of a good engine: it does nothing until somebody builds the car around it. This package is the car. It is the complete collection of AutoPhi PCIe 5.0 accelerator board designs, 518 source files from three sub-projects and one tooling directory. At the center of every board sits the AutoPhi V19 Pinnacle IC in a custom BGA package, wired through four Texas Instruments PCIe retimers to a standard x16 edge connector on a PCI-SIG half-height, half-length card. Thirty-four variants share one core layout and differ only in the bracket connector at the edge, so one design serves data-center, telecom, automotive, industrial, aerospace, medical, consumer, RF and debug work.
Underneath is the part buyers never see: two proprietary BGA package definitions, 256-ball and 1,536-ball, every pin assigned, plus the canonical KiCad library that every downstream board consumes as its single source of truth. Beside it is a pipeline of 33 Python scripts that forks the TI TIDA-00423 reference into 34 routed variants with automated placement, maze routing, design-rule checks, SVG rendering and catalog export. The stackup is ten-layer Megtron 6 with ENIG finish.
This is for datacenter operators and engineering buyers who want a board family, not a board. The BGA library release is frozen at version one and the pipeline is operational. A buyer walks away with the library, the schematics, the pipeline and all 34 variants; the patent filings and the inventor's name stay with Christopher Gabriel Brown.
Description
Patents: USPTO 18/370,908 | 19/403,339 | 3561/2876 | 1026 | 1096–1098 | 1105 | 3559. Patent pending; all rights to seek additional patent protection are expressly reserved by the inventor.
Status: Research & Development — BGA library release v1 frozen; 34-board pipeline operational; schematic and routing automation complete.
Overview
The 45-all-autophi-boards package is the unified deliverable containing every AutoPhi PCIe 5.0 accelerator board design, spanning three coordinated sub-projects and one cross-project tooling directory. It consolidates 518 source files covering two proprietary BGA package definitions (256-ball and 1,536-ball), 34 I/O bracket board variants , a fully automated fork-place-route-verify-export pipeline derived from the Texas Instruments TIDA-00423 PCIe Gen 3 reference design, and the canonical BGA component library that all downstream board projects consume as their single source of truth.
The core AutoPhi V19 Pinnacle IC sits in a custom BGA package (10 mm flat, 32 mm width, sub-100 W) and connects through four TI DS80PCI810 PCIe retimers to a standard PCIe x16 edge connector on a PCI-SIG-compliant half-height half-length (HHHL) card outline. All 34 board variants share the same core PCB layout—identical IC, retimer, DDR3, and passive placement—and differ only in the I/O bracket connector at J2/J3, enabling one design to serve data-center, telecom, automotive, industrial, aerospace, medical, consumer, RF, and debug applications.
39-autophi-pcie5-256 39-autophi-pcie5-256/ Active schematic tree for BGA-256 and BGA-1536 variants of the QSFP28 optical board; hierarchical KiCad schematics with 16 generator scripts, FreeRouting integration, and full PCIe + DDR3 wiring 117 files
40-autophi-bga256 40-autophi-bga256/ Canonical source-of-truth library for AutoPhi BGA component definitions: footprints, symbols, pinmaps, governance docs, and Magento catalog generation 188 files
44-autophi-pcie5-1536 44-autophi-pcie5-1536/ Blueprint pipeline (33 Python scripts, ~14,000 lines) that forks the TI TIDA-00423 reference into 34 routed product variants with automated placement, A* maze routing, DRC, SVG rendering, and Magento CSV export 170 files
_tools _tools/ Cross-project FreeRouting and rewiring utilities for both BGA-256 and BGA-1536 board variants 4 files
Pin domain layout per row Cols 1–4: MGMT, Cols 5–6: POWER, Cols 7–8: GND, Cols 9–14: HSIO, Cols 15–16: GND
Motivation V19 Pinnacle class; supports full 64-bit DDR3 (4 chips x 16-bit), additional I/O, expanded power/ground planes
BGA interchange window 95.0 mm maximum
Surface finish ENIG (Electroless Nickel Immersion Gold) — required for BGA pads at 1.0 mm pitch
Target fabricator JLCPCB (primary); Advanced Circuits (alternate / prototyping)
Board outline TI TIDA-00423 (PCI-SIG HHHL) with flattened retention tab; main body X: −14.92 to 152.72 mm, Y: −51.44 to −3.4 mm
Power policy 75 W max board-level external input (hybrid power model: internal battery + external input)
U1 AutoPhi Quantum IC (BGA-256 or BGA-1536) BGA 22x22 mm / 95x90 mm Main SoC / accelerator — only non-vendor-catalog silicon Center (68.9, −29.5) mm, front
U2–U5 TI DS160PR810 PCIe retimers QFN-64, 8x8 mm PCIe Gen3 retimer/redriver (4 lanes each, x16 total) Symmetric around U1, front
U6–U7 TI LP3878 LDO regulators NGT package 3.3 V / 1.8 V power regulation (113.9, −39.5 / −29.5), front
U20 Lattice iCE40UP5K FPGA QFN-48, 7x7 mm Auxiliary compute / configuration (113.9, −16.5), front
U21–U24 Telemetry + clock ICs Various SMD Si5351A clock synthesizer, temperature sensors, voltage monitors Back top row
U25–U28 Optical + thermal controllers Various SMD QSFP28 control, TEC driver, LED management Front/back per variant
U45–U52 TI TPD4E004 ESD protection arrays DRY package 8-channel ESD on sideband/control lines Back mid row
U63–U66 DDR3 SDRAM (x4 geometry) FBGA-96, 11x15 mm 64-bit DDR3 memory bank (4 chips x 16-bit = 64-bit bus) Reflow, per DDR3 fly-by topology
U70 Boot EEPROM SOIC-8 Configuration and address storage Back side
J1 PCIe x16 edge connector 164-pad gold finger Host PCIe interface (PCI-SIG CEM compliant) (72, 6.87), bottom edge
J2, J3 I/O bracket connectors (variant-specific) Per variant (34 types) External I/O interface — defines the board variant Left short edge, flush mount
J21 Battery connector JST / header Internal battery interface (hybrid power model) Back side
TEC1, TEC2 Thermoelectric cooler modules Custom Active cooling for BGA and retimers Front mid row, post-reflow manual
LED1, D1–D4 Status LEDs 0603 / 0402 Power-good indicators, link status D1–D4 at (143, −40 to −25)
SW1–SW8 DS80PCI810 strap switches SMD tactile Retimer configuration straps Back mid row
RT1–RT8 NTC thermistors 0402 Temperature monitoring at inter-chip gaps Between U1 and retimers
RT9–RT34 49.9 ohm 0402 terminators 0402 Signal termination under BGA (back side empty zone) Back side under U1
TP1–TP6 Test points Through-hole Debug access Left corridor between J2/J3
MH1–MH6 M3 mounting holes 3.0 mm drill, 3 mm keepout zone Mechanical mounting (connected to GND net) Around U1 and board corners
C1–C331 Decoupling capacitors 0201–0805 Bypass/decoupling: 128 rings around retimers (32 each), 20 around U1, 8 bulk around LDOs, 128 PCIe AC coupling caps, plus power filter caps Distributed
R1–R34+ Resistors 0402 Pull-ups (I2C 4.7k, JTAG 4.7k), voltage dividers (VREF), ZQ cal (240 ohm), termination (39 ohm), feedback Distributed
FB1–FB10 Ferrite beads 0402–0603 Power rail filtering Near power ICs
CE1–CE4, CS1–CS4 Bulk + supercapacitors Various Energy storage and power smoothing Distributed
Total BOM: ~352 unique component references per board; ~2,390 total pads; ~323 nets; ~232 signal nets routed per variant.
+12V 12.0 V PCIe edge connector (J1 pins A2, A3, B1–B3) Main input, converted to lower rails
TX BGA-side U1 BGA TX (HSIO pair 0–15) C_AC_TX_BGA (0.1 uF 0402 X5R 16V) Retimer INB 2 (P+N)
RX BGA-side Retimer OUTB C_AC_RX_BGA (0.1 uF 0402 X5R 16V) U1 BGA RX (HSIO pair 16–31) 2 (P+N)
Total AC coupling capacitors: 8 per lane x 16 lanes = 128 caps , all 0.1 uF 0402 X5R 16V.
Retimer decoupling: 8 caps per retimer x 4 retimers = 32 caps (10 uF bulk + 1 uF mid + 0.1 uF fine per VIN pin; 0.1 uF per VDD pin).
Fly-by termination Not required (single load, internal ODT) 23 x 39 ohm to VTT_DDR (A0–A14, BA0–2, RAS, CAS, WE, ODT, CKE, CS, CK P/N)
Total DDR-related components ~194 ~221
The pipeline transforms the TI TIDA-00423 reference design into 34 production-ready board variants in five automated stages, driven by 33 Python scripts totaling approximately 14,000 lines of code.
0 — Schematic generate_schematic.py, skidl_autophi_v3.py Template + pinmap .kicad_sch + KiCad netlist (16,624 lines) + XML + BOM CSV (352 rows)
1 — Fork fork_ti_board.py (2,087 lines), ti_net_mapping.py, generate_pcb.py TIDA-00423 reference .kicad_pcb 34 x .kicad_pcb files (one per variant)
2 — Place place_passives_clustered.py, resolve_collisions.py, snap_passives.py Forked .kicad_pcb Placed boards (caps wrapped around ICs, zero courtyard collisions)
3 — Route auto_route.py (1,749 lines — A* maze router with diff-pair, row-to-layer, DRC halos, global+detailed routing) Placed .kicad_pcb Routed boards + route cache (shared core JSON)
4 — Verify drc_check.py (349 lines) Routed .kicad_pcb DRC violation report (target: 0 collisions on all 34 boards)
5 — Export render_board_svg.py (657 lines), build_magento_34_boards.py, domino_pipeline.py Verified .kicad_pcb SVG previews, Magento CSV (34 product rows), product packaging
One-command build: python blueprints/build_all.py — runs fork, SVG render, collision check, Magento CSV, preview HTML. Output: OK: 34 boards, 0 collisions .
auto_route.py 1,749 A* maze router: grid routing, differential-pair coupling, row-to-layer BGA fan-out, DRC halos, global coarse-tile BFS + detailed corridor routing, backoff retry
fork_ti_board.py 2,087 Fork TI TIDA-00423 into 34 .kicad_pcb variants with outline flattening, fixed-part placement, zone packing, and side-split allocation
render_board_svg.py 657 Direct SVG renderer: front (gold pads) / back (cyan pads) split, ratsnest, layer colors, bbox outlines for collision visibility
drc_check.py 349 Post-route clearance verification (trace/via/pad), integrates with kicad-cli pcb drc
skidl_autophi_v3.py ~500 SKiDL-based schematic generation from live PCB inventory (1,723 connections)
extract_board_netlist.py ~200 PCB sexpr parser to JSON inventory (352 parts, 323 nets, 2,390 pads)
make_schematic_viewer.py ~200 HTML schematic viewer (14 functional sections, color-coded by net class)
01 — Central Processor U1 AutoPhi BGA (256/1536), PCIe lane mapping (HSIO pairs 0–31), MGMT GPIO assignment gen_mcu.py (for MSP430 companion)
02 — PCIe Retimers U3/U6/U17/U21 DS80PCI810 (4 retimers x 4 lanes), CML pin mapping, I2C address straps gen_retimer_decoupling.py
03 — PCIe x16 Edge J5/J1 164-pad edge connector, 16 TX + 16 RX differential pairs, power pins, sideband —
04 — Power Tree LP3878 LDOs, TPS62080 1.5V buck, TPS51200 VTT regulator, power sequencing gen_power_tree_main.py, gen_power_supplements.py, gen_power_filter.py
05 — DDR3 Memory U4/U9/U19/U31 DRAM, 64-bit bus, DQS strobes, address/command, ZQ calibration gen_ddr3_chip.py, gen_ddr3_aux.py, gen_ddr3_flyby.py
06 — Telemetry + Clock Si5351A clock synthesizer (REFCLK_P/N), temperature sensors, voltage monitors gen_clock_si5351.py, gen_telemetry.py
07 — ESD Protection 8x TPD4E004 arrays on sideband/control lines gen_esd.py
08 — QSFP28 Optical QSFP28 cage, Amphenol U95T151100A connector, thermal management gen_qsfp_cage.py
09 — Boot + Config EEPROM, SPI flash, USB-C charger gen_boot_eeprom.py, gen_charger_usbc.py
10 — Heatsink + Mounting MH1–MH6 mounting holes, heatsink attachment gen_heatsink_mh.py
12 — PCIe Supplement 128 AC coupling caps + 32 retimer decoupling caps + I2C/JTAG pull-ups + reset circuit gen_ac_coupling.py
ZQSFP_1x1_PLACEHOLDER_AMPH_UE76A20X010T.kicad_mod QSFP cage placeholder (Amphenol UE76 variant)
generate_bga_footprint_grid.py Parametric BGA footprint generator with profile support (v19_default, zetta_ref, smd15_ref)
generate_bga_pinmap_template.py Generate pinmap CSV template from footprint pad definitions
promote_provisional_signals.py Promote TBD placeholder names to stable canonical signal names
finalize_power_rails.py Finalize voltage-domain placeholders across both BGA-256 and BGA-1536 pinmaps
validate_bga_library.py Cross-validate pinmap/symbol/footprint alignment for all BGA entries
build_magento_series_draft.py Build consolidated Magento catalog CSV (34 board rows + BGA library rows)
profile_switch.py Dimension profile management (v19_default, zetta_ref, smd15_ref)
rebuild_provisional_seed.ps1 One-command reproducible full rebuild (normalize + seed + symbol + report + checkpoint)
gen_ac_coupling.py Generate 128 PCIe AC coupling capacitor schematic entries (4 sides x 16 lanes x 2 diff)
gen_clock_si5351.py Generate Si5351A clock synthesizer schematic (REFCLK, CLK_100M, CLK_10M)
gen_power_supplements.py Generate supplementary power circuits (1.5V buck, VTT, battery management)
gen_retimer_decoupling.py Generate per-retimer decoupling capacitor network (8 caps x 4 retimers = 32 caps)
gen_telemetry.py Generate telemetry subsystem schematic (voltage/current/temperature monitors)
AutoPhi V19 Pinnacle (canonical) 10 mm flat 32 mm 384–1,536 Sub-100 W (~58.7 W narrative) Board-series default
AutoPhi Single Zetta (special ref) 5 mm stack 36 x 36 mm die N/A (500 layers) ~140 W Reference only
Semiconductor Method Discovery 15 (special ref) 10 mm chip 32 mm square N/A (32 layers) 235 W Reference only
Schematic Viewer Functional Sections
The auto-generated HTML schematic viewer organizes the design into 18 color-coded sections:
KiCad PCB layouts (.kicad_pcb) 34+ One per board variant (BGA-256 and BGA-1536 versions), plus reference designs
KiCad schematics (.kicad_sch) Multiple Hierarchical schematic sheets (12+ sheets per variant), parent and sub-sheet files
KiCad project files (.kicad_pro, .kicad_prl) Multiple Project settings, layer preferences, local settings
Custom footprints (.kicad_mod) 27 All 27 footprints in AutoPhi.pretty library (IC, connector, passive packages)
Python automation scripts ~80 Pipeline scripts (33 in blueprints), BGA library scripts (16), schematic generators (16), utility/analysis scripts
Specctra DSN/SES files Multiple FreeRouting design and session files for both BGA variants
Netlist files (.net, .json) Multiple KiCad netlists (16,624 lines), TI reference netlists (TIDA-00423), board inventory JSON
BOM CSVs Multiple 352-row BOM per variant, Magento import CSVs (34 product rows), manifest CSVs
SVG board previews 34 Rendered front/back PCB views per variant (gold front, cyan back)
HTML viewers Multiple 34-board grid preview, schematic viewer (14 sections), interactive placement editor, unconnected-triage viewer
DRC/ERC reports Multiple Design rule check and electrical rule check reports (.rpt, .json, .txt)
Routing logs Multiple Auto-router session logs, FreeRouting logs, route cache metrics
Documentation (.md) 45 Technical specifications, routing techniques, manufacturing specs, handoff guides, process docs
Governance files 5 LICENSE, MANIFEST.json, CITATION.cff, CHANGELOG.md, CONTACT_INFO.txt
PowerShell/Bash build scripts Multiple rebuild_provisional_seed.ps1, batch routing scripts, export scripts
Delivery: Shipped on a single Blu-ray disc. All files are AES-256 encrypted. Dispatched by tracked post.
© 2026 Christopher Gabriel Brown. All rights reserved. Patent pending. No intellectual property is conveyed with the deliverable. The underlying copyrighted material and the method-claim patent strategy remain the property of the inventor.
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Footnotes
- Product number 8494.
- Family: autophi pcie cards.
- Purchase: When you buy, you buy the use of that blueprint only.