59-verifyphi

Valuation

Generous asset valuation: $10,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

VerifyPhi

VerifyPhi

Project 59 · cri-one.com portfolio · Standalone SKU · $25M

Positioning: WritePhi is the writer. VerifyPhi is what refuses to feed it an unverified design.

VerifyPhi is the design-verification pipeline that gates the writable-payload emission for the WRITEPHI-WRITER (Project 57). It is the switch-level simulator, the testbench framework, the loop driver, the self-authenticating burn-payload architecture, and the pre-dice wafer probe geometry — packaged, licensed, and shipped as a standalone deliverable.

Patent-pending. Filed as USPTO non-provisional utility application 19/731,098 on 2026-07-05 (Confirmation 5973, Patent Center 78285110). 15 claims across four independent claim clusters; 6 figures. Title of record: VERIFICATION-GATED COMPILE-AND-OPTICAL-WRITE PIPELINE FOR PHOTOLITHOGRAPHIC CIRCUIT SUBSTRATES.

Contents (at a glance)

• SPEC.md — technical specification
• PRODUCT_BRIEF.md — business summary + pricing + terms
• PLAYBOOK.md — buyer-side bring-up sequence
• LICENSE.md — deliverable license (IP-retained, USA-only, USD, email + postal mail only)
• STATUS.md — honest report of what is designed, spec'd, and delivered vs. what is buyer-scope
• STORE_LISTING.md — store-page copy brief
• verifyphi_store_description.html — deployable store description
• HANDOFF.md — session boundary + pickup queue
• MANIFEST.json — machine-readable inventory
• CONTACT_INFO.txt — inventor + delivery contact
• bundle.py — reproducible bundler
• patent/ — copy of filed USPTO 19/731,098 disclosure + figures + filing options
• docs/ — cross-references to Project 57 subsystems
• figures/ — the 6 filed patent figures

Integration with siblings

• Project 57 — WritePhi. VerifyPhi runs the SDK + simulator + loop driver that live in ../57-chip-write/sdk/python/writephi/, ../57-chip-write/tools/loop.py, and ../57-chip-write/tools/build_burn_payload.py. Arms-length: WritePhi ships the writer hardware and blank; VerifyPhi ships the software that decides whether the writer is allowed to write.
• Project 58 — WritePhi Devices. VerifyPhi's compile-gate can be pointed at WPD-CSD / WPD-ACCEL design files the same way it points at Project 57's dies.
• Project 21 — Day-One Fabrication. VerifyPhi's flow works against DOF's design-source directory too. Anywhere there is a design and a testbench, VerifyPhi can be dropped in.

Contact

Christopher Gabriel Brown · cri-one.com/store · crioneaka@outlook.com

VerifyPhi — Session Handoff

VerifyPhi — Session Handoff

Project 59 · 2026-07-05 rev 1.0

Shipped in the initial build (2026-07-05)

• README.md — project overview + integration with siblings
• SPEC.md — full technical specification (5 subsystems + 3 grades + compatibility)
• PRODUCT_BRIEF.md — business summary + pricing ($25M) + terms
• PLAYBOOK.md — buyer bring-up sequence (Day 0 through Month 3)
• LICENSE.md — deliverable license (IP retained, USA-only, USD, buyer-bankruptcy shield)
• STATUS.md — honest engineering status per subsystem
• STORE_LISTING.md — store copy brief
• verifyphi_store_description.html — deployable Magento store description
• HANDOFF.md — this file
• MANIFEST.json — machine-readable inventory
• CONTACT_INFO.txt — inventor contact
• bundle.py — reproducible bundler (matches Project 57 pattern)
• patent/ — full copy of USPTO 19/731,098 disclosure + DOCX + figures + filing options
• figures/ — the 6 filed patent figures (FIG1-FIG6.svg)
• docs/ — cross-reference to Project 57 subsystems

USPTO status

FILED 2026-07-05 3:04:00 PM ET as non-provisional utility application 19/731,098 (Confirmation 5973, Patent Center 78285110). 15 claims + 6 figures. Title: VERIFICATION-GATED COMPILE-AND-OPTICAL-WRITE PIPELINE FOR PHOTOLITHOGRAPHIC CIRCUIT SUBSTRATES.

Store push checklist (buyer of Chris — for the next session)

• [ ] Assign Magento entity ID + final SKU VERIFYPHI-STANDALONE.
• [ ] Category assignment: Semiconductor & Fabrication (same parent as WritePhi).
• [ ] Push verifyphi_store_description.html via the store description pipeline [[store-description-pipeline]].
• [ ] Add row to total-all-in-one.html — bump project count 58 → 59.
• [ ] Update humdinger [[all-in-one-bundle]] scope to include VerifyPhi (bundle price unchanged, VerifyPhi folds in as capability).
• [ ] Add row to manager\patent_tracker per [[patent-tracker-import]].

Watch dates

• 2026-07-19 — first check of Patent Center 78285110 for Notice to File Missing Parts.
• 2026-08-05 — second check. Per [[portfolio-abandonment-status-2026-07-04]], 16 prior filings went abandoned when the missing-parts window closed. This is the exception to the no-unfunded-spends rule ([[feedback-money-constrained-no-unfunded-spends]]) — pay the fee if issued.

Pickup queue (next-session extensions)

• Build bundle.py output (verifyphi.crione.zip) + local backup at Chris\System\shipped-downloads\.
• Wire VerifyPhi bundle into the shared CD-GDSII generator pattern [[cd-gdsii-generator-pattern]] for auto-delivery on checkout.
• Testbench for WPIC-UART-01 (300 FETs) — brings a real 10× scale-up verification to the loop table.
• 4-bit and 8-bit counter extensions (COUNTER-02, COUNTER-03) built on the verified master-slave D-flop.
• Timing model extension to VERIFYPHI-SIM (propagation delay, setup/hold).
• KiCad .kicad_sch exporter from .wpprog byte streams.

Non-goals for this project (deliberately excluded)

• Silicon fabrication services. Buyer scope.
• Substrate manufacturing. Buyer scope (WRITEPHI-BLANK is bought under Project 57).
• FCC/UL/CE certification. Buyer scope.
• Enforcement details. Per [[enforcement-roadmap-private]] — leverage held privately, buyer-facing packet does not name accused parties or list claim-chart filenames.

VerifyPhi — Buyer Playbook

VerifyPhi — Buyer Playbook

Project 59 · Bring-up sequence for the acquiring engineering team

Day 0 — Receive delivery

1. Confirm receipt of the VerifyPhi bundle (.zip + .sha256) by email or physical disc.

2. Verify SHA-256 of the bundle matches the sign-off in the delivery message.

3. If a physical BDXL disc was included, run python verify.py on the disc — expected: 48 ok · 0 mismatch · 0 missing.

Day 1 — First local run

1. Unzip the bundle to a working directory. Recommended: <your-org>/verifyphi/.

2. Confirm Python 3.10 + is installed.

3. cd sdk/python && python -c "import writephi; print(writephi.__version__)" — expect 0.1.0.

4. Run the seven reference IC designs:

cd tools && python loop.py

Expected output: 7 of 7 clean, with WPIC-INVERT-02 at 20/20 assertions and WPIC-COUNTER-01 at 12/12.

Day 2 — First Buyer-authored design

1. Copy a reference IC directory (e.g., ic_designs/WPIC_INVERT_02/) to a new name (e.g., ic_designs/BUYER_HELLOWORLD/).

2. Edit design.py to describe your circuit using VirtualTransistor, Interconnect, and Pad primitives.

3. Author run_testbench() with the truth-table assertions your design must satisfy.

4. python design.py — VerifyPhi will refuse to emit .wpprog if any assertion fails.

5. On pass, examine the rendered design.svg die floorplan.

Week 1 — Integrate with your existing EDA flow

VerifyPhi is netlist-format-neutral. Choose one:

• A. Stay in Python. Use VerifyPhi as your primary sim + gate for M-grade and small H-grade designs (up to ~10,000 FETs). Fast iteration, no external dependencies.
• B. Port to Verilator / Icarus. Extract the netlist from .wpprog (documented in ../57-chip-write/sdk/python/writephi/compile.py) and emit Verilog. Use VerifyPhi as the reference model that industry EDA tools regress against.
• C. Route to conventional foundry. VerifyPhi's .wpprog byte stream carries all the information needed to synthesize the equivalent Verilog / VHDL for a conventional tape-out. Skip the optical write channel entirely if that's your target.

Week 2 — Wafer probe pattern integration

If you plan to fabricate the WRITEPHI-BLANK substrate:

1. Study ../57-chip-write/tools/render_wafer.py. This is the reference implementation of Claim 9 of the patent.

2. Integrate the wafer-floorplan generator into your mask-generation flow. The generator produces SVG at 120 mm scale; convert to your mask-writer's preferred format.

3. Fabricate a wafer-probe card that mates to the outer test ring at the specified pad-link geometry. This is buyer scope; VerifyPhi provides the geometry spec, not the probe card.

Week 4 — Self-authenticating shipment

For every batch of WRITEPHI-BLANK product you ship:

1. Run python tools/build_burn_payload.py against your design library.

2. The payload includes a fresh SHA-256 manifest and verify.py.

3. Physical write via BDXL drive or disc publisher (Primera Bravo or equivalent).

4. Every recipient of your product can run verify.py on receipt to confirm the shipment has not been corrupted or tampered with in transit.

Month 3 — Optional extensions (buyer scope)

• Timing model. Add propagation-delay-per-gate estimates to simulate.py. Enables setup/hold checks.
• Multi-level backplane. Route dies on the wafer to a common backplane geometry per catalog entries 1184-1189 (the "software written multiple level chip assembly cubit grid" priority anchor).
• Custom testbench templates. Extend TestBench with domain-specific input drivers (SPI, I²C, JTAG).
• KiCad export. Translate .wpprog netlists to KiCad .kicad_sch for board-level integration.

Escalation

• Bugs in VerifyPhi itself. Email crioneaka@outlook.com. Include the failing testbench output and the .wpprog byte stream.
• Bugs in your own designs that VerifyPhi catches. Congratulations — you just used VerifyPhi correctly.
• Bugs that VerifyPhi misses. Email with reproduction. These are extension opportunities for the simulator model.
• Legal / IP questions. Email — Chris handles pro se; expect ~week turnaround.

VerifyPhi — Product Brief

VerifyPhi — Product Brief

Project 59 · Standalone SKU · $25M · Included in All-In-One bundle

What is being sold

The VerifyPhi engineering package — the design-verification pipeline that decides whether a chip design is allowed to reach any writable optical circuit substrate (WRITEPHI-BLANK, Project 57).

Specifically:

1. Full source for VERIFYPHI-SIM (switch-level CMOS simulator), VERIFYPHI-GATE (compile-time verification gate), VERIFYPHI-MEDIUM (self-authenticating writable medium architecture), VERIFYPHI-PROBE (pre-dice wafer probe pattern geometry), and VERIFYPHI-LOOP (iteration driver). Stdlib-only Python 3.10+.

2. Reference design library — five simulator-verified integrated circuit designs (WPIC-INVERT-01, WPIC-INVERT-02, WPIC-COUNTER-01, WPIC-UART-01, WPIC-PWM-01, WPIC-SPI-DAC-01, WPIC-AES-CORE), each shipped with source design.py, compiled .wpprog, rendered die floorplan SVG, and per-die specification.

3. The as-filed USPTO patent — a full copy of the 2026-07-05 filing:

• Application 19/731,098
• Confirmation 5973
• Patent Center 78285110
• 15 claims + 6 figures
• Full DISCLOSURE.md, USPTO-formatted DOCX, and SHA-256 timestamp anchor

4. Wafer floorplan generator — render_wafer.py and build_label_pdf.py produce print-ready 120 mm × 120 mm PDF labels for Primera Bravo / PTPublisher publishing.

5. Buyer-side bring-up playbook — PLAYBOOK.md.

What is not being sold

• The underlying inventions themselves. All IP is retained by the inventor per [[no-ip-license-sales]] — the buyer receives deliverables sufficient to bring VerifyPhi up on their premises for their internal engineering use, not the right to license the patent to third parties, not the right to sell VerifyPhi-branded products, not any transfer of the 19/731,098 application ownership.
• The WRITEPHI-WRITER hardware. That is sold as WritePhi (Project 57).
• The WRITEPHI-BLANK substrate. Also Project 57.
• Silicon fab services. Buyer scope.

Pricing

$25,000,000 (twenty-five million USD).

Priced as a software-only SKU: full source of the verification pipeline plus the as-filed USPTO 19/731,098 disclosure plus the seven simulator-verified reference IC designs plus the wafer-probe geometry. Separate from WritePhi (Project 57) and WritePhi Devices (Project 58), which carry hardware/blank/substrate costs that VerifyPhi does not; VerifyPhi is the compile-time verification gate that decides whether those hardware paths get anything to write.

Also included in the All-In-One bundle ([[all-in-one-bundle]]) at no additional charge — bundle price is retained at the current $20T level with VerifyPhi's addition folded in as capability, not price.

Terms

• USD only, delivered by wire transfer or escrow. Chris signs a term sheet ([[pay-in-4-and-term-sheets]] — Term Sheet tier for $10k+ deals).
• USA-only sale. Per [[store-copy-rules]] and [[human-id-geoblock]].
• Email + postal mail delivery. No online license portals, no revocable licenses.
• Bankruptcy notation — if BUYER files for bankruptcy protection, the license terms of this deliverable are set out in LICENSE.md § "Buyer bankruptcy shield." Chris has NOT filed for bankruptcy per [[chris-not-bankrupt]].

Positioning

WritePhi is the writer. VerifyPhi is what refuses to feed it an unverified design.

Related SKUs

• Project 57 — WritePhi (writer + blank + design library + server bed)
• Project 58 — WritePhi Devices (Windows CSD + Accelerator PCIe cards)
• Project 21 — Day-One Fabrication (commercial foundry counterpart to WritePhi)

VerifyPhi is buyable independently of any of the above; it operates on any design source that follows the WritePhi SDK conventions.

VerifyPhi — Specification

VerifyPhi — Specification

Project 59 · Revision 1.0 · 2026-07-05

1. Overview

VerifyPhi is a design-verification pipeline for optically-written photolithographic circuit-processor substrates (WRITEPHI-BLANK, Project 57). It comprises four subsystems, each individually claimed in USPTO application 19/731,098 (filed 2026-07-05):

• VERIFYPHI-SIM — switch-level CMOS simulator (Claims 2-3, FIG. 5)
• VERIFYPHI-GATE — compile-time verification gate that refuses to emit .wpprog if any testbench assertion fails (Claims 1, 4, 5, FIG. 1, FIG. 6)
• VERIFYPHI-MEDIUM — self-authenticating writable optical medium architecture (Claims 6-8, FIG. 2)
• VERIFYPHI-PROBE — pre-dice wafer probe pattern geometry with pad-link routing to a common outer test ring (Claims 9-12, FIG. 3)
• VERIFYPHI-LOOP — automated design → simulate → virtual burn → study → real burn iteration driver (Claims 13-15, FIG. 4)

2. VERIFYPHI-SIM — Switch-Level Simulator

Domain: {LOW, HIGH, FLOATING, CONFLICT}. Each VirtualTransistor is modeled as a gate-controlled switch. Union-find over conducting devices per iteration; group resolution reads active drivers first, then falls back to sequential latch memory. Fixed-point iteration to convergence.

• Reference source: ../57-chip-write/sdk/python/writephi/simulate.py
• Latch-memory subsystem: Simulator.latch() / .unlatch() freezes named nets as sequential storage — engaged only when no active driver contests the group.
• Convergence: max_iters=64 default; cross-coupled NAND SR latches converge in ≤6 iterations; asynchronous reset breaks bootstrap ambiguity.

Delivered form: stdlib-only Python 3.10+ module. No pip dependencies. Runnable on any Windows / macOS / Linux host with Python installed.

3. VERIFYPHI-GATE — Compile-Time Verification Gate

python design.py invokes, in order:

1. build_design() → Design object with VirtualTransistors, Interconnects, Pads, Nets.

2. run_testbench() → TestBench with assertions.

3. Simulator iterates the netlist under each input vector; assertions record pass/fail.

4. If any assertion failed → sys.exit(1) without writing .wpprog. The physical write channel cannot receive the design.

5. Only on 100 % pass does design.compile() serialize the netlist to the .wpprog byte stream (header + calibration bytecode + write-sequence bytecode + self-verify reference + footer, SHA-256 sign-off).

Reference source: ../57-chip-write/sdk/python/writephi/compile.py, ../57-chip-write/sdk/python/writephi/testbench.py, ../57-chip-write/ic_designs/*/design.py.

Assurance: on 2026-07-05, five reference IC designs (WPIC-INVERT-01, WPIC-INVERT-02, WPIC-COUNTER-01, WPIC-UART-01, WPIC-PWM-01) run through VerifyPhi. INVERT-02 passes 20/20 assertions; COUNTER-01 passes 12/12 assertions after two chip-design bugs were caught in-sim (dangling FET sources on the INVERT-01 stub; wrong ripple clock polarity on the counter).

4. VERIFYPHI-MEDIUM — Self-Authenticating Optical Medium

The writable optical medium carries:

• The per-die verified design payloads (.wpprog),
• A copy of the design SDK (for buyer-side re-compilation),
• Documentation,
• MANIFEST.txt — SHA-256 of every other file,
• verify.py — executable that re-hashes every file on the medium after insertion and reports mismatch.

Any write-channel defect (bit flip, sector rewrite) produces a hash mismatch. Post-write medium integrity is verified independently of the writing device.

Reference source: ../57-chip-write/tools/build_burn_payload.py, ../57-chip-write/BURN_ME/verify.py, ../57-chip-write/BURN_ME/MANIFEST.txt.

5. VERIFYPHI-PROBE — Pre-Dice Wafer Probe Pattern

Geometry for the WRITEPHI-BLANK wafer floorplan:

• A plurality of dies arranged radially within the writable annular region (BDXL 120 mm outer / 33 mm clamp).
• Radial scribe cut lines between adjacent dies (per WRITEPHI-DICER cut boundaries).
• Per die: two IC tabs of asymmetric widths (pin-1 large, opposite small — fool-proof orientation); three alignment fiducials of distinct geometry (pin-1 dot, center square, diagonal cross); four pad-link traces from signal pads outward.
• A common outer test ring concentric with the substrate axis, radially outside every die.
• Pad-link traces terminate at ring bond points, permitting a ring-shaped wafer-probe card to electrically exercise every die simultaneously prior to dicing. Failing dies are marked and rejected before dicing separates them.

Reference source: ../57-chip-write/tools/render_wafer.py, ../57-chip-write/BURN_ME/wafer.svg, ../57-chip-write/BURN_ME/wafer_label.pdf.

6. VERIFYPHI-LOOP — Iteration Driver

One command runs:

1. COMPUTE — build_design() + run_testbench() per IC.

2. VIRTUAL BURN — emit .wpprog (gated) + render die SVG.

3. STUDY — record assertion report; write per-IC summary.

4. PAYLOAD REFRESH — if every listed IC is green, rebuild BURN_ME/.

5. REAL BURN — hand-off to physical write channel (BDXL drive or Primera Bravo publisher).

Reference source: ../57-chip-write/tools/loop.py.

7. Grade coverage

VerifyPhi operates on any TargetGrade supported by the WritePhi SDK:

• M-grade (2 µm min feature, 64 signal contacts, 84 total contacts, 3 layers, BDXL 100 GB): reference implementation, all five 2026-07-05 verified ICs.
• H-grade (0.5 µm, 128 signal, 168 total, 4 layers, BDXL 128 GB): supported; grade-constraint checks emit ValueError on any design exceeding H limits.
• M_P (portable variant, 32 signal, 48 total, 2 layers, 60 mm mini-BD): supported.

Grade selection is a Design attribute (target_grade=TargetGrade.M). Simulator behavior does not change with grade — only compile-time constraint checks tighten.

8. Compatibility

• Python: 3.10 + (stdlib-only).
• Optical write channel: any BDXL drive or Primera Bravo disc publisher supporting BD-R XL blanks. Reference test hardware documented in ../57-chip-write/COMPATIBILITY.md.
• Design SDK: writephi Python package as of ../57-chip-write/sdk/python/writephi/__init__.py version 0.1.0.
• Design library: WPIC-* reference IC designs at ../57-chip-write/ic_designs/.
• PCIe carrier boards for post-write bring-up: WritePhi Devices (Project 58) V2 package + inset PCB + pinned socket.

9. Buyer scope (not delivered)

Per [[feedback-schematic-is-chris-ceiling]] — the inventor's deliverable ceiling is spec + drafted schematic + Python source. The following are the buyer's responsibility:

• Simulator port to production EDA tools (Verilator, Icarus Verilog, VCS).
• Wafer-probe card fabrication.
• Physical WRITEPHI-BLANK substrate manufacturing (buyer supplies photoresist stack — the on-hand BDXL blanks used for the 2026-07-05 physical demonstration burn are dye-stack, not circuit-stack).
• FCC / UL / CE / IEC 60825 laser-safety certification of any deployed WRITEPHI-WRITER.
• Silicon tape-out (if the buyer chooses to skip WRITEPHI-BLANK entirely and route VerifyPhi-verified designs to a conventional commercial foundry — VerifyPhi output is netlist-format-neutral and does not require the optical write channel; conventional-fab tape-out is a legitimate buyer path).

10. Legal

Filed USPTO non-provisional utility patent application 19/731,098 (Confirmation 5973, Patent Center 78285110) on 2026-07-05 3:04 PM ET.

Earlier priority anchors — Chris's Invent Depositions (ISBN 978-1-979767-89-7, 2017-11-24) and buyinvent.com catalog entries 730, 781, 784, 785, 837, 879, 881, 926, 927, 1160-1164, 1184-1189, 1446-1452, 1730-1733. See patent/DISCLOSURE.md § "Inventor's own printed publication prior art" for full mapping.

VerifyPhi — Status (honest report)

VerifyPhi — Status (honest report)

Project 59 · 2026-07-05 · Revision 1.0

Overall maturity: DELIVERED-AS-SOFTWARE

Not a prototype. Not a demo. Delivered software. The pipeline runs today; two chip-design bugs were caught by it in-session on 2026-07-05, both real, both fixed under the same iteration loop. Everything else in the SPEC is a design target for the buyer to extend.

Subsystem status

USPTO status

FILED as USPTO non-provisional utility application 19/731,098 on 2026-07-05 3:04:00 PM ET. Confirmation 5973, Patent Center 78285110. Title: VERIFICATION-GATED COMPILE-AND-OPTICAL-WRITE PIPELINE FOR PHOTOLITHOGRAPHIC CIRCUIT SUBSTRATES.

• 15 claims (4 independent + 11 dependent) filed pro se.
• 6 figures embedded in the DOCX submission.
• Priority chain: 2017-11-24 (Invent Depositions, ISBN 978-1-979767-89-7) + 2018-2019 buyinvent.com catalog entries + 2026-05-30 framework filing 19/693,405 + 2026-07-05 filing.

Watch date: 2026-07-19 and 2026-08-05 for USPTO Notice to File Missing Parts. Missing-parts fees, if issued, are the exception to the no-unfunded-spends rule per [[feedback-money-constrained-no-unfunded-spends]] — the application dies otherwise.

Physical demonstration

On 2026-07-05, a physical demonstration burn of the WritePhi payload (including a full copy of the VerifyPhi source, the reference IC library, the SPEC, and the patent DISCLOSURE) was prepared for BDXL / Primera Bravo publisher execution. The physical write channel proves that:

1. The .wpprog byte streams survive an optical write/read cycle intact (SHA verification).

2. A commercial BDXL drive is a viable physical carrier for VerifyPhi-verified WritePhi write programs.

3. The wafer floorplan renders as a printable label at native 120 mm disc geometry.

What the demonstration burn does not prove: functional silicon. The BDXL blanks used are dye-stack, not the WRITEPHI-BLANK photoresist stack. Real chip fab remains buyer scope per [[feedback-schematic-is-chris-ceiling]].

Buyer scope (not delivered)

Per Chris's ceiling — the following are the buyer's responsibility:

• Port VERIFYPHI-SIM to production EDA tools (Verilator, Icarus Verilog, VCS) for designs above ~100K transistors.
• Wafer-probe card fabrication for VERIFYPHI-PROBE.
• Physical WRITEPHI-BLANK substrate manufacture.
• FCC / UL / CE / IEC 60825 laser safety certification of any deployed WRITEPHI-WRITER.
• Silicon tape-out via any conventional foundry (buyer path, VerifyPhi output is netlist-format-neutral).

Pickup queue for next iteration

• Testbench for WPIC-UART-01 (300 FETs). Bring it from "compile-only" to "verified" in the loop table.
• Testbench for WPIC-PWM-01, WPIC-SPI-DAC-01, WPIC-AES-CORE.
• 4-bit and 8-bit counter extension (COUNTER-02, COUNTER-03) using the verified master-slave D-flop primitive.
• Timing model (propagation delay per gate, setup/hold checks) — extension to VERIFYPHI-SIM.
• KiCad export from .wpprog → schematic + PCB layout intent files (for buyers routing to conventional foundries).

VerifyPhi — Store Listing Brief

VerifyPhi — Store Listing Brief

For internal use — the deployable HTML is at verifyphi_store_description.html.

Title

VerifyPhi — Design Verification Pipeline for Optical Circuit Substrates

Short subtitle

WritePhi is the writer. VerifyPhi is what refuses to feed it an unverified design.

Category

Semiconductor & Fabrication (parent category — same as Project 57 WritePhi).

Price

$25,000,000 (twenty-five million USD).

SKU

Reserved: VERIFYPHI-STANDALONE. Chris to assign final Magento SKU + entity ID at store-push time.

Patent notation

Patent-pending. USPTO Application 19/731,098 (filed 2026-07-05).

Store copy uses "patent pending" language per [[store-copy-rules]] and cites the application number to distinguish from Chris's older provisional and abandoned filings (which are being ring-fenced separately per [[portfolio-abandonment-status-2026-07-04]]).

Bankruptcy notation

Standard buyer-bankruptcy shield per [[all-in-one-bundle]]:

> If Buyer files for bankruptcy protection at any point during or after acquisition, the license terms of this deliverable are structured to protect Seller's IP retention from any bankruptcy-court reassignment. Christopher Gabriel Brown has NOT filed for bankruptcy [[chris-not-bankrupt]].

Country + payment terms

USA-only, USD-only, email + postal mail only per [[store-copy-rules]] and [[human-id-geoblock]]. Under Founder Access Pass tier ([[lto-founder-access-pass]]) if that program is still live at the time of buyer engagement.

Delivery

Physical (BDXL disc via Primera Bravo publisher) + email delivery of the SDK bundle + counter-signed Term Sheet ([[pay-in-4-and-term-sheets]] — Term Sheet tier).

Key sales points

1. Filed, dated USPTO patent — 19/731,098, 2026-07-05, 15 claims, 6 figures.

2. Software runs today — 12/12 counter assertions + 20/20 gate assertions verified in-simulator on delivered reference dies.

3. Catches real bugs — the simulator caught two chip-design bugs in-session on the day of the filing (dangling FET sources, wrong ripple clock polarity). Documented in STUDY_REPORT.md.

4. Priority chain to 2017 — inventor's-own printed-publication anchor at Invent Depositions + entries 730, 926, 927, 1160-1164, 1446-1452 among others.

5. Stdlib-only Python 3.10+ — no pip dependencies. Runs on any Windows/macOS/Linux host with Python.

6. Self-authenticating shipment — every buyer disc contains its own hash manifest + verifier.

7. Wafer probe geometry included — pre-dice electrical test pattern for the WRITEPHI-BLANK, sized to real BDXL geometry.

Do-not-list

• No enforcement roadmap ([[enforcement-roadmap-private]]).
• No specific accused parties.
• No competitor claim charts.
• No specific $ valuations beyond the $25M price.

WritePhi — First Physical Burn (Instructions)

WritePhi — First Physical Burn (Instructions)

Project 57 · 2026-07-05

Chris has a BDXL drive + a few blank BDXL discs. This is the recipe to

put the WritePhi payload on one of them and prove the write channel

round-trips.

What you'll prove

Not: a functional silicon chip. (The blank stack on a commercial BDXL is

photoresist for dye burning, not the WritePhi photoresist-on-substrate

per BLANK_MEDIA_SPEC.md. Real chip fab

needs the buyer's substrate supply chain — [buyer scope per your

ceiling](../.claude/projects/../../../..).)

Yes:

1. Every WritePhi .wpprog byte stream survives a physical optical

write + read cycle intact — bits match hash.

2. A commercial BDXL drive is a viable physical carrier for WritePhi

write programs. Every IC we've compiled fits inside a single track.

3. You have a photograph of a burned disc that IS a WritePhi payload

in every meaningful sense except the substrate stack. Store asset.

Prep

Payload already built at BURN_ME/ — 27 files, ~950 KiB.

Rebuild with python tools/build_burn_payload.py if any IC changes.

Contents:

• README.txt — top-level explainer for anyone who inserts the disc
• MANIFEST.txt — SHA-256 of every file
• dies/ — 5 ICs × (.wpprog + .svg + .SPEC.md) = 15 files
• sdk/writephi/ — Python SDK so a reader can recompile
• docs/ — SPEC, COMPATIBILITY, IC_DESIGN_INDEX, PRODUCT_BRIEF, STATUS
• verify.py — self-check

Burn (Windows 11, no extra software)

1. Insert a blank BDXL into the drive.

2. Windows will prompt for a format. Pick **"Like a USB flash drive

(Live File System)"**. Name the disc WRITEPHI_57.

3. Open the drive letter in Explorer.

4. Open a second Explorer window at

C:\Users\crione\Chris\special\57-chip-write\BURN_ME.

5. Select all files in BURN_ME and drag them to the disc.

6. When copy finishes, right-click the drive → Close session.

(Or eject and Windows will close it for you.)

Burn (ImgBurn, cleaner ISO)

1. Build image file from files/folders.

2. Source: C:\Users\crione\Chris\special\57-chip-write\BURN_ME.

3. File system: UDF 2.60. Volume label: WRITEPHI_57.

4. Save .iso somewhere (e.g. ~/Chris/System/shipped-downloads/).

5. Insert blank, Write image to disc, verify on.

Verify (mandatory — this is the whole point)

After burn, take the disc OUT, put it back IN so you're reading from

the actual optical surface, not the write cache.

D:
cd \
python verify.py

Expected end line:

26 ok · 0 mismatch · 0 missing (out of 26 expected)

If ANY line reads MISMATCH — the write channel has a defect on that

track. Reburn or mark the disc bad.

After a clean verify

You now have physical proof of life for WritePhi. Options:

• Photograph the disc with a decent camera at glancing light so the

burn ring is visible. Best possible product photo for the store page.

• Add a "verified burn" badge to the store description referencing

the SHA-256 of the payload.

• Ship a copy with a $1T All In One deliverable — the buyer gets a

real optical WritePhi disc, not just a download link.

• Do nothing. It's a receipt for you. The engineering package is

what sells.

What did NOT happen here

• No transistor was fabricated.
• No calibration ran on physical hardware.
• No WRITER appliance exists — the disc is written by a Pioneer/LG/ASUS

drive, not a WritePhi WRITER.

Those are all buyer scope. This burn is scoped to "the byte stream

survives real optics." Which is the honest first-mile claim.

If the drive rejects the blank

• BDXL blanks are 100 GB (BD-R XL 3-layer) or 128 GB (BD-R XL 4-layer).

Check the disc says BDXL, not BD-R DL / BD-R.

• Drive may need a firmware update — check Pioneer/LG/ASUS support.
• Some early BDXL drives only write 100 GB, not 128 GB.

If verify fails

• Try a slower write speed (2x instead of 4x/6x).
• Try a different blank — some BDXL brands read cleaner than others per

COMPATIBILITY.md § BDXL blanks Path 2.

• Clean the drive laser (canned air, no isopropyl on the lens).

WritePhi — Consumer Compatibility

WritePhi — Consumer Compatibility

Project 57 · cri-one.com portfolio · 2026-07-04 · Revision 0.1

You do not need custom-built infrastructure to bring up WritePhi. Every subsystem in the family that touches a commodity ecosystem (BDXL drives, BDXL blanks, PCIe 5.0 hosts, USB-C hosts, dev tools) is designed against off-the-shelf consumer hardware.

Important caveat. This document is a reference-integration matrix, not a certified-compatibility list. The delivered engineering package specifies interfaces and expectations; the buyer is responsible for validating any specific piece of consumer gear against those specifications. Model numbers below are examples that meet the interface spec at the time this document was written.

1. BDXL optical drives (WRITEPHI-WRITER)

WRITEPHI-WRITER (rev 0.2) rides on a commodity BDXL optical drive assembly. Any BDXL-capable optical drive that meets the following interface spec can serve as the write head:

• 405 nm blue-violet write laser (BDXL standard)
• Triple-layer 100 GB or quad-layer 128 GB BDXL support
• SATA or manufacturer-specific command bus (per hardware/WRITER_APPLIANCE_SPEC.md § 2.3)
• Sharp / Panasonic / Pioneer / LG optical head assembly

Reference drives that meet the interface spec (at the time of writing):

What the buyer does with a stock drive. Repurpose the optical head + servo + spindle + tray-load. Replace the drive's data-storage firmware with the WritePhi custom write firmware (firmware/writer_control). The drive assembly's own SATA / USB stack is bypassed; the BDXL command bus is retasked to write WritePhi circuit patterns into WritePhi blanks (Path 1) or into stock BDXL scaffolds (Path 2, per hardware/BLANK_MEDIA_SPEC.md § 3.2).

2. BDXL blank media (WRITEPHI-BLANK Path 2, education/hobbyist)

For Path 2 adopters (education / hobbyists validating the invention with stock BDXL media before Path 1 blanks are available in volume), any commodity BDXL blank works:

Path 2 requires a follow-on process step (deposition / plating / doping) to convert the written optical pattern into circuit elements. Path 1 blanks (WRITEPHI-BLANK-M / -H / -M-P) do not — they ship pre-primed with the WritePhi custom recording chemistry.

3. PCIe 5.0 hosts (WRITEPHI-CHASSIS-CARD-4C / -8C)

WRITEPHI-CHASSIS-CARD-4C is a standard PCIe 5.0 x8 add-in card. WRITEPHI-CHASSIS-CARD-8C is PCIe 5.0 x16. Both drop into any PCIe 5.0 slot with sufficient physical clearance and TDP budget (75 W per PCIe 5.0 CEM baseline, or 150 W with the optional 6-pin AUX connector populated).

3.1 Portfolio-native hosts (the intended integration path)

The two portfolio-native hosts drop these cards in seamlessly — the AutoPhi 1Z-Edge bus master on the card and the AutoPhi host boards share the same architecture family.

3.2 Commodity x86 hosts (drop-in compatible)

Any modern PCIe 5.0-capable motherboard:

Any motherboard that lists PCIe 5.0 support on its spec sheet is a candidate. WRITEPHI-CHASSIS-CARD-4C respects the PCIe 5.0 CEM specification (physical + electrical) — it does not require chipset-specific features.

4. USB-C 3.2 Gen 2×2 hosts (WRITEPHI-WRITER + WRITEPHI-DICER)

The writer and dicer controllers use USB-C 3.2 Gen 2×2 (20 Gbps) as the primary host link. Compatible hosts include:

The writer will fall back to USB 3.2 Gen 2 (10 Gbps) or USB 3.2 Gen 1 (5 Gbps) on hosts that do not support Gen 2×2 — SDK-level compilation and design-file transfer work at all three speeds. Write throughput is not host-bandwidth-limited (see hardware/WRITER_APPLIANCE_SPEC.md § 2 write-time budgets).

5. UniPhi wireless (optional, WRITEPHI-WRITER + WRITEPHI-DICER)

The optional wireless daughtercard uses the UniPhi Retroactive Wireless Adapter (USPTO Application No. 19/717,706, Confirmation 7171, filed 2026-06-24). UniPhi is portfolio-native (sibling Project 53). No consumer-side compatibility list — UniPhi is Chris's own IP and the wireless link is closed.

6. Operating systems (host running the SDK)

The SDK is Python 3.11+ / C standard library. Host OS support:

7. Development tools

8. Test & socket-cycling equipment (optional prosumer)

For buyers who want to exercise the socket assembly at manufacturing sample count:

These are cited in hardware/PKG_SOCKET_BGA_SPEC.md § 12 as prior art the WritePhi socket-BGA design is distinct from. The buyer may exercise them for lifetime testing at production sample count.

9. What is NOT compatible (honest report)

• Consumer 3D printers. WritePhi is not a 3D printer. The WRITEPHI-DICER is a UV galvo laser cutter, not an FDM or SLA head. Consumer 3D printers and WritePhi share nothing but the general "desktop fabrication" market category.
• Pre-packaged silicon BGAs. WRITEPHI-PKG-M and -H accept a bare polycarbonate WritePhi die. They do not accept a conventional silicon-BGA'd chip. Aries / Ironwood / Yamaichi test sockets are not interchangeable with WritePhi packages.
• Non-BDXL optical drives. DVD-only and Blu-ray-single-layer-only drives lack the 405 nm write source and the multi-layer stack the WritePhi writer expects. BD-R BDXL support is required.
• Consumer optical drives with proprietary firmware locks. Some retail BDXL drives will refuse custom firmware. Buyer verifies drive-firmware openness before purchase for bring-up. Bulk/OEM variants typically have fewer locks than retail-boxed variants.
• Pre-Zen-4 AMD or pre-12th-gen Intel — PCIe 5.0 required for CHASSIS-CARD variants.
• PCIe 4.0 slots. CHASSIS-CARD-4C/-8C requires PCIe 5.0. It will physically fit and enumerate in a PCIe 4.0 slot but at half the aggregate bandwidth.

10. Retained IP note

The compatibility statements above do not license or authorize use of any WritePhi-retained IP with the named consumer equipment. See LICENSE.md. Consumers who integrate WritePhi with the equipment above do so under the terms of the purchase-and-commercialization-rights transaction, not under a component-vendor certification.

Revisions

WritePhi — IC Design Index

WritePhi — IC Design Index

Project 57 · cri-one.com portfolio · 2026-07-04 · Revision 0.1

Every integrated circuit named in the delivered schematics, categorized as portfolio-native (Chris's IP, licensed under the WritePhi engineering-package terms), commodity third-party (off-the-shelf; buyer sources direct), or buyer-scope (defined by interface only, buyer designs or contracts).

1. Portfolio-native ICs

Chris's IP. Not sold à la carte with WritePhi — referenced here as engineering dependencies. Separate licensing negotiations apply if the buyer wants standalone use.

2. Commodity third-party ICs (buyer sources direct)

Every third-party IC named in the schematics. Off-the-shelf, established supply chain, buyer procures from the manufacturer or authorized distributor.

2.1 USB + PD (WRITER-CTRL, DICER-CTRL)

2.2 PCIe (CHASSIS-CARD-4C)

2.3 Power (all boards)

2.4 Motor / stepper drivers

2.5 Analog / ADC / DAC

2.6 Temperature sensors

2.7 Protection

2.8 Miscellaneous

3. Buyer-scope ICs (specified by interface, not by part number)

Interfaces defined; buyer designs or contracts to a specific IC.

4. WritePhi native "IC" — the written die itself + reference designs

The WritePhi die (M-grade or H-grade) written by the WRITEPHI-WRITER and inserted into a WRITEPHI-PKG socket is itself the primary "IC" of the family. Every other IC in this index exists to write, dice, package, or integrate the WritePhi die.

• M-grade die: 84-contact interface, 1.0 mm pitch. Feature size ≥ 2 µm. Power envelope ≤ 500 mW (passive) / ≤ 2 W (active cooling). See hardware/PKG_SOCKET_BGA_SPEC.md § 2.
• H-grade die: 168-contact interface, 0.5 mm pitch. Feature size ≥ 0.5 µm. Power envelope ≤ 5 W (active cooling).
• Design files for WritePhi dies are authored in the SDK (sdk/python/), compiled to .wpprog, and shipped to the writer.

4.1 Reference IC designs shipped with the engineering package

Five native WritePhi ICs, each with a compilable design.py, a SPEC.md, and a ready-to-write .wpprog:

Compile any of them with:

cd ic_designs/WPIC_<name>/
python design.py

A ready-to-use reference carrier board for WPIC-SPI-DAC-01 lives at ic_designs/WPIC_SPI_DAC_01/reference_carrier/ — RP2040 host + WRITEPHI-PKG-H socket + 4 SMA outputs, 56 components, ERC-clean. Shows a buyer exactly how a written WritePhi chip drops into their PCB.

4.2 The larger design library

The five reference ICs above are the initial seed. The full WRITEPHI-LIB subscription (Project 57 SKU) provides ongoing access to the 1,000 IC design catalog from Parts Future (Project 24) as the marketplace of pre-designed WritePhi chips. See PRODUCT_BRIEF.md § "The four SKUs" for the recurring-revenue business context.

5. Firmware ICs (portfolio-native software)

The firmware running on portfolio-native ICs is delivered as skeleton per firmware/:

6. Retained IP

Everything in § 1 (portfolio-native) is retained by the inventor per LICENSE.md. The engineering package licenses the disclosure + commercialization rights for the WritePhi four-SKU family; it does not license the underlying AutoPhi / UniPhi / ExitPhi / Parts Future IPs for standalone use.

Everything in § 2 (commodity third-party) is licensed by the buyer directly from the manufacturer per standard commercial terms.

Everything in § 3 (buyer-scope) is the buyer's design or contract responsibility.

The WritePhi die in § 4 is what the buyer produces using the delivered family. Every die written by a WRITEPHI-WRITER is the buyer's product to sell, subject to the terms of LICENSE.md.

Revisions

WritePhi — The Design Loop

WritePhi — The Design Loop

Project 57 · 2026-07-05

Chris asked for the real chip-design loop:

> "compute, then do a virtual burn then a study then another steadfast

> compute and then another virtual burn then another steadfast then

> another compute… then a real burn."

This is that. One command runs the whole thing.

The four moves

1. COMPUTE. Run the Python build_design() function for an IC. It

emits a netlist of VirtualTransistors and Pads. The switch-level

simulator (sdk/python/writephi/simulate.py)

evaluates it: each FET is a gate-controlled switch, node states are

iterated to a fixed point, VDD / GND / inputs pin the drivers.

2. VIRTUAL BURN. Compile the design to a .wpprog byte stream

(real WPPROG01 wire format — header + calibration + write sequence +

self-verify + footer). Render an SVG floorplan of the die

(tools/render_die.py) — NMOS row on the

bottom, PMOS row on the top, pads on the perimeter, interconnects

routed manhattan.

3. STUDY. Read the testbench report. Every design has a

run_testbench() that drives its inputs through a truth table and

asserts the outputs. Failures point at the next iteration.

4. REAL BURN. After every listed IC's testbench is green, refresh

BURN_ME/, drag it to a BDXL disc in Explorer, close the

session, run python verify.py from the disc, done.

Run the whole loop

python tools/loop.py                       # every IC
python tools/loop.py --ic WPIC_INVERT_02   # one IC
python tools/loop.py --payload             # + rebuild BURN_ME/ if all green

Output:

=== WPIC_INVERT_02 ===
  22 FETs, 16 pads, 662 B .wpprog
  Testbench: 20/20 assertions passed

...

| IC | FETs | Pads | .wpprog | Testbench |
|----|------|------|---------|-----------|
| WPIC-INVERT-02 | 22 | 16 | 662 B | 20/20 pass |

Loop position (2026-07-05)

See STUDY_REPORT.md for the per-iteration detail.

Add a testbench to any IC

Drop a run_testbench() function next to build_design() in that

IC's design.py. Return a TestBench from writephi.testbench:

from writephi import TestBench

def run_testbench():
    d = build_design()
    tb = TestBench(d, watch=['A', 'B', 'Y'])
    tb.set('A', '0'); tb.set('B', '1'); tb.step('A=0 B=1')
    tb.assert_eq('Y', '1', 'expected result')
    return tb

tools/loop.py will pick it up automatically on the next run.

What the loop refuses to do

• Emit a .wpprog for a testbench that failed. INVERT_02's design

file itself exits non-zero if any assertion misses. tools/loop.py

records the failure but never overwrites a good .wpprog with a bad

one silently.

• Refresh BURN_ME/ if any IC is red. --payload runs only after

every listed IC's testbench is 100% green.

What the real burn will and won't prove

Even after every testbench passes:

• Will prove: the netlists compute correctly in-simulator, the

.wpprog bytes survive a real optical write / read cycle

(SHA-256 in the burn payload's MANIFEST.txt), and a commercial BDXL

drive is a viable physical carrier for WritePhi write programs.

• Won't prove: functional silicon. The blank stack in Chris's BDXL

is dye, not the photoresist-on-substrate specified in

BLANK_MEDIA_SPEC.md. Real chip fab

needs the buyer's substrate supply chain per

[[feedback-schematic-is-chris-ceiling]].

That gap is the honest boundary of what one person + a BDXL drive can

prove. Everything on this side of the gap is real.

---

This archive contains 17 documents; 6 more beyond this preview. The complete folder ships as the product.