59-verifyphi

Description

VerifyPhi — Design Verification Pipeline for Optical Circuit Substrates (Project 59, SKU 2090)

Patent-pending. USPTO non-provisional utility application 19/731,098 , filed 2026-07-05 3:04 PM ET. Confirmation 5973, Patent Center 78285110. Title of invention: Verification-Gated Compile-and-Optical-Write Pipeline for Photolithographic Circuit Substrates. 15 claims (4 independent, 11 dependent) across four independent claim clusters. 6 figures. Filed pro se. Related earlier filing: USPTO framework application 19/693,405 (2026-05-30). Priority chain anchored to Invent Depositions (ISBN 978-1-979767-89-7, 2017-11-24) and buyinvent.com catalog entries 730, 781, 784, 785, 837, 879, 881, 926, 927, 1160–1164, 1184–1189, 1446–1452, 1730–1733. Inventor: Christopher Gabriel Brown . Status: filed, pending examination.

Overview

VerifyPhi is the design-verification pipeline that decides whether a chip design is allowed to reach any writable optical circuit-processor substrate (WRITEPHI-BLANK, Project 57). It is the software half of the WritePhi platform — the switch-level CMOS simulator, the compile-time verification gate, the self-authenticating writable-medium architecture, the pre-dice wafer probe pattern geometry, and the automated iteration loop that ties them together.

WritePhi is the writer. VerifyPhi is what refuses to feed it an unverified design.

The pipeline runs today as delivered software. On the day the patent was filed (2026-07-05), it caught two real chip-design bugs before either could reach the physical write channel: (1) dangling FET sources in a stub toggle-flop that would have silently emitted a dead netlist, and (2) a ripple counter clocked on the wrong edge polarity that would have produced Gray-code-adjacent output instead of binary UP count. Both bugs were fixed in the same iteration session. The rebuilt designs pass 20/20 gate assertions and 12/12 counter-cycle assertions.

Subsystem Architecture

VerifyPhi comprises five subsystems, each individually claimed in USPTO application 19/731,098:

Subsystem Function Patent Claims Figures Status

VERIFYPHI-SIM Switch-level CMOS simulator Claims 2, 3 FIG. 5 Runs. Verified.

VERIFYPHI-GATE Compile-time verification gate Claims 1, 4, 5 FIG. 1, FIG. 6 Runs. Verified.

VERIFYPHI-MEDIUM Self-authenticating writable optical medium Claims 6, 7, 8 FIG. 2 Runs. Verified.

VERIFYPHI-PROBE Pre-dice wafer probe pattern geometry Claims 9, 10, 11, 12 FIG. 3 Rendered. Geometry delivered.

VERIFYPHI-LOOP Design → simulate → virtual burn → study → real burn iteration driver Claims 13, 14, 15 FIG. 4 Runs. Verified.

VERIFYPHI-SIM — Switch-Level CMOS Simulator

The simulator models each VirtualTransistor as a gate-controlled switch. NMOS conducts drain-to-source when its gate voltage is HIGH; PMOS when its gate voltage is LOW. Node values inhabit the domain {LOW, HIGH, FLOATING, CONFLICT} . Nets named VDD are forced HIGH; GND forced LOW; testbench-driven inputs are forced to the caller’s value.

The solve routine iterates to a fixed point:

• Seed all nets to FLOAT.
• Apply forced drivers and rail nets.
• Union-find groups of nets connected by conducting transistors (using the prior iteration’s gate values).
• Resolve each connected component: any HIGH + any LOW → CONFLICT; else HIGH if any; else LOW if any; else fall back to sequential-latch memory; else FLOAT.
• Repeat until state is stable or iteration cap reached.

Latch-memory subsystem Simulator.latch() / .unlatch() — freezes named nets as sequential storage; engaged only when no active driver contests the group

Language Python 3.10+, stdlib only, zero pip dependencies

When a design source file ( design.py ) is executed, the gate runs five steps in strict order:

• build_design() → Design object with VirtualTransistor , Interconnect , Pad , and named Net primitives.
• run_testbench() → TestBench with named assertions.
• Simulator iterates the netlist under each input vector; assertions record pass/fail.
• If any assertion fails → sys.exit(1) without writing .wpprog . The physical write channel cannot receive the design.
• Only on 100% pass does design.compile() serialize the netlist to the .wpprog byte stream.

Header Magic ( WPPROG01 ), version identifier, grade code, payload checksum, payload length, design name (14 bytes)

Calibration bytecode Minimum-feature (nm), contact-pitch (μm), layer count, reserved

Write-sequence bytecode One opcode-tagged record per transistor ( 0x10 , 11 bytes), interconnect ( 0x20 , 6 bytes), and pad ( 0x30 , 19 bytes)

• The per-die verified design payloads ( .wpprog )
• A copy of the design SDK (for buyer-side re-compilation)
• Documentation
• MANIFEST.txt — SHA-256 hash of every other file on the medium
• verify.py — executable that re-hashes every file on the medium after insertion and reports any mismatch

Any write-channel defect (bit flip, sector rewrite) produces a hash mismatch. Post-write medium integrity is verified independently of the writing device. On 2026-07-05, the self-authenticating payload reported 48 ok, 0 mismatch, 0 missing (48/48 clean).

IC tabs per die 2 — asymmetric widths (pin-1 large, opposite small) for fool-proof orientation

Alignment fiducials per die 3 — pin-1 dot, center square, diagonal cross (distinct geometry)

Pad-link traces per die 4 signal-pad traces routed from die edge to common outer test ring

Common outer test ring Concentric with substrate axis; permits ring-shaped wafer-probe card to exercise every die simultaneously prior to dicing

Wafer-probe card fabrication is buyer scope; VerifyPhi delivers the geometry specification. The wafer floorplan generator ( render_wafer.py ) produces SVG at 120 mm scale. A companion tool ( build_label_pdf.py ) generates a print-ready 120 mm × 120 mm PDF label for Primera Bravo / PTPublisher disc publishing.

• COMPUTE — build_design() + run_testbench() per IC.
• VIRTUAL BURN — emit .wpprog (gated on 100% pass) + render die SVG.
• STUDY — record assertion report; write per-IC summary.
• PAYLOAD REFRESH — if every listed IC is green, rebuild the burn payload ( BURN_ME/ ).
• REAL BURN — hand-off to physical write channel (BDXL drive or Primera Bravo publisher).

The loop refuses to emit a .wpprog for any testbench that fails. It refuses to refresh the burn payload if any IC is red. These refusals are the core guarantee: unverified designs cannot reach the write channel.

Usage:

• python tools/loop.py — iterate all 11 listed ICs
• python tools/loop.py --ic WPIC_INVERT_02 — iterate one IC
• python tools/loop.py --payload — iterate all + rebuild burn payload if all green

Reference IC Designs — Verified and Shipped

The bundle includes 11 reference integrated circuit designs. Two are fully simulator-verified with testbenches (20/20 and 12/12 assertions), five are compile-verified, and four additional designs are shipped with compiled .wpprog and rendered die floorplans:

IC SKU Grade Function FETs Signal Pads .wpprog Size Testbench Status

WPIC-INVERT-01 M Hello-world CMOS inverter + 4-bit ripple counter stub 27 8 602 B Inverter 2/2 pass; counter is documented stub (dangling sources)

WPIC-INVERT-02 M Simulator-verified CMOS gate library (INV, NAND2, NOR2, AND2, OR2) 22 16 662 B 20/20 pass

WPIC-COUNTER-01 M Master-slave D-flop + 4-bit ripple counter 88 — — 12/12 pass

WPIC-COUNTER-04 M Extended counter design — — — Compile-verified

WPIC-ADD-4 M 4-bit adder — — — Compile-verified

WPIC-REG-8 M 8-bit register — — — Compile-verified

WPIC-UART-01 M 8N1 UART transceiver, 4-bit BAUD_SEL 300 12 3,958 B Compile-verified

WPIC-PWM-01 M 4-channel 12-bit PWM controller 480 58 7,038 B Compile-verified

WPIC-SPI-DAC-01 H 4-channel 12-bit SPI DAC 906 10 11,250 B Compile-verified

WPIC-AES-CORE H AES-128 accelerator, byte-serial (32 signal contacts) 3,160 32 38,698 B Compile-verified

WPIC-MEGA-COUNTER-ARRAY — Large-scale counter array — — — Compile-verified

Each design ships with source design.py , compiled design.wpprog , rendered die floorplan design.svg , and a per-die specification ( SPEC.md ). Total across the original five reference ICs: 4,873 transistors, 61.5 KB of compiled write programs. WPIC-SPI-DAC-01 additionally includes a complete reference carrier board ( reference_carrier/ ) with KiCad 10 schematic ( .kicad_sch ), schematic generator ( gen_schematic.py ), and board-level SPEC — an RP2040 host + WRITEPHI-PKG-H socket + 4 SMA outputs, 56 components, ERC-clean.

Grade Min Feature Signal Contacts Total Contacts Layers Media

M-grade 2 μm 64 84 3 BDXL 100 GB

H-grade 0.5 μm 128 168 4 BDXL 128 GB

M_P (portable) 2 μm 32 48 2 60 mm mini-BD

Grade selection is a Design attribute ( target_grade=TargetGrade.M ). Simulator behaviour does not change with grade — only compile-time constraint checks tighten. Designs exceeding grade limits emit ValueError .

SDK — __init__.py sdk/python/writephi/__init__.py Package entry; exports Design , VirtualTransistor , Interconnect , Pad , TargetGrade

SDK — simulate.py sdk/python/writephi/simulate.py Switch-level CMOS simulator (VERIFYPHI-SIM)

SDK — testbench.py sdk/python/writephi/testbench.py Testbench framework (assertions, waveform, reporting)

SDK — grades.py sdk/python/writephi/grades.py TargetGrade M/H/M_P + resolution constraint checks

Tool — loop.py tools/loop.py VERIFYPHI-LOOP iteration driver (157 lines)

Tool — render_die.py tools/render_die.py Die floorplan SVG renderer from .wpprog (270 lines)

Tool — render_wafer.py tools/render_wafer.py Wafer floorplan SVG renderer — all dies on one 120 mm BDXL (270 lines)

Tool — build_burn_payload.py tools/build_burn_payload.py Assembles BURN_ME/ payload + MANIFEST.txt + verify.py (244 lines)

Tool — build_label_pdf.py tools/build_label_pdf.py Converts wafer.svg to print-ready 120 mm PDF for Primera Bravo (56 lines)

All SDK modules and tools are stdlib-only Python 3.10+. No pip dependencies required. build_label_pdf.py optionally uses svglib + reportlab for PDF generation.

Optical write channel Any BDXL drive or Primera Bravo disc publisher supporting BD-R XL blanks

Reference drives Pioneer BDR-212DBK, LG WH16NS40, ASUS BW-16D1HT, Panasonic UJ-260, Verbatim 43886

Claim 1 Independent Method of preparing optically-written substrate with verification-gated payload emission

Claim 2 Dependent (1) Switch-level simulator with union-find, {LOW, HIGH, FLOATING, CONFLICT} domain, fixed-point iteration

Claim 3 Dependent (2) Sequential-latch memory — latched net retains value only absent active driver

Claim 4 Dependent (1) .wpprog byte stream format: header + calibration + write-sequence + self-verify + SHA-256 footer

Claim 9 Independent Photolithographic substrate with radial dies, scribe lines, asymmetric tabs, fiducials, test ring, pad links

Claim 13 Independent Design-iteration pipeline: loop driver + gated payload builder + self-verification manifest

FIG. 2 Self-authenticating writable optical medium and verifier flow FIG2_self_authenticating_medium.svg

FIG. 3 Pre-dice wafer probe pattern on optical substrate FIG3_wafer_probe_pattern.svg

FIG. 4 Design → simulate → virtual burn → study → real burn loop pipeline FIG4_loop_pipeline.svg

Priority anchors trace to Christopher Brown’s 2017 printed publication Invent Depositions (ISBN 978-1-979767-89-7, published 2017-11-24) and the 2018–2019 buyinvent.com catalog entries:

Entry/Range Anchor

730 Verification-gate concept — “software driven registration for designing acceptable circuit driven operations”

The chain closes with the 2026-05-30 portfolio-wide framework filing (USPTO 19/693,405) and the 2026-07-05 non-provisional utility filing (USPTO 19/731,098).

57 WritePhi Writer hardware + blank + design library + server bed. VerifyPhi gates what the writer is allowed to write.

58 WritePhi Devices WPD-CSD + WPD-ACCEL PCIe cards. VerifyPhi’s compile-gate operates on WPD design files.

21 Day-One Fabrication Commercial foundry counterpart. VerifyPhi works against DOF design-source directories.

VerifyPhi is buyable independently of any sibling. It operates on any design source that follows the WritePhi SDK conventions. Its output is netlist-format-neutral — VerifyPhi-verified designs can be routed to a conventional commercial foundry as a legitimate buyer path.

What Is in the Package

The VerifyPhi standalone bundle ( verifyphi.crione.zip , SHA-256: a7156b... ) ships 100 files across the following inventory:

Project 59 Core Documents

• README.md — project overview + integration with sibling projects
• SPEC.md — full technical specification (5 subsystems, 3 grades, compatibility)
• PRODUCT_BRIEF.md — business summary + pricing ($25M) + terms
• PLAYBOOK.md — buyer-side bring-up sequence (Day 0 through Month 3)
• LICENSE.md — deliverable license (IP-retained, USA-only, USD, buyer-bankruptcy shield, 10 sections)
• STATUS.md — honest engineering status per subsystem
• STORE_LISTING.md — store-page copy brief
• HANDOFF.md — session handoff + pickup queue
• MANIFEST.json — machine-readable inventory (105 lines)
• CONTACT_INFO.txt — inventor + delivery contact
• bundle.py — reproducible bundler (236 lines, stdlib-only Python)
• verifyphi_store_description.html — deployable Magento store description

Patent Materials ( patent/ )

• DISCLOSURE.md — full as-filed patent disclosure (286 lines, 15 claims, 6 figures, prior-art analysis)
• DISCLOSURE.docx — USPTO-formatted submission document
• DISCLOSURE.sha256 — cryptographic timestamp anchor
• FILING_OPTIONS.md — filing strategy analysis (5 paths, A through E)

Patent Figures ( figures/ )

• 6 patent figures as SVG: FIG1_verification_gate.svg through FIG6_cmos_nand_topology.svg
• Product art: verifyphi_flat_symbol.png , verifyphi_flat_symbol_200.png , verifyphi_flat_icon.png , verifyphi_flat_store_display.png , verifyphi_flat_store_display_1000.png
• generate_flat_pngs.py — product art generator

WritePhi Reference Source ( writephi_reference/ )

• SDK ( sdk/python/writephi/ ): 6 Python modules — __init__.py , design.py , compile.py , simulate.py , testbench.py , grades.py
• Tools ( tools/ ): 5 scripts — loop.py , render_die.py , render_wafer.py , build_burn_payload.py , build_label_pdf.py
• IC Designs ( ic_designs/ ): 11 IC directories, each containing design.py , design.svg , design.wpprog , and SPEC.md ; WPIC-SPI-DAC-01 additionally contains reference_carrier/ with KiCad schematic + generator + SPEC
• Documentation : SPEC.md (WritePhi full spec, revision 0.3), COMPATIBILITY.md (consumer compatibility matrix), IC_DESIGN_INDEX.md (IC index with all portfolio-native, commodity, and buyer-scope ICs), STUDY_REPORT.md (per-iteration simulator results), LOOP.md (design loop documentation), BURN_INSTRUCTIONS.md (first physical burn recipe)

Bundle Integrity

• BUNDLE_MANIFEST.txt — SHA-256 hash of every file in the bundle (100 entries)
• README.txt — top-level bundle explainer with verification command
• verifyphi.crione.sha256 — companion checksum for the zip archive

• Simulator port to production EDA tools (Verilator, Icarus Verilog, VCS) for designs above ~100K transistors
• Wafer-probe card fabrication for VERIFYPHI-PROBE
• Physical WRITEPHI-BLANK substrate manufacture (buyer supplies photoresist stack)
• FCC / UL / CE / IEC 60825 laser safety certification of any deployed WRITEPHI-WRITER
• Silicon tape-out via any conventional foundry (legitimate buyer path — VerifyPhi output is netlist-format-neutral)

Payment Wire transfer or escrow via seller-approved escrow agent. Term Sheet required at $10k+ tier.

Delivery Email delivery (zip + SHA-256 sign-off) + optional physical BDXL disc via U.S. Postal Service certified mail

IP retention All IP retained by inventor. No patent license, no use license, no sublicense. Buyer receives artifacts only.

Buyer bankruptcy shield License survives buyer bankruptcy; no IP transfers to trustee. Seller has NOT filed for bankruptcy.

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

© 2026 Christopher Gabriel Brown. All rights reserved.

Disclaimer: All products on this store are fictional ICs and designs. Nothing on this page constitutes an offer of functional semiconductor devices. The engineering packages described are design documentation, source code, and specifications only.

Photo