79-writephi-2

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Asset valuation: $16,000,000,000. Project 79 · cri-one.com portfolio · 2026-08-04 The ordered how-to for standing up the platform. This document is the buyer-facing operating manual for WritePhi-2. It answers "we bought the design package — what do we do first, second, third?" It is deliberately ord

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Valuation

Generous asset valuation: $16,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

WritePhi-2 — Buyer Playbook

Project 79 · cri-one.com portfolio · 2026-08-04

The ordered how-to for standing up the platform.

This document is the buyer-facing operating manual for WritePhi-2. It answers "we bought the design package — what do we do first, second, third?" It is deliberately ordered by dependency, not by category: each numbered step unlocks the next.

Phase 0 — Prerequisites

Before Day 1 of the buyer engagement, the buyer procures (independent of the WritePhi-2 package):

1. A WritePhi Writer. From Project 57. One unit is enough for the pilot. Chris does not resell WritePhi Writers as part of Project 79; the buyer contracts to the Project 57 SKU directly.

2. A WritePhi Dicer. Same source.

3. A CXL 3.0-capable server for host-side testing. Any Sapphire Rapids / Emerald Rapids / EPYC 9004+ / EPYC 9005+ system with a DDR5 slot that routes CXL. A single dual-socket server is sufficient for the pilot.

4. A small industrial site. ~1,000 sq ft. Standard commercial power (208 V three-phase preferred, 120 V single-phase acceptable at pilot scale). No cleanroom, no cryostat, no chilled water.

5. A specialty-chemical partner for Q-Blank recording chemistry. One US supplier willing to co-develop under NDA. Preference: an established supplier of Ormocer, chalcogenide, or sol-gel photoresist chemistries.

Phase 1 — Chemistry selection (weeks 1-6)

The Q-Blank recording chemistry is the single blocking item. All Phase-2 and later work assumes chemistry-in-hand.

1. Convene chemistry review. With the specialty-chemical partner, review the three candidate families (Ormocer / chalcogenide / photorefractive sol-gel) against the WritePhi Writer's laser wavelength and pulse profile. Select one.

2. Fabricate first Q-Blank batches. Small runs (100 discs each) with the selected chemistry, applied to the standard BDXL polycarbonate envelope. Coordinate with the buyer's Q-Blank substrate source.

3. Characterize. Measure propagation loss at 1550 nm, thermo-optic stability, photostability under continuous illumination. Compare against the SPEC targets. Iterate chemistry if needed.

4. Freeze chemistry rev 1. File the inventor-record entry 79-E under the buyer's licensed IP scope with 2026-08-04 priority.

Phase 1 exit criterion: a batch of ≥ 10 characterized Q-Blanks meeting the SPEC targets for loss, stability, and photostability.

Phase 2 — First-write bring-up (weeks 7-10)

1. Compile a reference .wpq design. Start with the Bell-pair example in wpqc/examples/bell_pair.wpq — it is small, fast to write, and yields an easily-verified test article.

2. Write the first Q-Blank. Load a Phase-1 Q-Blank into the WritePhi Writer. Run the .wpprog produced by wpqc build bell_pair.wpq.

3. Dice. Run the Dicer over the written Q-Blank. The Bell-pair example dices to a single strip; larger designs dice to N strips.

4. Inspect. Optical inspection under a standard photonic-integrated-circuit inspection microscope. Confirm the waveguide, resonator, and phase-shifter features match the .wplayout.

5. Repeat. Write and inspect five more Q-Blanks with the same Bell-pair design. Confirm write reproducibility (all five produce visually identical layouts).

Phase 2 exit criterion: five Q-Blanks written with the same design, all visually correct on inspection.

Phase 3 — Bridge PCB fabrication (weeks 7-12, parallel to Phase 2)

1. Draft the bridge PCB schematic. From the SPEC.md component list: CXL controller (buyer-selected: Astera Leo / Marvell Structera / Microchip PM8000), quad-core ARM Cortex-A55 (or an AutoPhi Modern soft core if licensed), photonic transceiver, V-groove fibre array footprint, DDR5 edge-connector fingers.

2. Contract PCB fab. Standard 8-layer FR-4, 50-mm × 20-mm outline, no exotic materials. Any US PCB fab.

3. Populate. Standard SMT assembly at any contract manufacturer. Add the photonic transceiver in a subsequent optical-packaging pass at a photonic-packaging vendor (Bright Photonics, PhotonDelta partner, or equivalent).

4. Bring up the CXL controller. Program the CXL controller firmware. Confirm the bridge PCB enumerates as a bare CXL 3.0 Type-2 device on the buyer's test server. At this point the disc is not yet attached and the DIMM only responds to CXL.io control-plane traffic; that is expected.

Phase 3 exit criterion: the bridge PCB enumerates on a CXL 3.0 host without a disc attached.

Phase 4 — First-DIMM assembly (weeks 13-16)

1. Polish coupling edges. Take one of the Phase-2 Q-Blanks. Run it through the Dicer's coupling-edge polishing pass.

2. Bond disc to fibre array. Align the polished disc edge to the V-groove fibre array on the bridge PCB, using the fiducials the Writer inscribed. Bond with a UV-cure optical adhesive.

3. Assemble DIMM. Bond the bridge PCB + disc subassembly to the DDR5 edge-connector board. Attach the heat spreader.

4. First-power test. Insert the DIMM into the buyer's test server's DDR5 slot with CXL 3.0 support. Confirm the host enumerates it as a CXL Type-2 memory-semantic device with the expected tile-region address map.

5. First Bell-pair run. Use the WritePhi-Q Tier-2 test harness to write the Bell-pair input to the correct tile region and read the measurement outcomes. Confirm the outcome statistics match the expected Bell-pair correlations.

Phase 4 exit criterion: the first WPQ-DIMM produces correct Bell-pair correlations on a CXL 3.0 host.

Phase 5 — First customer application (weeks 17-24)

Choose one:

AI/ML CIM offload. Compile a small attention-head kernel from the WritePhi-Q Tier-3 examples. Benchmark against a reference DDR5 + GPU baseline on a modest transformer workload. Publish the result as a case study to the WPQ-Library.
Defense signal-processing pilot. Compile a small FFT / correlation / adaptive-filter design from the Tier-3 examples. Benchmark against the buyer's incumbent DSP baseline.
Research/algorithm-development pilot. Deploy the DIMM to a research group. Support the group's authoring of new WritePhi-Q designs and contribute those designs to the WPQ-Library.

Phase 5 exit criterion: a first end-user application running on the WPQ-DIMM with a published performance number against a well-documented baseline.

Phase 6 — Pilot assembly-site standup (months 4-9)

Once Phase 5 has validated the platform, scale from one hand-built DIMM to a pilot assembly line.

1. Site selection. Small industrial unit. 1,000-2,000 sq ft. Standard commercial power. Located wherever the buyer wants — the point of WritePhi-2 is that this can be anywhere, not just Silicon Valley.

2. Staffing. Four Writer operators, two Dicer operators, six assembly technicians, two test technicians, one supervisor, one QA technician. Sixteen direct manufacturing hires per shift. Community-college-trainable; no cleanroom certification, no physics degree.

3. Line layout. Writer bay (four Writers) → Dicer bay (two Dicers) → coupling-and-bond bay (four workstations) → DIMM assembly bay (six workstations) → test bay (four automated CXL bring-up stations).

4. First-shift target. 100 WPQ-DIMMs per shift. Sustain for one week. Iterate on line balance.

5. Second-shift add. Once first-shift is stable, add a second shift. Doubles output; workforce doubles.

6. Steady state. 500 WPQ-DIMMs per shift, three shifts per day. Roughly 300k DIMMs per year per site.

Phase 6 exit criterion: a pilot assembly site producing 500 WPQ-DIMMs per shift, three shifts per day, at ≥ 95 % yield.

Phase 7 — Scale-up (year 2+)

1. WPQ-Bed deployment. Ship the WPQ-Bed 16- and 32-DIMM chassis so buyers can consolidate multiple DIMMs into one CXL device.

2. Additional assembly sites. Replicate the pilot site's layout at additional locations. Rural Georgia, upstate NY, west Texas, Ohio, etc. Each site: 16 direct jobs per shift, three shifts, plus indirect roles.

3. WPQ-Library expansion. Publish the Advanced-tier stdlib entries (defense-grade cryptographic primitives, novel algorithm bundles). Ongoing subscription revenue.

4. Chemistry rev 2. Iterate the Q-Blank recording chemistry for lower loss, higher yield, and higher tile density. Reduces DIMM cost and increases capability per disc.

Phase 8 — What the buyer never has to do

Build a cryostat. WritePhi-2 does not need one.
Build a cleanroom. WritePhi-2 does not need one.
Negotiate HBM allocation with Samsung / SK Hynix / Micron. WritePhi-2 does not use HBM.
License a foreign fab. Every line of the BOM has a US-domestic source.
Compete with hyperscalers for memory supply. WPQ-DIMMs are made against orders, not against HBM allocation cycles.
Train physicists. Assembly technicians are community-college-trainable.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Available exclusively to companies incorporated, headquartered, and primarily operating in the United States. USD only. Email and postal mail only.

WritePhi-2 — Red-Team Technical Assessment

Project 79 · cri-one.com · 2026-08-05 · internal

Method: five independent literature-grounded reviews (write/chemistry, passive photonics, the quantum claim, classical-vs-quantum, system/packaging), each instructed to find why the product fails. This is the adversarial case — the buyer's physicist's memo — not a balanced brochure.

Bottom line

The idea underneath is strong: a photonic linear-algebra compute engine that lives near memory and serves the memory-bandwidth-bound AI/HPC market. That thesis (WHY_NOW) is real and well-argued.

But three of the product's defining claims each fail independently on the physics/engineering — and all three are removable without killing the value:

1. "Quantum" — unnecessary. Every workload pitched (matmul, FFT, unitary/attention, CIM) is done by classical optical interference. Quantum adds no speedup for any of them and imports an unwinnable claim.

2. "Written onto a Blu-ray disc" — the write-resolution, throughput, thermo-optic, and material-contrast requirements are mutually contradictory. No single written medium can be all of {high-resolution-writable, low-loss, low-thermo-optic, high-contrast, 10k-hr-stable, single-photon-emitting}.

3. "In a DDR5 DIMM via CXL-over-DDR5" — a physical-layer category error. CXL's PHY is PCIe SerDes; the DDR5 socket is a parallel bus to the memory controller. No host will route CXL to those pins. The product's own PCIe-card fallback is the only real path.

What survives is a genuinely credible product — see §7.

1. Scorecard

2. Write + chemistry — the resolution/speed contradiction

Sub-diffraction 250 nm patterning requires a nonlinear threshold process: two-photon polymerization (fs laser, quasi-stationary focus, ~100 nm lateral / 300 nm axial). A "Blu-ray-speed spinning disc" is linear 405 nm marking, diffraction-limited to ~285–480 nm, and cannot hold ±30 nm overlay on a rotating substrate. You get the resolution or the disc speed — not both. Even accepting serial TPP, filling a 120 mm disc at ~100 nm pitch is ~10¹³–10¹⁴ voxels; at the best parallel research rates (~2×10⁶ voxels/s) that is months-to-years per disc versus Blu-ray's minutes. Candidate chemistries: Ormocer (Δn ~0.001–0.02, passive), GST (a lossy binary switch, ~1 dB/element), Zr sol-gel (passive/gain) — none host a driven phase shifter or a single-photon source.

3. Passive photonics — thermo-optically self-defeating

The loss target (≤3 dB/cm straight) is actually reachable (written chalcogenide 0.11–1.47 dB/cm; PC slab 0.34–0.6 dB/cm) — but it is ~10³–10⁴× worse than SiN (0.016 dB/m) and irrelevant once you bend. The blocker is thermo-optics + contrast: polymers have the largest dn/dT of any platform (PC ≈ −1.0 to −1.3×10⁻⁴/K), so the spec's 1×10⁻⁴/K ceiling is already exceeded by the substrate, and 85 °C detunes a 5 µm ring by ~8 nm. And a written low-contrast index change (Δn ~10⁻³–10⁻²) needs ~100s-µm bend radii — a 5 µm ring needs Δn ~order-1, which writing can't produce. Photostability compounds it: a medium photosensitive enough to write is by construction photobleachable.

4. The quantum claim — a category error

KLM linear-optical gates (which the compiler's stdlib names) cannot be a static written structure. A linear-optical CNOT needs (1) ancilla single photons injected per gate, (2) photon-number-resolving detectors mid-circuit, (3) sub-ns electro-optic feed-forward. A passive written mesh illuminated by light is a fixed linear unitary on field amplitudes — i.e., classical interferometry. Add the detector problem (SNSPDs at 2–3 K, or room-temp SPADs at 10–20% efficiency = photon loss), the ~10% total loss budget quantum tolerates, and the open problem of room-temperature indistinguishable single-photon sources, and the "room-temperature written photonic quantum" premise collapses. Most charitable reading: classical optical matrix-multiply relabeled with quantum vocabulary.

5. Classical vs quantum — the value doesn't need quantum

Classical photonic accelerators (Lightmatter, Lightelligence, Celestial AI, Luminous) already do matmul, FFT, unitary transforms, and transformer attention with coherent classical light in MZI meshes — demonstrated, funded, shipping on PCIe/CXL. Quantum linear algebra (HHL) has been largely dequantized for the low-rank case AI uses and can't even output a classical result vector. So "quantum" adds no matmul/FFT/attention speedup — only caveats. The only genuinely-quantum item (Grover search) is a quadratic speedup that doesn't serve the AI/HPC workloads WritePhi-2 targets and doesn't fit a memory slot. The positioning is self-defeating: it dismisses Lightmatter/Ayar as "classical, not quantum," yet that classical work is WritePhi-2's real, credible product.

6. System — CXL-over-DDR5 is not a thing

CXL runs over the PCIe 5.0 electrical sub-block (serial, differential, on the CPU's Flex Bus lanes). A DDR5 288-pin socket is wired to the integrated memory controller as a parallel, source-synchronous bus with an I3C SPD sideband. There is no PCIe SerDes on those pins, and the host will never route a CXL stack to them. The sole "protocol-over-DIMM" precedent (Intel Optane DDR-T) worked only because Intel owned both ends. Compounding: no shipping CPU is CXL 3.0 — Sapphire Rapids is CXL 1.1, EPYC 9004 is 1.1, Turin/Granite Rapids are 2.0. Also, driverless enumeration is a Type-3 (memory) property; a Type-2 accelerator whose whole purpose is a compute op needs a driver. And ≥95% hand-assembly yield is refuted by fiber-coupling reality: a 0.5 µm offset costs ~3 dB, per-attach yields run 60–90%, and 0.95¹² ≈ 54% across 12 WDM channels — ≥95% overall needs automated ±0.1 µm alignment, not trainees without a cleanroom. The product's own PCIe 5.0 x8 shim is the only physically real form factor.

7. What survives — the credible product

Strip the three failing wrappers and a real, buildable, differentiated product remains:

> **A classical photonic optical-linear-algebra compute accelerator — matmul / FFT / unitary / attention / CIM in coherent light — on a PCIe/CXL add-in card (Type-2, with a driver), whose differentiation is a low-cost, domestic, fab-light way to fabricate the passive photonic circuits.**

The market thesis is intact (memory-bandwidth wall, domestic manufacturing, jobs).
The compute model becomes demonstrated-real (Lightmatter/Lightelligence/Celestial prove it).
The genuine potential innovation is the manufacturing idea — writing classical passive photonic circuits cheaply without a $20 B fab. That is interesting and defensible if the write process is validated for loss and contrast on real substrates. It is a rapid-prototyping / low-cost-fab story for classical silicon-photonics-class circuits, not a quantum story.

8. The falsifiable tests (what would change these verdicts)

Fair is fair — here is exactly what data would move each "implausible" toward "proven." If WritePhi pursues this, these are the milestones that matter:

1. Written waveguide, measured: propagation loss (<0.5 dB/cm target) and index contrast Δn, on the real polycarbonate stack — not a bulk-glass coupon.

2. A ring resonator written by the same writer: measured loaded Q (>10⁴) and resonance drift across 0–85 °C. If Δn is low, the 5 µm ring is off the table regardless.

3. A phase shifter with a stated drive mechanism (thermo-optic V_π or otherwise) written into the medium.

4. If quantum is retained: HOM two-photon interference visibility >0.9 between two written sources, and g²(0) ≪ 0.5 under pulsed excitation. Weak-coherent-light HOM caps at 0.5 — anything ≤0.5 proves it's classical. Plus the detector datasheet (efficiency, dark counts, operating temperature).

5. Write-time budget: measured areal/voxel rate × required feature density for one full disc — to prove it isn't months per unit.

6. System honesty: commit to the PCIe/CXL card, re-spec host CXL versions (1.1/2.0), present it as Type-2-with-driver, and show a per-coupling yield number with the pᴺ roll-up and the alignment method.

9. Recommendation

1. Reposition to classical photonic compute-in-memory on a PCIe/CXL card. Keep "photonic quantum" only as an explicitly-labeled, honest, far-future roadmap tier. This loses zero of the pitched value and removes the three unwinnable claims.

2. **Reframe the core innovation as low-cost domestic fabrication of classical passive photonic circuits** — and treat the write-process loss/contrast validation (tests 1–3) as the make-or-break program, because it is.

3. Fix the store/marketing copy accordingly. The current honesty in STATUS.md ("design targets, not measured") is the product's saving grace and must stay; but "photonic quantum compute" and "CXL 3.0 DIMM on Sapphire Rapids" should be corrected — they're the specific claims a technical buyer or investor will bounce on.

Net: as an honestly-labeled design + license package, the concept is a legitimate thing to sell. As a working product a skeptic would test, the quantum + written-disc + DDR5-DIMM claims do not hold — and the strongest version of WritePhi-2 is the one that drops them.

Sources are cited inline in the five underlying thread reports (SNSPD operating temperatures, KLM 2/27 success bound, polymer dn/dT values, SiN loss records, CXL/PCIe PHY specifications, Optane DDR-T precedent, photonic-coupling yield data). This memo is the adversarial view by design; a fair overall judgement weighs it against the honest maturity framing already in STATUS.md.

Session Log — 2026-08-05

Everything done in this session, plus the technical learnings worth keeping. Two big threads: store fixes and building the WritePhi-2 explainer video (from script to homepage).

1. Store — WritePhi-2 SKUs completed

Problem: writephi-2.html (category 3416) advertised more SKUs than existed.

Added 5 missing SKUs (entity_ids 32884–32888), matched to the existing 10 WP2-* products (simple type, attr set 4, visibility 4, manage_stock=0 per the digital-product rule, website 1, url_rewrite at store 1):

Downloads: attached the package zip to WP2-BUNDLE + WP2-PDEPO (converted them to downloadable), verified end-to-end 2/2 with store_manager/verify_downloads.py. Two pre-existing bugs fixed along the way:

catalog/downloadable/order_item_status was 0 (invalid) → set to 9 (Invoiced). It was making every downloadable link instant-expire.
Downloadable files must live under .../pub/media/downloadable/files/links/<link_file>, NOT .../files/<link_file>. Magento's Link::getBasePath() hardcodes the /links/ segment.

Product images (5 new SKUs): generated photoreal shots (ComfyUI, matched sibling style), uploaded to pub/media/catalog/product/w/p/. Gotcha: setting the image/small_image/thumbnail EAV attrs is NOT enough — Magento's product view reads the media_gallery tables. Had to insert rows into catalog_product_entity_media_gallery + _value_to_entity + _value. See scratchpad/add_media_gallery.py.

Docs updated: STORE_LISTING.md (full SKU price table), STATUS.md, WRITEPHI2_CONCEPT.md.

2. Store — theme, catalog, navigation

Theme reverted to stock Luma (kept only the mega-menu). Key realization: the store was already on Magento/luma; its custom look came from CSS/JS injected via the three design/head/includes blobs (configs 40/930/1020) + nginx sub_filter. Stripped everything except the cgb-nav-v1 mega-menu span. Backups: DB table cri_bak_head_includes_20260805_062745, cri-one.conf.bak-themerevert-20260805-062745.
"All Products" category (id 3419, /store/catalog.html) — all 601 sellable products EXCEPT the mass families (AutoPhi Collections 3017, Elemental Medicine 317).
Mega-menu: added "All Products", "WritePhi", "WritePhi Devices" to the Shop group's GROUPS array (the menu lists top-level cats explicitly; it doesn't auto-add new ones).
Footer + Sitemap: added a 5-column footer nav to design/footer/absolute_footer and a Sitemap CMS page at /store/sitemap.

3. The site gate (important, corrected)

The nginx lockdown gate is DISABLED (commented out since 2026-08-03). The live gate is a Magento module Custom\LockdownGate\Observer\GateObserver that redirects logged-out visitors to login. No cookie bypass — cri_gate is only set, never checked. To view store pages, log in as test-download@cri-one.com / TestDL9999!. All real work is via root SSH, which the gate never touches.

4. WritePhi-2 explainer video — the main build

Pipeline, all local + free, all scripts in 79-writephi-2/video/:

Story → VIDEO_SCRIPT.md (9-scene concept-pitch, ~1:45) + STORYBOARD.md (photoreal shot list, per-scene prompts).

Narration (VO) → Piper TTS (piper-tts from pip, voice en_US-ryan-high, ~121 MB). video/generate_vo.py → 9 per-scene WAVs + writephi2_VO_full.mp3. 1:44 total.

Keyframes → ComfyUI (C:\ai\comfy), RealVisXL V5 + sdxl_lightning_4step LoRA, 4-step. video/generate_keyframe.py / generate_all_keyframes.py. 9 photoreal stills in ~38s. Weak ones (3/4/9) regenerated via fix_weak_frames.py (stronger text-suppression negatives; the disc-in-DIMM cutaway is not achievable via txt2img — used a glowing-chip stand-in).

Generative motion → Stable Video Diffusion (svd_xt.safetensors, 9.5 GB, downloaded to comfy checkpoints). video/svd_motion.py / svd_batch.py → 25-frame img2vid clip per scene (~2.7 min each on the A10M).

Assembly → video/assemble_svd_video.py — each SVD clip is boomeranged + looped to fill its VO scene duration, crossfaded, VO laid on top → writephi2_cut2_svd.mp4 (1:45, 1080p). (assemble_video.py is the earlier Ken-Burns-on-stills cut → writephi2_cut1.mp4.)

Homepage → web-optimized (build_homepage_intro.py, faststart) + VTT subtitles from the VO timings → deployed as /static/intro-2026-08-05.mp4 (+ .vtt), rewired index.html. The homepage intro overlay auto-plays muted with subtitles, has a "Sound on" + "Skip" button. Old 10s intro backed up.

ComfyUI rig — the hard-won learnings (READ before next video job)

GPU: NVIDIA A10M, compute 8.6 (Ampere), 19 GB. RealVisXL/SVD (fp16) work; fp8 models do NOT (LTX-2 19B is fp8 → CUDA error: operation not supported; fp8 needs Ada/Hopper 8.9+). LTX-2 is a dead end on this box.
MUST launch ComfyUI with --disable-cuda-malloc or image/video ops fail with cudaErrorNotSupported. The stock run_nvidia_gpu.bat also has --gpu-only which forbids CPU offload → OOM on big models. Best launch for video: python -s ComfyUI\main.py --windows-standalone-build --disable-cuda-malloc --lowvram --port 8188.
Models load only from the folder the loader expects: CheckpointLoaderSimple/ImageOnlyCheckpointLoader read models/checkpoints/ only. Hard-link models in from diffusion_models/ if needed (New-Item -ItemType HardLink).
Drive ComfyUI headless via its HTTP API: POST graph to /prompt, poll /history/<id>, read node schemas from /object_info. All the video/*.py scripts do this.
SVD specifics: native 1024×576, 25 frames, motion_bucket_id ~45 (subtle) … 110 (strong), fp16, fits 19 GB fine. --disable-cuda-malloc required.

Re-run cheatsheet

cd 79-writephi-2/video
python generate_vo.py                 # VO
python generate_all_keyframes.py      # stills (needs comfy running)
python svd_batch.py                   # motion clips
python assemble_svd_video.py          # final cut
python build_homepage_intro.py        # web mp4 + vtt

ComfyUI launch (video): cd C:\ai\comfy && .\python_embeded\python.exe -s ComfyUI\main.py --windows-standalone-build --disable-cuda-malloc --lowvram --port 8188

SSH/DB: root@192.250.226.230 (creds in special\manager\store_manager\.env); DB mysql -u magento -p… mage165 (tables prefixed mgcx_).

WritePhi-2 — Hardware Specification

Project 79 · cri-one.com portfolio · 2026-08-04

Working draft — Christopher Gabriel Brown, inventor

Scope

This document specifies the WritePhi-2 DIMM hardware, the coupling of the WritePhi Q-Blank disc(s) to the host interface, the CXL 3.0 protocol shape, the Q-Blank recording-chemistry surface, and the thermal/mechanical envelope. The WritePhi-Q language and its compiler are specified separately in WRITEPHI_Q_LANGUAGE.md. The upstream WritePhi Writer, Dicer, and .wpprog format are specified in Project 57.

The WPQ-DIMM package

Mechanical envelope

Form factor: JEDEC DDR5 UDIMM, 288-pin edge, 133.35 mm × 32 mm, 1.2 mm PCB thickness at edge.
Height including heat spreader: 34.0 mm (standard tall DIMM). Fits any DDR5 tall-DIMM chassis.
Weight: target ≤ 45 g for the 1-disc variant, ≤ 75 g for the 4-disc stack.
Mating socket: any JEDEC-compliant DDR5 DIMM socket. Retention is standard cam-lever.

Electrical envelope

Interface: CXL 3.0 memory-semantic (Type-2 device: memory + accelerator).
Signaling on the DDR5 edge: CXL-over-DDR5 (as supported by Intel Sapphire Rapids and later, AMD EPYC 9004+, and CXL 3.0 memory expansion sockets). Boards that do not natively route CXL over the DDR5 socket require a shim adapter (see § Compatibility).
Power: ≤ 15 W total DIMM budget under peak workload. Idle ≤ 1 W. Sourced from the DDR5 12 V rail and the 3.3 V I/O rail as JEDEC specifies.
Thermal: target junction ≤ 85 °C at 15 W with standard tall-DIMM heat spreader in a chassis with 100 LFM airflow. No cryostat, no active cooling.

Density variants at launch

Higher densities are available via the WPQ-Bed multi-DIMM chassis (see Project 79 concept doc § SKU family).

The disc-to-electrical bridge

The WPQ-DIMM contains one to four written Q-Blanks stacked horizontally on a machined-aluminum mounting frame. Each disc's photonic surface must be coupled to the CXL front end's control channel and read channel. The path we commit to:

Path A — edge coupling via V-groove fibre array

The WritePhi Dicer (Project 57 SKU) cuts each Q-Blank to a 120 mm × approx. 4 mm strip that captures the tile grid. A polishing pass finishes the coupling edge.
The polished edge butt-couples into a silicon V-groove fibre array bonded to the bridge PCB. Fibre pitch is 127 µm (standard).
Alignment is passive per fiducials the WritePhi Writer inscribes during the write pass.
Insertion loss target: ≤ 2 dB per interface, verified during factory outgoing inspection.

Path B (surface grating coupling) is deferred to a WPQ-DIMM-Lite variant if edge coupling proves too demanding at volume.

The photonic-electrical bridge board

A small daughter PCB (approx. 50 mm × 20 mm) sits between the disc stack and the DIMM edge connector. Contains:

CXL 3.0 controller — commodity silicon (Astera Labs Leo, Marvell Structera, or Microchip PM8000-series). Presents CXL Type-2 to the host.
Photonic transceiver — light-source + drive electronics for the disc's classical control channel; single-photon detector array for the disc's read channel. Target: 12-channel WDM (wavelength-division multiplexing) at 1550 nm ± 20 nm.
Classical control processor — small CPU that runs classical operations dispatched by Tier-3 WritePhi-Q programs (transpose, softmax, activation functions). Provisional choice: quad-core ARM Cortex-A55 at 1.2 GHz. Alternate: a stripped-down AutoPhi Modern soft core if the Project 2 team wants the alignment.
Thermal management — passive heat-spreader interface only; no active cooling.

The Q-Blank recording chemistry

The WritePhi Q-Blank shares the 120 mm × 1.2 mm polycarbonate envelope of the WritePhi-1 blank (invention 1448) but uses a distinct recording chemistry optimized for photonic quantum operation.

Requirements the chemistry must meet

1. Sub-diffraction-limit feature resolution. Waveguide widths at 250 nm and phase-shifter alignment tolerances at ± 30 nm require sub-405 nm-diffraction-limit writing. The WritePhi Writer's optical writing is expected to achieve this via [chemistry-defined non-linear response — spec TBD].

2. Low propagation loss at 1550 nm target wavelength: ≤ 3 dB / cm.

3. Thermo-optic stability over the 0-85 °C operating range: refractive index drift ≤ 1 × 10⁻⁴ / K.

4. Photostability under continuous operation for target 10 000 hours. No visible degradation of features or coupling.

5. Compatibility with dicing — the WritePhi Dicer must cleanly cut the substrate without inducing edge damage in the photonic layer within 5 µm of the cut.

Candidate chemistries (not yet selected)

Hybrid organic-inorganic photoresists (Ormocer family, TPP-hardened variants).
Amorphous chalcogenide phase-change layers (Ge₂Sb₂Te₅ family).
Photorefractive nanocomposites (Zr-containing sol-gel).

Selection depends on write-laser wavelength and pulse-shape compatibility with the WritePhi Writer. Candidate inventor-record entry: 79-E — WritePhi Q-Blank recording chemistry, TBD chemistry chosen.

CXL 3.0 protocol shape

The WPQ-DIMM enumerates as a CXL 3.0 Type-2 device with the following advertised features:

CXL.mem — memory-semantic access to the DIMM's tile address space. Host maps the DIMM into its own address space. Reads and writes at CXL.mem addresses map to WritePhi-Q operations.
CXL.cache — optional coherent caching if the host supports it. Not required for correctness.
CXL.io — control-plane, used for enumeration, firmware update, telemetry.

Address-space model

The DIMM's address space is divided into tile regions, each corresponding to one photonic quantum tile on the disc. Regions are memory-mapped at DIMM-relative offsets. Each region has three sub-regions:

A single Tier-3 program lowers to writes/reads across one or more tile regions. The CXL front end serializes host requests to match the tile availability schedule.

Latency shape

Small operations (single-tile matmul, single-tile FFT): target ≤ 5 µs end-to-end (host issue → compute → result available).
Large operations (multi-tile attention block): target ≤ 100 µs.
Firmware update / stdlib reload: offline, requires DIMM power cycle.

The write / assembly flow

At the factory:

1. Design ingest. The buyer supplies .wpprog files (from wpqc build) OR selects designs from the WPQ-Library.

2. Q-Blank write. The WritePhi Writer (Project 57 SKU) inscribes each .wpprog onto a Q-Blank.

3. Dicing. The WritePhi Dicer cuts each written Q-Blank to the DIMM tile-strip form factor and polishes the coupling edge.

4. Stack assembly. One to four discs are stacked on the aluminum mounting frame.

5. Bridge PCB assembly. The bridge PCB is populated (CXL controller, photonic transceiver, classical CPU, passives) using standard SMT.

6. Coupling. The polished disc edges are aligned and bonded to the V-groove fibre array on the bridge PCB.

7. DIMM assembly. The bridge PCB + disc-stack subassembly is bonded to the DDR5 edge-connector board. Heat spreader is attached.

8. Test. Every DIMM undergoes automated per-tile bring-up: each written tile is exercised via a golden CXL sequence, results compared to expected outputs.

9. Ship. Passed DIMMs are labeled, packaged, and shipped.

All steps use commodity or existing-WritePhi tooling. No cleanroom for the DIMM assembly; the disc write step itself is done in the WritePhi Writer's own enclosed optical bay.

Compatibility

Boards that natively route CXL over DDR5

Intel Sapphire Rapids + Emerald Rapids server platforms
Intel Granite Rapids / Sierra Forest (upcoming)
AMD EPYC 9004 (Genoa) + EPYC 9005 (Turin)
Ampere AmpereOne (CXL 2.0; WPQ-DIMM falls back to CXL 2.0 features on these)
Any CXL 3.0 memory-expansion socket on future platforms

Boards without native CXL-over-DDR5

Ship with a CXL-shim adapter card — a small PCIe 5.0 x8 card that receives a WPQ-DIMM in a horizontal socket and bridges to the host over PCIe. Loses the DIMM-slot convenience but preserves the compute model. The shim is a WPQ-Bed-derivative SKU.

Firmware update

The DIMM's CXL front-end firmware and the classical control processor's firmware are updatable via CXL.io. Signed updates only; no unsigned code accepted.

Firmware update does not update the written photonic layer on the disc. The disc is fixed at write time. To change the disc's design, the buyer either swaps the DIMM or (for buyers who own a WritePhi Writer) writes a new Q-Blank and reassembles.

Priority + IP

The specifications in this document are candidate inventor-record entries at priority 2026-08-04:

Entry 79-F — WPQ-DIMM package (DDR5 edge + CXL 3.0 electrical + disc stack).
Entry 79-G — Photonic-electrical bridge board.
Entry 79-H — Disc-to-fibre edge-coupling via post-write polishing pass and fiducial-aligned V-groove array.

Underlying WritePhi-1 platform IP (inventions 1443-1462) is referenced and re-used.

Maturity

All performance numbers are design targets, not measured guarantees. No prototype WPQ-DIMM exists. No Q-Blank recording chemistry has been fabricated and characterized. The CXL controller silicon, ARM CPU, photonic transceiver, and disc envelope are commodity or existing-portfolio components; the WritePhi-2 contribution is the integration.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Available exclusively to companies incorporated, headquartered, and primarily operating in the United States. USD only. Email and postal mail only.

WritePhi-2 — Status Report

Project 79 · cri-one.com portfolio · 2026-08-04

Working draft — Christopher Gabriel Brown, inventor

Summary

Maturity: Concept + designed. All performance numbers in the WritePhi-2 documentation are design targets, not measured guarantees. No prototype exists at any layer. Priority date is 2026-08-04.

Store listing: Live. The writephi-2.html category on cri-one.com carries the full 15-SKU catalog (see STORE_LISTING.md for the price table and every SKU code). Category ID 3416 on the store.

Below is a subsystem-by-subsystem accounting.

Language + toolchain

Hardware — the DIMM

The written disc

Software — inheritance from WritePhi-1

CXL protocol integration

Priority date + IP status

Project 79 concept + language + hardware spec: written 2026-08-04. This is the operative priority date for the entries below.
Candidate inventor-record entries under Project 79:
79-A: WritePhi-Q language design (three-tier structure + lowering discipline).
79-B: PQIR intermediate representation.
79-C: Compile-time photonic-realizability type system.
79-D: Stdlib versioning + reproducibility manifest.
79-E: WritePhi Q-Blank recording chemistry (TBD once chemistry selected).
79-F: WPQ-DIMM package.
79-G: Photonic-electrical bridge board.
79-H: Disc-to-fibre edge-coupling method.
Upstream inventions carried forward: 1443-1462 from WritePhi-1 (Project 57), plus 1448 (Path 1 blank chemistry family) and 1451 (object writer).

What blocks a working prototype

Roughly in order of severity:

1. Q-Blank chemistry selection + fabrication. Everything else waits on this. Without a written Q-Blank, there's no photonic circuit to test.

2. wpqc compiler front end. A minimal front-end that parses WritePhi-Q, emits PQIR, and calls into a placeholder layout pass is achievable in ~two weeks of focused work.

3. PQIR reference emitter + a hand-written PQIR test case. Needed to exercise the layout pass against the WritePhi-1 SDK before the compiler is complete.

4. Bridge PCB schematic + fabrication. Buyer-scope PCB work with commodity parts.

5. Photonic transceiver integration + fibre-coupling bring-up. Bench work with a commodity photonic-packaging vendor.

6. First-DIMM assembly + CXL bring-up. Once (1)–(5) exist, first-DIMM bring-up is measured in days.

None of (1)–(6) is scientifically speculative. All are engineering integration of known techniques with a new recording chemistry and a new language layer.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

WritePhi-2 — Store Listing

Product family: WritePhi-2 (Project 79)

Category: Semiconductor & Fabrication — Photonic Quantum

Priority: 2026-08-04

Title

WritePhi-2 — Photonic Quantum Compute in a Memory Slot

One-line

The photonic quantum compute platform, delivered as a CXL 3.0 memory-semantic DIMM.

Price

$10,000,000 (USD) — full WritePhi-2 Design + Product License Package. One-time payment. Other structures negotiable: installments (3-60 months), milestone-based, royalty, or revenue share. No IP transfer. All underlying platform IP (inventions 1443-1462 from WritePhi-1 and Project 79 entries 79-A through 79-H) is retained by the inventor. What the buyer receives is a design + product license that includes worldwide commercialization rights for the manufactured WPQ-DIMMs.

The pitch (short)

WritePhi-2 puts a photonic quantum compute engine into a standard DDR5 DIMM socket. Developers write designs in WritePhi-Q, a three-tier language that lowers cleanly from application-level compute-in-memory calls all the way down to waveguide-level photonic layouts. The compiled design is inscribed onto a WritePhi Q-Blank (a Blu-ray-envelope photonic substrate) by the WritePhi Writer, packaged into a WPQ-DIMM, and plugged into any CXL 3.0-capable board.

No cryostat. No optical bench. No custom carrier. Just a DIMM.

The pitch (long)

Every prior photonic quantum system has required a cryogenic dilution refrigerator, an optical bench the size of a car, or both. WritePhi-2 breaks that pattern by inheriting the WritePhi platform (Project 57): kitchen-table chip fabrication using an optically-written Blu-ray-envelope substrate as the physical chip. WritePhi-2 extends that platform in three specific ways:

1. A photonic quantum recording chemistry (Q-Blank) — same disc envelope, new chemistry that produces waveguide, resonator, phase-shifter, and single-photon-source elements as it's written.

2. A DIMM package with CXL 3.0 semantics — the written disc(s) are diced, edge-polished, coupled to a small bridge PCB carrying a CXL controller + photonic transceiver + classical control CPU, and assembled into a JEDEC DDR5 DIMM. Plug it into any Sapphire Rapids-class or later server board; the host sees a CXL 3.0 Type-2 memory-semantic device.

3. WritePhi-Q, a three-tier language — Tier 1 for photonic engineers who want to draw the waveguides themselves; Tier 2 for quantum algorithm developers thinking in gates; Tier 3 for application developers who just want quantum-accelerated compute-in-memory. All three tiers lower to the same intermediate representation and produce a single .wpprog write program.

The result: a shippable, ordering, standard-slot photonic quantum accelerator that any team with a CXL-capable server can drop into their infrastructure.

Who buys WritePhi-2

What's in the box (bundle)

The WritePhi-2 bundle (WP2-BUNDLE, $10,000,000), at the top-level price, includes:

1. WritePhi-Q SDK — compiler (wpqc), simulator (wpqsim), Language Server (wpq-lsp), inspection tools (wpq-inspect), and reference examples.

2. WPQ-DIMM-1 starter set — three WPQ-DIMM-1 devices pre-loaded with the reference-example designs, ready to plug in.

3. WPQ-Blank M-pack — twenty writable Q-Blanks for buyer authoring (requires WritePhi Writer from Project 57, sold separately or bundled).

4. WPQ-Library base subscription — access to wpq-stdlib core algorithm and CIM tile entries; twelve-month term.

5. Full engineering documentation — CONCEPT.md, WRITEPHI_Q_LANGUAGE.md, SPEC.md, STATUS.md, PLAYBOOK.md, HANDOFF.md.

SKU catalog

Every SKU below is live on the store in category writephi-2.html. Prices are USD, one-time except where noted.

Package tiers

Reference DIMMs (evaluation articles)

Scale-up chassis (WPQ-Bed)

Software + consumables + adapters

What is NOT included

The WritePhi Writer, Dicer, or Server Bed (Project 57 SKUs). Sold separately.
Any AutoPhi ISA or classical AutoPhi chip family (Projects 2, 18, 21, 23, 24).
A cryostat. WritePhi-2 does not need one.

Package type

Design + Product License Package. Buyer receives complete engineering package plus worldwide commercialization rights for the manufactured DIMMs. All underlying platform IP (inventions 1443-1462 and Project 79 entries 79-A through 79-H) is retained by the inventor.

Terms

Available exclusively to companies incorporated, headquartered, and primarily operating in the United States.
USD only.
Email and postal mail only. No phone.
Contact: crioneaka@outlook.com · crioneaka@outlook.com
Postal: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Maturity — honest report

Concept + designed. The concept document, WritePhi-Q language specification, and SPEC.md are on file at priority date 2026-08-04. What is not yet in hand: the Q-Blank recording chemistry (candidate materials identified, none selected or characterized), a working WritePhi-Q compiler, a working WPQ-DIMM prototype, any measured performance data. All numbers in this listing are design targets derived from the engineering record — not measured guarantees. See STATUS.md for subsystem-by-subsystem detail.

Christopher Gabriel Brown — Inventor · Author · Visionary

This archive contains 24 documents; 18 more beyond this preview. The complete folder ships as the product.

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