58-writephi-devices

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Asset valuation: $14,000,000,000. Project 58 · cri-one.com portfolio · 2026-07-04 Windows-compatible computational storage device and computational accelerator, built on the WritePhi platform (Project 57). One physical device, two Windows-driver personas.

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Valuation

Generous asset valuation: $14,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

WritePhi Devices

Project 58 · cri-one.com portfolio · 2026-07-04

> Windows-compatible computational storage device and computational accelerator, built on the WritePhi platform (Project 57). One physical device, two Windows-driver personas.

What this is

Two Windows-plug-in products sharing one silicon platform:

1. WPD-CSD — Computational Storage Device. Presents as a standard NVMe drive to Windows. Runs compute jobs inside the drive against the data at rest (NVMe 2.0 Computational Programs command set). Replaces a slot of SSD storage with a slot of "storage that runs your code."

2. WPD-ACCEL — Computational Accelerator. Presents as a PCIe compute endpoint via a KMDF driver. Runs offloaded workloads (crypto, DSP, small-model inference) on a fleet of WritePhi dies.

Same PCIe 5.0 x8 add-in card. Different firmware. Different Windows driver. Buyer picks the persona at purchase.

The productization step at the package level

Project 58 introduces the V2 package — a redesigned die-carrier architecture that replaces WritePhi-PKG-M / -H (Project 57) for volume manufacturing:

Inset PCB carrier — small FR-4 PCB with WritePhi die bonded to top-side pads via low-temp anisotropic conductive adhesive (ACA), pads on the bottom for socket mating
Pinned socket — socket with upright pins that the inset PCB drops onto
Cut marks on the die — DICER cuts scribe lines + alignment fiducials + IC tabs during the same pass that produces the die outline
Socket-to-IC tabs — physical tabs on the die/carrier mate to socket recesses for fool-proof orientation and shear retention
No solder reflow anywhere on the die — polycarbonate die is bonded via ACA (< 100 °C), carrier PCB is soldered separately to the host

The V2 package makes WritePhi dies PCB-manufacturable at any PCB house and socketable in a standard pinned socket, opening volume manufacturing that the cam-lever contact-on-die scheme (Project 57 rev 0.5) does not support at production sample count.

Read in this order

1. WPD_CONCEPT.md — the vision, why both personas share one card

2. PRODUCT_BRIEF.md — one-page buyer brief

3. SPEC.md — top-level device specification

4. hardware/V2_PACKAGE_SPEC.md — V2 package overview

5. hardware/INSET_PCB_SPEC.md — die-carrier PCB

6. hardware/PINNED_SOCKET_SPEC.md — the new socket

7. hardware/DIE_CUT_MARKS_SPEC.md — cut marks + tabs the DICER cuts

8. hardware/WPD_ACCEL_CARD/ — reference add-in card schematic

9. hardware/INSET_PCB_M/ — reference inset PCB schematic (M-grade)

10. windows/README.md — Windows driver stack

11. firmware/README.md — on-device firmware

12. STATUS.md — honest maturity report

13. LICENSE.md — what conveys, what is retained

14. HANDOFF.md — session state and pickup queue

Cross-reference to Project 57 (WritePhi)

Project 58 depends on Project 57 for:

The WRITEPHI-WRITER (writes the dies used in the V2 package)
The WRITEPHI-DICER (dices dies + cuts the new tab / fiducial features)
The WRITEPHI-BLANK family (M-grade and H-grade substrates)
The WRITEPHI-LIB design library (source of the IC designs that get written)
The shared _factory.py for KiCad 10 schematic generation

The two projects are arms-length per portfolio firewall — Project 58 is a distinct product family with its own SPECs, sockets, drivers, and revenue. It licenses Project 57's writer/dicer/blank output at portfolio-family rates.

License terms (headline)

Buyer receives the engineering package + worldwide commercialization rights.
All patents, prosecution rights, enforcement rights, and trademarks retained by the inventor.
NOT a patent license.
USA-only, USD-only, email + postal mail only.
Full terms in LICENSE.md.

Price

USD $1,000,000,000,000 standalone. Included in All In One (20T) — the complete cri-one.com portfolio acquisition — at no extra charge.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

WritePhi Devices — Handoff (pickup queue)

Project 58 · cri-one.com portfolio · 2026-07-04 · Revision 0.1

Shipped in the initial build (2026-07-04)

Full initial engineering package. New project directory adjacent to Project 57 (57-chip-write); imports shared factory + hardware conventions.

Top-level docs:

README.md, WPD_CONCEPT.md, PRODUCT_BRIEF.md, SPEC.md
LICENSE.md, STATUS.md, CONTACT_INFO.txt, MANIFEST.json, HANDOFF.md

V2 package specs (the productization innovation):

hardware/V2_PACKAGE_SPEC.md — overview
hardware/INSET_PCB_SPEC.md — die-carrier PCB with bottom pads + tab recesses
hardware/PINNED_SOCKET_SPEC.md — spring-loaded pin block + cam-lever cap
hardware/DIE_CUT_MARKS_SPEC.md — new DICER geometry (scribe lines + fiducials + IC tabs)

Reference schematics:

hardware/WPD_ACCEL_CARD/ — PCIe 5.0 x8 accelerator/CSD card
hardware/INSET_PCB_M/ — M-grade inset PCB carrier

Windows + firmware overviews:

windows/README.md — driver stack overview
windows/nvme_csd_driver/README.md — NVMe class driver plan for CSD persona
windows/kmdf_accel_driver/README.md — KMDF driver plan for ACCEL persona
windows/userspace/README.md — user-mode SDK plan
firmware/device_firmware/README.md — on-device firmware overview

Pickup queue

Ordered by leverage.

1. INSET_PCB_H reference schematic (H-grade variant)

M-grade inset PCB is drafted. H-grade variant is a straightforward clone with 168 top-side pads + 168 bottom-side pads at 0.5 / 0.8 mm pitch respectively.
Adds hardware/INSET_PCB_H/ — same shape as INSET_PCB_M/.

2. Firmware persona milestones (CSD + ACCEL runnable)

CSD persona: firmware/device_firmware/nvme_csd/ — NVMe 2.0 admin queue enumeration + minimal identify controller / identify namespace / read / write / compute submit stubs.
ACCEL persona: firmware/device_firmware/kmdf_accel/ — command / completion queue + minimal job submit / result poll stubs.
Both run on AutoPhi 1Z-Edge bus master (portfolio-native compute).

3. Windows driver stub milestones

NVMe class driver: no work needed — Windows 11 24H2+ ships stornvme.sys that handles NVMe 2.0.
KMDF driver stub: windows/kmdf_accel_driver/wpd_accel.sys — INF + KMDF template + IOCTL definitions.
User-mode SDK DLL: windows/userspace/wpd_sdk.dll — command-queue front-end.

4. WPD-ACCEL-CARD-8 (full-length PCIe 5.0 x16)

8-socket variant of the reference card. Same architecture, double the socket count.
Adds hardware/WPD_ACCEL_CARD_8/.

5. WPD-CSD as a U.2 / M.2 form factor

The base WPD-CSD is a PCIe x8 AIC. A U.2 (2.5" bay) and M.2 (22110) variant would open a larger consumer market.
Adds hardware/WPD_CSD_U2/ and hardware/WPD_CSD_M2/.

6. Store product page + product bundle

Store listing at cri-one.com/store/wpd.html (or split into /wpd-csd.html + /wpd-accel.html)
Rebuild bundle.py at Project 58 root to ship a Windows-buyer package
Add to total-all-in-one.html humdinger row (project count 57 → 58)

7. WritePhi Devices-specific USPTO utility patent

Anchor: V2 package + inset PCB + socket-to-IC tabs + cut-mark method.
2017-11-24 printed publication is the operative § 102(a)(1) anchor for the WritePhi-family foundations; V2 package is a novelty step over the Project 57 PKG-M/-H disclosure.
Cost: standard USPTO fees. Per feedback-money-constrained-no-unfunded-spends, evaluate USPTO Pro Bono referral before out-of-pocket spend.

Cross-references to Project 57

Project 58 depends on Project 57 for the writer/dicer/blank family + shared _factory.py. The DICER-CTRL rev in Project 57 is capable of the writer geometry; new cut-mark firmware for the V2 package is a Project 57 firmware upgrade on that pickup queue.

Contact

Christopher Gabriel Brown

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

WritePhi Devices — Product Brief (one page)

Project 58 · cri-one.com portfolio · 2026-07-04

The problem

The WritePhi platform (Project 57) proved chips can be written in a kitchen. But every WritePhi buyer to date has to bring up their own PCB layout, source a socket body, get the Windows driver working, and pass FCC / UL / CE cert. That is a heavy lift for prosumer + enterprise + OEM buyers who want a plug-and-play PCIe card on Windows and are unwilling to become a chip-packaging house to get there.

The invention

WritePhi Devices — one physical PCIe 5.0 x8 add-in card, two Windows-driver personas:

WPD-CSD — Computational Storage Device. NVMe 2.0 with the Computational Programs command set. Windows sees an SSD; applications can run code against the data at rest.
WPD-ACCEL — Computational Accelerator. KMDF-driver compute endpoint. Windows sees an accelerator; applications submit compute jobs.

Same card. Different firmware. Different driver skin. Buyer picks at purchase.

Both personas ride on the V2 package — a redesigned die-carrier architecture that makes WritePhi dies volume-manufacturable and socketable at any standard PCB / socket vendor.

The four V2 innovations

1. Inset PCB carrier — small FR-4 PCB with the WritePhi die bonded via anisotropic conductive adhesive (< 100 °C, below polycarbonate softening point)

2. Cut marks on the die — DICER cuts scribe lines + fiducials + IC tabs during the same pass as die outline

3. Socket-to-IC tabs — physical tabs on the die + matching recesses on the carrier prevent shear + enforce orientation

4. Pinned socket — commodity spring-loaded pin block on the host PCB accepts the inset PCB

The buyer's advantage

Windows-native. No custom driver stack. NVMe class driver ships with Windows; KMDF is a documented Microsoft framework.
PCIe 5.0 x8 drop-in. Any modern Intel / AMD / Xeon / EPYC workstation or server host.
Two personas, one card. Buyers can start with CSD (storage-with-compute) and re-flash to accelerator persona for the same silicon investment.
Volume-manufacturable. V2 package uses standard PCB fab + commodity sockets + industry-standard SMT pick-and-place. No custom-injection-molded socket bodies.
User-serviceable in the field. Individual dies are replaceable via the pinned socket without PCB rework. Same productization advantage as Project 57 PKG-M / -H, at production sample count.

What the buyer receives

One-line SPEC + product brief + playbook (SPEC.md, WPD_CONCEPT.md, PLAYBOOK.md)
V2 package specification: inset PCB + pinned socket + cut marks + tabs (hardware/*_SPEC.md)
Reference PCIe 5.0 x8 add-in card schematic + BOM (hardware/WPD_ACCEL_CARD/)
Reference inset PCB schematic + BOM (hardware/INSET_PCB_M/)
Windows driver stack overview (windows/)
On-device firmware overview (firmware/)
Worldwide commercialization rights

What the buyer does NOT receive

The underlying patents and inventor record are retained by the inventor. V2 package + inset PCB + socket-to-IC tabs are anchored to invention 1453 (many optical circuit objects on a server bed of input ports) and future WritePhi-Devices-specific claims. This is a documentation + commercialization-rights transaction, not a patent license or assignment.

Maturity — honest report

Designed. V2 package, inset PCB, pinned socket, cut marks / tabs — spec'd on file. One reference add-in card schematic + one inset PCB reference schematic drafted. Windows-driver personas outlined. No prototype. All performance numbers are design targets, not measured guarantees. See STATUS.md.

Buyer scope — what YOU do

The blueprints delivered here are COMPLETE engineering packages at the inventor's ceiling: V2 package SPECs + drafted schematics + Windows driver plans + firmware overview. They are not partial drafts. But an engineering package is not a finished shipping Windows device — the following are yours to execute, at whatever tier you purchase:

PCB layout of the WPD-ACCEL-CARD reference schematic + INSET-PCB-M reference schematic (both ship as ERC-clean KiCad 10 .kicad_sch; buyer routes copper on Megtron 6 or MEGTRON GX for PCIe 5.0 lane compliance)
Tape-out of any silicon named — AutoPhi 1Z-Edge bus master, WritePhi die substrate
ACA bond process qualification — anisotropic conductive adhesive bond of die to inset PCB at ≤ 100 °C, cure schedule and pressure characterized at production sample count
Pinned socket sourcing — Yamaichi IC189 series / Aries Correct-8 / Ironwood HiPer / Enplas ORDER at buyer's chosen pitch and mating-cycle grade
Windows driver development — the driver plans delivered here (NVMe class extension for CSD persona + KMDF driver for ACCEL persona + user-mode SDK) are architectural specifications; buyer writes the actual wpd_accel.sys C source and INF file
Windows driver signing — buyer sets up a WHCP (Windows Hardware Compatibility Program) partner account and submits their driver package through it (attestation signing or full signing depending on volume)
Windows HLK certification — Windows Hardware Lab Kit tests for Storage Adapter class (CSD persona) or System class (ACCEL persona), submitted with the signed driver
NVMe SIG certification — CSD persona undergoes NVMe compliance test at NVM Express interop workshops; opcode assignment for the Computational Programs command set (reference: 0xE0-0xE2 admin, 0xD8-0xDA I/O) is negotiated with NVMe SIG
PCI-SIG PCIe 5.0 compliance — Buyer certifies through PCI-SIG for the finished card
Firmware bring-up beyond overview — buyer implements the shared/ + csd/ + accel/ modules described in firmware/device_firmware/README.md
Certification — FCC Part 15 Class B, CE, UL 60950-1 / IEC 62368-1 for the consumer / commercial market
Environmental testing at production sample count
Trademark registration in the buyer's market (buyer's own marks; WPD-CSD / WPD-ACCEL / V2 Package marks retained except at OEM Engineering-Package Acquisition tier)
Marketing, sales, distribution, warranty, and support for the finished Windows-plug-in devices the buyer ships

Everything above is standard commercial-hardware bring-up work for a Windows-plug-in PCIe accelerator or storage device. The engineering package makes it faster — V2 package specs are complete, reference schematics are ERC-clean, driver plans are architected, firmware overview is on file — but does not eliminate it.

Pricing — sellable-parts structure

The store sells downloadable blueprints, not physical hardware. Buyer picks the specific blueprint(s) they want. Each sub-blueprint ships as its own self-contained zip.

Study tier — four per-part blueprints at $99 each

Personal + educational only; no commercial rights.

Full + Commercial + OEM tiers

Aligned with Chris's Licensed Research pricing playbook ($99–$12.75M per SKU family, per portfolio precedent).

What conveys per LICENSE.md: engineering documentation + commercialization rights at the license breadth of the chosen tier. What does NOT convey at any tier: the underlying patents, prosecution rights, or enforcement rights — those are retained by the inventor. This is a documentation + commercialization-rights transaction. NOT a patent license and NOT a patent assignment.

Structure — asset purchase, exclusive license, joint venture, revenue share, milestone-based, strategic acquisition — can be tailored at any tier above Study.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

USA-only, USD-only, email + postal mail only.

WritePhi Devices — Technical Specification

Project 58 · cri-one.com portfolio · 2026-07-04 · Revision 0.1

1. Scope

Two Windows-native products sharing one physical PCIe 5.0 x8 add-in card:

WPD-CSD — Computational Storage Device (NVMe 2.0 + Computational Programs)
WPD-ACCEL — Computational Accelerator (KMDF-driver compute endpoint)

Same silicon (WritePhi dies, M-grade or H-grade, per Project 57). Different firmware. Different Windows driver.

Package deliverable: SPEC + BOM outline + LAYOUT_HINT for the card, the inset PCB, and the pinned socket. Firmware skeleton per persona. Windows driver plan per persona. All performance figures are design targets derived from the engineering record, not measured guarantees.

2. System architecture

   Windows host                         Card (WPD-DEVICE)
   +-----------+                        +------------------------------+
   |           |    PCIe 5.0 x8         |  Host bridge (AutoPhi 1Z-Edge)|
   |  NVMe or  |<---------------------->|  Persona firmware             |
   |  KMDF     |                        |  (CSD or ACCEL)               |
   |  driver   |                        +------------------------------+
   +-----------+                                |  |  |  |
                                                |  |  |  |  Hyperthreading
                                                v  v  v  v
                                        +---+ +---+ +---+ +---+
                                        |SCK| |SCK| |SCK| |SCK|   4 pinned
                                        | 0 | | 1 | | 2 | | 3 |   sockets, each
                                        +-+-+ +-+-+ +-+-+ +-+-+   holds a V2
                                          |     |     |     |     inset PCB
                                          v     v     v     v     with a
                                        +---+ +---+ +---+ +---+   WritePhi die
                                        |V2 | |V2 | |V2 | |V2 |
                                        |die| |die| |die| |die|
                                        +---+ +---+ +---+ +---+

The card carries 4 pinned sockets in the reference design (WPD-ACCEL-CARD-4). An 8-socket variant (WPD-ACCEL-CARD-8) uses the full PCIe 5.0 x16 electrical width.

3. The V2 package (this project's core innovation)

Four sub-components, each with its own SPEC:

Inset PCB carrier (hardware/INSET_PCB_SPEC.md) — small FR-4 PCB with WritePhi die bonded to top-side pads via anisotropic conductive adhesive (ACA); standard FR-4 pads on the bottom for socket mating
Pinned socket (hardware/PINNED_SOCKET_SPEC.md) — spring-loaded pin block that accepts the inset PCB; cam-lever cap for retention
Die cut marks + tabs (hardware/DIE_CUT_MARKS_SPEC.md) — additional geometry the WRITEPHI-DICER (Project 57) cuts during the same pass: scribe lines, fiducials, IC tabs
V2 package overview (hardware/V2_PACKAGE_SPEC.md) — how the four sub-components integrate

Why V2 exists: the Project 57 socket (PKG-M/-H) uses a cam-lever socket whose contacts land directly on pads written into the WritePhi die. Fine for benchtop bring-up. Not manufacturable at volume — the polycarbonate die can't survive automated pick-and-place, sea-freight shipping, or board-level rework without a carrier. V2 puts the die on an FR-4 carrier once at factory (ACA bond, < 100 °C, below polycarbonate softening point of 145 °C), then the FR-4 carrier is what handles the mechanical cycling.

4. WPD-CSD persona — Computational Storage Device

4.1 Front-end

NVMe 2.0 over PCIe 5.0 x8. Windows 11 24H2+ recognizes natively via the stornvme.sys class driver.
Namespace layout: 1 admin namespace + N data namespaces (N = number of populated sockets on the card). Each socket-hosted WritePhi die is a distinct namespace.
Advertises: standard NVMe 2.0 features + Computational Programs command set (NVMe TP4091). Programs are submitted via NVME_ADMIN_CMD_COMPUTE_PROGRAM_SUBMIT (opcode 0xD8 in this reference; buyer negotiates with NVMe SIG for final opcode assignment).
Reference performance targets (design, not measured):
4-socket M-grade: 100k random 4KB IOPS, 1 GB/s sequential
8-socket H-grade: 800k random 4KB IOPS, 8 GB/s sequential

4.2 User-mode SDK (Windows)

DLL exposes wpd_open_device(), wpd_submit_program(), wpd_get_result() on top of DeviceIoControl().
Compatible with existing NVMe I/O — buyer's application can read/write the storage AND submit compute programs through the same handle.

4.3 Reference use cases

Encrypted-at-rest storage where decrypt happens in-drive (only decrypted plaintext streams to host)
Compressed-at-rest storage with in-drive query engine (SQL / KV lookup)
Video archive with in-drive frame-extraction / re-encoding
Log storage with in-drive grep / regex filter

5. WPD-ACCEL persona — Computational Accelerator

5.1 Front-end

PCIe 5.0 x8. Custom KMDF driver (wpd_accel.sys) enumerates the card as an accelerator device.
Presents a command / completion queue pair per socket (per die), similar to CUDA streams. Applications submit jobs to a specific socket or let the driver load-balance across sockets.
Optionally publishes a DirectML backend for Windows AI framework integration.

5.2 User-mode SDK (Windows)

DLL exposes wpd_accel_open(), wpd_accel_submit(), wpd_accel_wait(), wpd_accel_result().
Model shape: buyer's application selects a program (compiled from sdk/python/writephi/ per Project 57) + submits a data buffer + receives a result buffer.
Sample programs for launch: AES-128 encrypt (WPIC-AES-CORE from Project 57), 12-bit SPI DAC waveform generation (WPIC-SPI-DAC-01), 4-channel PWM (WPIC-PWM-01), and a small INT8 convolution kernel.

5.3 Reference use cases

Bulk crypto (AES / SHA / hash operations offloaded from host CPU)
DSP (FIR filter arrays, DFT/FFT, waveform generation)
Small-model inference (INT8 CNN, small transformer heads, embedding lookups)
Codec offload (H.264 / H.265 partial decode helpers)

6. The physical card (WPD-DEVICE)

6.1 Form factor

PCIe 5.0 x8 (WPD-ACCEL-CARD-4, 4 sockets) or x16 (WPD-ACCEL-CARD-8, 8 sockets)
Half-height / half-length (HHHL) or full-height / full-length (FHFL) depending on socket count
Standard PCIe AIC edge; drops into any PCIe 5.0 slot

6.2 Compute layout

AutoPhi 1Z-Edge bus master + persona firmware
4 or 8 pinned sockets, each holding one V2-packaged WritePhi die
Hyperthreading fabric between sockets (per Project 57 inventions 1455-1458)
Per-socket VDD_CORE regulator — independent sequencing, no single-die failure takes down the card

Full detail in hardware/WPD_ACCEL_CARD/SPEC.md.

7. Firmware

7.1 Persona firmware — CSD

NVMe front-end: implements the NVMe 2.0 spec + Computational Programs command set
Storage layer: maps NVMe LBA space to WritePhi-die-hosted flash pages (each die can host a small SRAM / flash block via a WritePhi-native memory-cell design)
Compute layer: dispatches submitted programs to the addressed die via the hyperthreading fabric

7.2 Persona firmware — ACCEL

KMDF command-queue front-end: implements job submission / completion signaling to the host
Scheduler: load-balances jobs across populated sockets
Compute layer: same underlying die-dispatch mechanism as CSD; different queue-entry format at the host boundary

Both personas share the AutoPhi 1Z-Edge bus master + hyperthreading fabric. The difference is at the PCIe-endpoint front-end and the host-facing queue format.

8. Certification & compliance (buyer scope)

PCI-SIG PCIe 5.0 compliance — buyer certifies through PCI-SIG
NVMe compliance (CSD persona) — buyer certifies through NVM Express
Windows Hardware Lab Kit (HLK) — buyer certifies for Windows logo
UL 60950-1 / IEC 62368-1 — buyer certifies for consumer / commercial use
FCC Part 15 Class B / CE — buyer certifies for consumer market

9. Standards followed

10. Portfolio firewall

Project 58 is arms-length from Project 57. Same architecture family (both use WritePhi dies + AutoPhi 1Z-Edge). Separate SKUs, separate contracts, separate revenue.

Project 58 sibling dependencies:

Project 57 — Writer/Dicer/Blank family (dies come from here)
Project 18 — AutoPhi Future (bus master silicon)
Project 39 / 44 — AutoPhi PCIe5-256 / -1536 host boards (optional portfolio-native hosts)

11. Revisions

WritePhi Devices — Status (honest report)

Project 58 · cri-one.com portfolio · 2026-07-04 · Revision 0.1

Overall maturity: DESIGNED. No prototype. No Windows driver has been compiled. No inset PCB has been fabricated. No pinned socket has been sourced.

Subsystem status

Dependencies on Project 57

WritePhi Devices requires a functioning Project 57 supply chain:

WRITEPHI-WRITER — writes the dies. Project 57 rev 0.5 has drafted controller schematic.
WRITEPHI-DICER — dices dies AND cuts the new V2 tab / fiducial features. Project 57 rev 0.5 has drafted controller schematic. Cut-mark firmware upgrade is on the Project 57 pickup queue.
WRITEPHI-BLANK — the substrates. Project 57 rev 0.2 spec on file.
WRITEPHI-LIB — design library. Project 57 seeded from Parts Future.

Honest report

Nothing is fabricated. Nothing is running Windows. Every performance number is a design target. Buyers who commit to Project 58 are committing to a complete engineering package + Windows-driver plan, not a shipping product.

What Chris's ceiling delivers: SPEC + BOM + LAYOUT_HINT + drafted schematics + firmware / driver plans. Everything else is buyer scope — PCB fab, socket sourcing, driver compilation, Windows HLK certification, PCI-SIG certification, NVMe certification, FCC / UL / CE certification, sea-freight-tested board bring-up.

WritePhi Devices — Store Listing Brief

Project 58 · cri-one.com portfolio · 2026-07-04

Brief for Chris — everything needed to create the WPD products on cri-one.com/store.

Live URL (target)

https://cri-one.com/store/wpd.html (or split as /wpd-csd.html + /wpd-accel.html if the two personas need separate landing pages)

Magento entity fields — sellable-parts structure

All SKUs are downloadable (product type downloadable, weight 0). Buyer picks the specific blueprint they want.

Study tier — four per-part blueprints at $1,250 each

Personal + educational use only.

Full + Commercial + OEM tiers

Shared fields (all SKUs): Category Semiconductor & Fabrication, Type Downloadable, Weight 0, Visibility Catalog, Search, Status Enabled, Country USA only (nginx geo-block + human-id-geoblock), Currency USD only, Tax class Taxable Goods, Description sourced from a future wpd_store_description.html (not yet drafted — on pickup queue). Downloadable files live in C:\Users\crione\Chris\System\shipped-downloads\ after running bundle.py.

Downloadable pack sizes (2026-07-04 build)

Deploy sequence

1. Prepare wpd_store_description.html (on pickup queue — not yet drafted; likely a persona-aware page showing both CSD and ACCEL angles)

2. Create Magento entities in admin at /mgmt---24 — 9 SKUs total (4 Study sub + Full + Commercial + BuildHelp + OEM-EngPkg + bundle reference)

3. Push descriptions via the prepare-then-push helper

4. Attach downloadable files from System\shipped-downloads\

5. Confirm production-mode caches after deploy per store-production-mode memory

6. Add row to total-all-in-one.html humdinger — bump project count 57 → 58

7. Verify from a US IP that /store/wpd.html renders + human-ID / geoblock work

WritePhi Devices — Concept

Project 58 · cri-one.com portfolio · 2026-07-04

Vision

One card. Windows plug-in. Either your data lives here, or your compute lives here — you pick at boot.

The WritePhi platform (Project 57) proved kitchen-table chip fabrication + user-in-place chip replacement. Project 58 productizes that platform into two Windows-native devices any buyer with a PCIe 5.0 slot can drop in and use without a custom driver stack or Linux-first setup.

Two personas, one card

WPD-CSD (Computational Storage Device) — presents as an NVMe drive on the SPCIe bus. Windows sees a storage device. Applications write data to it like any SSD. But the device runs code against that data at rest via the NVMe 2.0 Computational Programs command set. Example: an application uploads 100 GB of data and a compressed query program; the device runs the query inside the drive and returns only the result. No host CPU cycles. No bus bandwidth spent shipping data over.

WPD-ACCEL (Computational Accelerator) — presents as a PCIe compute endpoint via a KMDF (Kernel-Mode Driver Framework) driver. Windows sees an accelerator device. Applications submit compute jobs to it — crypto operations, DSP transforms, small-model inference, video codec offload. The device executes on a fleet of WritePhi dies and returns results.

The physical card is identical. The firmware in the AutoPhi 1Z-Edge bus master picks the persona at boot time; the Windows driver picks the matching enumeration. A buyer who wants both can flash between them; a buyer who wants CSD-only or accel-only gets a firmware-locked variant that ships pre-configured.

Why this is possible only with V2 package

The Project 57 socket (WRITEPHI-PKG-M / -H) uses a cam-lever socket whose contacts land directly on pads written into the WritePhi die. That works for benchtop / education / small-lab bring-up. It does not work for volume manufacturing of a Windows-plug-in device that has to survive:

Sea-freight shipping (mechanical shock)
Retail-channel handling (drops, vibration, thermal cycling)
Automated pick-and-place assembly (the die needs to sit on a carrier pick-and-place can grab)
Board-level rework (removing / replacing an individual die on a populated card)
Certification (UL, FCC, CE) — every certified device needs a repeatable, characterized assembly method

The V2 package solves this by bonding the WritePhi die once at factory onto a small inset PCB carrier using anisotropic conductive adhesive (ACA) below the polycarbonate softening point. The carrier PCB has standard FR-4 pads on the bottom that mate to a standard pinned socket. Everything downstream is normal PCB manufacturing — pick-and-place places the carrier + die assembly; the socket is a commodity spring-loaded pin block; the host PCB fabrication is standard.

The four V2 innovations

1. Inset PCB — small FR-4 PCB (5 × 5 mm to 12 × 12 mm) with the WritePhi die bonded to the top, pads on the bottom

2. Cut marks on the die — the WRITEPHI-DICER cuts scribe lines + fiducials during the same pass that dices the die outline; the fiducials remain visible after dicing for auto-alignment at ACA bonding

3. Socket-to-IC tabs — the DICER cuts tabs into the die outline; the inset PCB has matching recesses; the tabs prevent shear + provide fool-proof orientation

4. Pinned socket — spring-loaded pin block on the host PCB; the inset PCB drops onto it and a cam-lever cap holds it down

Every one of these is buyer-manufacturable at existing PCB / assembly / socket vendors. The buyer does not need custom-injection-molded socket bodies (unlike Project 57 PKG-M/H). The buyer contracts to Yamaichi / Ironwood / Aries for the pinned socket + standard PCB fab for the carrier.

The buyer's Windows integration

For WPD-CSD:

Windows 11 24H2 recognizes any NVMe 2.0 device natively. The Microsoft NVMe class driver handles enumeration + I/O.
The Computational Programs command set (NVMe 2.0 TP4091) is optional — WPD-CSD advertises it as an optional feature; Windows applications that don't know about it see a normal SSD.
User-mode SDK is a small DLL exposing wpd_submit_program() / wpd_get_result() on top of the standard DeviceIoControl() interface.

For WPD-ACCEL:

Custom KMDF driver (wpd_accel.sys) enumerates the card as a compute device.
User-mode SDK exposes wpd_accel_submit() / wpd_accel_result() similar to CUDA / OpenCL / DirectML in shape.
Optionally publishes a DirectML backend for out-of-the-box Windows AI framework support.

Full detail in windows/README.md.

Firewall — Project 58 is arms-length from Project 57

Project 57 (WritePhi) sold as kitchen-table chip fabrication + user-in-place chip replacement for education / DIY / small-defense / prosumer. Project 58 sold as Windows-plug-in device for prosumer / enterprise / OEM.

Same silicon (WritePhi dies). Different distribution model. Different Windows integration. Different revenue stream. Separately licensable per LICENSE.md.

Maturity — honest report

Designed. V2 package, inset PCB, pinned socket, cut marks / tabs — all spec'd on file. One reference add-in card schematic + one inset PCB reference schematic drafted. Windows driver personas outlined; NVMe class driver for CSD is 90 % Microsoft-shipped-in-box; KMDF for accelerator is buyer-scope development. No prototype exists. All performance numbers are design targets, not measured guarantees. See STATUS.md.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

Email: crioneaka@outlook.com · crioneaka@outlook.com

Mail: 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

WritePhi Devices — Store Listing Brief

Project 58 · cri-one.com portfolio · 2026-07-04

Brief for Chris — everything needed to create the WPD products on cri-one.com/store.

Live URL (target)

https://cri-one.com/store/wpd.html (or split as /wpd-csd.html + /wpd-accel.html if the two personas need separate landing pages)

Magento entity fields — sellable-parts structure

All SKUs are downloadable (product type downloadable, weight 0). Buyer picks the specific blueprint they want.

Study tier — four per-part blueprints at $99 each

Personal + educational use only.

Full + Commercial + OEM tiers

Downloadable pack sizes (2026-07-04 build)

Deploy sequence

1. Prepare wpd_store_description.html (on pickup queue — not yet drafted; likely a persona-aware page showing both CSD and ACCEL angles)

2. Create Magento entities in admin at /mgmt---24 — 9 SKUs total (4 Study sub + Full + Commercial + BuildHelp + OEM-EngPkg + bundle reference)

3. Push descriptions via the prepare-then-push helper

4. Attach downloadable files from System\shipped-downloads\

5. Confirm production-mode caches after deploy per store-production-mode memory

6. Add row to total-all-in-one.html humdinger — bump project count 57 → 58

7. Verify from a US IP that /store/wpd.html renders + human-ID / geoblock work

WritePhi Devices — Four Explanations at Different Knowledge Levels

Project 58 · cri-one.com portfolio · 2026-07-04

Same subject matter — what WPD is and how it works — explained four times at progressively technical levels. Pick the section that matches your background.

Level 1 — Newcomer (Study tier · $99–$1,499)

What WritePhi Devices is, in plain English.

WritePhi Devices takes the "make your own chips" idea from WritePhi (Project 57) and turns it into a plug-and-play device that works on a Windows PC. You get a card that goes in a PCIe slot inside your computer — the same kind of slot a graphics card goes in.

The card can do one of two things:

1. Storage that runs your code. Instead of buying a solid-state drive that just holds files, you buy this card, which holds files and can run small programs on the data at rest. Example: you upload 100 GB of encrypted photos and a program that decrypts them. The card decrypts them without sending encrypted data over the computer's bus. It's called Computational Storage.

2. An accelerator. Same card, different personality. Windows sees it as a compute accelerator. You send it math jobs (crypto, signal processing, small AI models) and it runs them on tiny chips inside the card while your CPU stays free.

The card physically holds 4 slots. Each slot holds a WritePhi chip — the same kind of chip you'd make on a Project 57 Writer. You can replace individual chips by hand in under a minute; no soldering iron needed.

The important part: the chips inside are packaged in a V2 package — a tiny circuit board that carries the chip and drops into a socket. This is different from Project 57's socket because it uses standard, off-the-shelf parts from companies like Yamaichi and Aries. That means you can actually build these cards in volume without inventing new socket bodies.

What you get for $99. One blueprint (V2 package, or reference cards, or Windows drivers, or firmware) — you pick. Personal / educational use. If you're an engineer studying how someone would build a Windows-plug-in chip carrier from scratch, this is where you start.

Level 2 — Practitioner (Commercial tier · $49,999)

What WPD is, for someone with hardware + Windows driver background.

WPD is a dual-persona PCIe 5.0 x8 add-in card that presents as either an NVMe 2.0 Computational Storage Device (via Windows in-box stornvme.sys extended with the NVMe TP4091 Computational Programs command set) or a KMDF-driver-based compute accelerator (with an optional DirectML backend published to Windows AI Foundry). Persona is selected at boot via strap resistors R1 / R2; both firmware images live in on-card NOR flash, and the AutoPhi 1Z-Edge bus master reads the strap and loads the matching persona at cold power-up.

The card's compute density comes from 4 socketed WritePhi dies (M-grade or H-grade per buyer order) in a star-topology hyperthreading fabric to the bus master. Each socket is a V2 pinned socket — commodity commercial pogo-pin socket from Yamaichi IC189 / Aries Correct-8 / Ironwood HiPer / Enplas ORDER lines — that accepts a small 12 × 12 mm (M) or 30 × 30 mm (H) FR-4 inset PCB carrier carrying the WritePhi die. The die is bonded to the top-side FR-4 pads via anisotropic conductive adhesive (Delo Katiobond LP686 or equivalent) at 90 °C for 15 minutes under 50 N/cm² — well below polycarbonate's 145 °C softening point. The carrier's bottom-side pads (144-ball 1.0 mm grid for M or 256-ball 0.8 mm grid for H) mate to the pinned socket's pogo pins.

Cut marks. The WRITEPHI-DICER (Project 57) cuts three additional geometry features during the dice pass: scribe lines (50% penetration for clean hand-break), 3 alignment fiducials per die (100 µm circle at pin-1, 100 µm cross at diagonal, 200 µm square at center), and asymmetric IC tabs (2 for M-grade, 4 for H-grade) that mate to slots in the inset PCB for fool-proof orientation and shear retention.

Windows integration. WPD-CSD reuses the Windows in-box NVMe class driver — no custom driver needed at the class layer. WPD-ACCEL uses a custom KMDF driver (wpd_accel.sys) that the buyer signs via WHCP. The user-mode SDK is a DLL (wpd_sdk.dll) exposing wpd_open(), wpd_accel_submit(), wpd_accel_wait(), wpd_accel_result() on top of DeviceIoControl(). Example: submit a WPIC-AES-CORE .wpprog (from Project 57) as the program + a 16-byte plaintext + 16-byte key, wait, read the ciphertext back.

What you get for $49,999. Full WPD blueprint + right to build and sell products from it, including signing your own KMDF driver under your WHCP account. You bring up the PCB layout of both reference schematics (WPD-ACCEL-CARD and INSET-PCB-M), qualify the ACA bond process, source pinned sockets from a commercial vendor, implement the driver from the delivered plans, and cert through PCI-SIG PCIe 5.0 + NVMe SIG + Windows HLK. The engineering package makes this a driver + PCB layout + cert effort, not an original architecture effort.

Level 3 — Engineer (Build-Help tier · $500,000)

What WPD is, for the engineer doing the actual Windows-plug-in bring-up.

WPD Rev 0.1 ships as two ERC-clean KiCad 10 schematics — WPD_ACCEL_CARD (89 components, 74 nets, 3,373-line .kicad_sch) and INSET_PCB_M (18 components, 20 nets, 739-line .kicad_sch) — plus V2 package sub-specs (V2_PACKAGE_SPEC covering the overall integration flow, INSET_PCB_SPEC covering the die-carrier PCB, PINNED_SOCKET_SPEC covering the commercial socket, DIE_CUT_MARKS_SPEC covering the new DICER firmware extensions for scribe + fiducial + tab cuts). Both KiCad schematics import from ../57-chip-write/hardware/_factory.py — the same recipe as Project 57 (grid-snap, PWR_FLAG per rail, bypass at every power_in, no_connect on every un-netted pin).

V2 package assembly flow at factory. WRITEPHI-WRITER writes a blank per SDK-compiled .wpprog. WRITEPHI-DICER dices the blank + cuts scribe + fiducials + IC tabs. Each die is picked (vacuum tool grips the protective cover, not the recording layer) and placed onto an inset PCB via vision-aligned bonder against the fiducials with ± 20 µm registration. ACA cure at 90 °C × 15 min × 50 N/cm². IC tabs mate to inset PCB slots — asymmetric geometry enforces orientation. Assembled inset PCB is wafer-level probe tested against a known-good .wpprog verify pattern (target good-die-good-package yield ≥ 99 % at 10k volume).

V2 package assembly flow at buyer's site. SMT reflow pinned sockets onto the host PCB using standard SAC305 profile (up to 260 °C peak). WritePhi dies are NOT present during host-PCB reflow — the 145 °C polycarbonate constraint is never approached at host-PCB manufacturing time. Assembled inset PCBs are inserted into pinned sockets by hand or automated placement head (both work — the inset PCB is standard FR-4 and grippable). Cam-lever cap on each socket rotates closed to retain.

Windows driver bring-up. For WPD-CSD, no new driver code required at the class layer — stornvme.sys handles NVMe 2.0 enumeration. If you're using the Computational Programs extension, you negotiate opcode assignment with NVMe SIG (reference opcodes: 0xE0-0xE2 admin, 0xD8-0xDA I/O) and add a filter driver or user-mode SDK that submits via IOCTL_STORAGE_QUERY_PROPERTY. For WPD-ACCEL, write wpd_accel.sys per Microsoft KMDF guidelines. IOCTL interface: IOCTL_WPD_SUBMIT (0x800), IOCTL_WPD_WAIT (0x801), IOCTL_WPD_RESULT (0x802, METHOD_OUT_DIRECT), IOCTL_WPD_QUERY_SOCKETS (0x803). DMA setup via WdfCommonBufferCreate with 4 KB alignment; MSI-X interrupt vector for completion signaling. Load balance across the 4 socket-hosted dies with socket_hint = 0xFFFFFFFF for round-robin, or pin to a specific socket for latency-sensitive workloads.

Cert path. PCI-SIG PCIe 5.0 CEM compliance (physical + electrical); Windows HLK Storage Adapter Tests (CSD persona) or System class + KMDF driver tests (ACCEL persona); if CSD-only variant, NVMe SIG interop workshop for Computational Programs certification; FCC Part 15 Class B + UL 60950-1 / IEC 62368-1 + CE for consumer market.

What you get for $500,000. Everything at Commercial tier plus inventor support (calendar-booked, remote), custom driver-plan development (specific IOCTL interfaces for buyer's Windows workflow), Windows HLK guidance (test-pass planning, waiver strategy). The support engagement is scoped to your specific Windows-plug-in bring-up.

Level 4 — Architect (OEM Engineering-Package tier · $12,750,000)

What WPD is, for the buyer becoming the WPD vendor.

WritePhi Devices is the productized Windows-plug-in layer built on the WritePhi (Project 57) fabrication platform. The V2 package (inset PCB carrier + pinned socket + cut marks + IC tabs) is the specific packaging invention that decouples the polycarbonate WritePhi die from the mechanical stresses of production Windows-device shipping (pick-and-place, sea-freight shock, board-level rework, Windows HLK certification), making WritePhi dies socketable via commodity commercial parts and thus volume-manufacturable at any established PCB / SMT / assembly vendor.

Portfolio positioning. Project 58 is arms-length from Project 57 per portfolio firewall. Same architecture family (both use WritePhi dies + AutoPhi 1Z-Edge). Separate SKUs, separate contracts, separate revenue. Project 57 sells the platform to education / DIY / prosumer / small-lab; Project 58 sells the Windows-plug-in productized layer to prosumer / enterprise / OEM. Portfolio siblings under separate license: AutoPhi Future (Project 18), AutoPhi 1Z Accelerator (Project 23), AutoPhi PCIe5-256 (Project 39, optional portfolio-native host board), AutoPhi PCIe5-1536 (Project 44, optional high-density host).

Prior-art positioning. V2 package distinguishes over Aries / Ironwood Electronics / Yamaichi / Enplas commercial socketed-BGA product lines (which accept pre-packaged silicon BGAs, not bare polycarbonate WritePhi dies), over industry MCM/interposer packaging (which is soldered, not user-serviceable), and over FPGA emulation platforms (which run pre-fab silicon, not written substrate). The specific novelty step: ACA bonding of a written polycarbonate optical-substrate die to an FR-4 carrier + inset carrier drops into a commodity pinned socket + IC tabs cut into the die outline for fool-proof orientation and shear retention. Anchored to Project 57 inventions 1449-1454 plus V2-specific method claims (cut-mark firmware extension to WRITEPHI-DICER, inset PCB carrier method, socket-to-IC tabs on optical-substrate dies). Priority date 2017-11-24 for the WritePhi foundations; V2-specific method claims require a new utility filing (Pro Bono track given inventor's SSI eligibility per portfolio memory).

Windows-integration architecture. Dual-persona firmware (CSD + ACCEL) shares an AutoPhi 1Z-Edge bus-master runtime with shared/ PCIe root, hyperthreading, socket-management, DDR4-buffer, NOR-flash, and logging modules, plus persona-specific csd/ (NVMe front-end + Computational Programs + program registry) or accel/ (MMIO command/completion queues + job scheduler + optional DirectML backend). Persona strap R1/R2 is read at cold boot; strap-forced-CSD / strap-forced-ACCEL / dual-boot variants ship at inventor's discretion. Vendor ID 0x1D7F is reserved for buyer's own PCI-SIG registration.

Revenue architecture. At the OEM Engineering-Package Acquisition tier, all V2 package IP + reference schematics + Windows driver plans + trademarks license (WPD-CSD, WPD-ACCEL, WPD-DEVICE, V2 Package, WPD-*) transfer to buyer. Inventor hand-off. Buyer becomes the WPD vendor and can sub-license the V2 package to third-party silicon (subject to Project 57 dependency license negotiation). Structure — asset purchase, exclusive license, joint venture, revenue share, milestone, strategic acquisition — is tailored per acquiring organization. Bankruptcy notation applies.

What you get for $12,750,000. All V2 package blueprints + WPD-ACCEL-CARD reference schematic + INSET-PCB-M reference schematic + Windows driver plans (both personas) + firmware overview + full commercialization rights + trademarks license + inventor hand-off. Aligned with the Licensed Research pricing playbook ($99–$12.75M ceiling per SKU family). Included at no extra charge inside All In One (20T) — the complete cri-one.com portfolio acquisition.

WritePhi Devices (Project 58) — Magento image upload map

Flat clip-art style (like Chemical-Cooker 3113 / Pagers 3153): colored shapes,

thin black outlines, soft shadow, caption at bottom.

Regenerate:

python gen_magento_pngs.py

Catalog / thumbnail (all WPD SKUs)

Product page hero

Per-SKU study blueprints ($99 each)

Each SKU also has a wpd_{sku}_hero.png alias (same art).

Technical block diagrams (gray flowcharts) remain in *.svg / gen_pngs.py for store HTML embeds.

This archive contains 21 documents; 11 more beyond this preview. The complete folder ships as the product.

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