Skip to the beginning of the images gallery

58-writephi-devices

$9,823.88

In stock

SKU

2089

WritePhi Devices: one PCIe card with four WritePhi dies switches between its two personas, storage and accelerator, animated picture

Asset valuation: $2,800,000,000. Project 58 · cri-one.com portfolio · 2026-07-04 Windows-compatible computational storage device and computational accelerator, built on the WritePhi platform (Project 57). One physical device, two Windows-driver personas.

For the curious

Think of a drive that does not just hold your data but runs your code against it. WritePhi Devices is one PCIe 5.0 x8 add-in card with two Windows personas, chosen at purchase. As WPD-CSD it appears as a standard NVMe 2.0 drive and runs compute jobs inside the drive against data at rest. As WPD-ACCEL it appears as a compute endpoint and offloads crypto, signal processing, small-model inference and codec work onto WritePhi dies. Same card; two strap resistors decide which firmware loads at power-up.

The V2 package is what makes the card buildable in volume. A pick-and-place head cannot reliably hold a bare polycarbonate die, so V2 bonds it at the factory onto a rigid FR-4 carrier with anisotropic conductive adhesive that sets well below the point where polycarbonate softens. The carrier drops into a commodity pogo-pin socket with a cam-lever cap: no custom-moulded socket bodies, a standard JEDEC BGA outline underneath, and the host board reflows with no die present. Rework is popping a carrier out. Shipping shock lands on the carrier, not the die.

This is for datacenter operators and Windows system builders who want a slot of storage that computes, and for engineering buyers who want a carrier any board house can make. Nothing is prototyped: ERC-clean KiCad 10 schematics, driver plans and a firmware overview are on file; every number is a design target. The buyer walks away with the V2 package specification and reference schematics; the IP, under the framework filing with its 2017 priority date, stays with the inventor.

Details

Description

WritePhi Devices — Dual-Persona PCIe 5.0 Computational Storage & Accelerator Card (Project 58)

Inventor: Christopher Gabriel Brown — cri-one.com portfolio, Project 58.

Framework filing: USPTO Application No. 19/693,405.

Priority date: 2017-11-24 (WritePhi substrate foundations); V2-specific method claims anchored to inventions 1449–1458 plus the V2 Package invention record.

Specification revision: 0.1, dated 2026-07-04.

Status: Designed. Complete engineering package on file — V2 package specifications, reference schematics (ERC-clean, KiCad 10), Windows driver plans, firmware overview. No prototype fabricated. All performance figures are design targets derived from the engineering record, not measured guarantees.

Overview

WritePhi Devices is a Windows-compatible product family built on the WritePhi fabrication platform (Project 57). One physical PCIe 5.0 ×8 add-in card serves two distinct Windows-driver personas — the buyer selects the persona at purchase:

WPD-CSD — Computational Storage Device. Presents as a standard NVMe 2.0 drive to Windows via the in-box stornvme.sys class driver. Runs compute jobs inside the drive against data at rest using the NVMe 2.0 Computational Programs command set (NVMe TP4091). Replaces a slot of SSD storage with a slot of “storage that runs your code.”
WPD-ACCEL — Computational Accelerator. Presents as a PCIe compute endpoint via a custom KMDF driver ( wpd_accel.sys ). Offloads crypto, DSP, small-model inference, and codec workloads onto a fleet of WritePhi dies. Optionally publishes a DirectML backend for Windows AI framework integration.

Same PCIe 5.0 ×8 card. Different firmware. Different Windows driver. Persona selected at boot via strap resistors R1 / R2 on the card. Both firmware images reside in on-card NOR flash; the AutoPhi 1Z-Edge bus master reads the strap at cold power-up and loads the matching persona.

The V2 Package — Core Productisation Innovation

Project 58 introduces the V2 package — a redesigned die-carrier architecture that makes WritePhi dies volume-manufacturable, pick-and-place-compatible, sea-freight-shippable, and field-serviceable at production sample count. Every WPD-CSD and WPD-ACCEL card uses V2 packaging. Four sub-components, each with its own specification:

Component What It Is

Inset PCB Carrier Small rigid FR-4 PCB (12 × 12 mm M-grade; 30 × 30 mm H-grade) with WritePhi die bonded to top-side pads via anisotropic conductive adhesive (ACA); standard ENIG pads on the bottom for pinned-socket mating.

Pinned Socket Spring-loaded pogo-pin block mounted on the host PCB. Cam-lever cap rotates closed to retain the inset PCB onto the pins. Buyer-sourceable from Yamaichi IC189, Aries Correct-8, Ironwood HiPer, or Enplas ORDER commercial families — no custom-injection-moulded socket bodies required.

Die Cut Marks + IC Tabs Additional geometry the WRITEPHI-DICER (Project 57) cuts during the same dicing pass: scribe lines for clean hand-break, three alignment fiducials per die for automated ACA bonding, and asymmetric IC tabs for fool-proof orientation and shear retention.

Host PCB Integration Standard JEDEC BGA outline on the pinned-socket underside; drops into any host PCB library without modification. SAC305 reflow up to 260 °C — no WritePhi die present during host-PCB reflow.

V2 vs. V1 — Why V2 Exists

Problem V1 (Project 57 PKG-M/-H) V2 (Project 58)

Pick-and-place Fragile polycarbonate die; vacuum head cannot reliably hold it. Standard FR-4 carrier; P&P grabs the carrier, die rides along.

Sea-freight shock Every shock applied directly to die-socket contact interface. Die ACA-bonded to rigid FR-4 carrier at factory; carrier absorbs shock.

Board-level rework Disassemble cam-lever socket + lift polycarbonate die out. Pop inset PCB out of pinned socket. Standard socketed-BGA rework flow.

Certification Every die-socket contact is a certification variable. Standard PCB-BGA-socket-PCB path, well-characterised in industry.

Automated test Custom probe cards required for raw die. Test inset PCB assembly once at factory; handle only carriers downstream.

Sourcing Custom-injection-moulded socket bodies (Project 57). Commodity pinned sockets + standard PCB fab at any board house.

Inset PCB Carrier — Dimensions & Specifications

M-Grade Reference (INSET-PCB-M)

Parameter Value

Board outline 12 × 12 mm

Board thickness 0.8 mm (4-layer FR-4, Tg 150)

Top-side pad count 84 (one per M-grade die contact)

Top-side pad pitch 1.0 mm

Top-side pad size 500 × 500 μm square

Bottom-side pad count 144 (12 × 12 grid, some depopulated)

Bottom-side pad pitch 1.0 mm

Bottom-side pad size 0.55 mm circle

Alignment tabs 2 (pin-1 chamfer corner + opposite corner, asymmetric)

Tab dimensions 1.5 × 1.0 mm (pin-1, larger) / 1.0 × 1.0 mm (opposite, smaller)

Surface finish ENIG (electroless nickel + immersion gold, 5 μm nominal)

Schematic KiCad 10 — 18 components, 20 nets

BOM cost estimate ~$3.60 per assembled unit at 10k volume (excludes WritePhi die)

ERC result 0 errors, 0 warnings

H-Grade Reference

Parameter Value

Board outline 30 × 30 mm

Board thickness 1.0 mm (6-layer low-loss FR-4, Megtron 6)

Top-side pad count 168

Top-side pad pitch 0.5 mm

Top-side pad size 250 × 250 μm

Bottom-side pad count 256 (16 × 16, some depopulated)

Bottom-side pad pitch 0.8 mm

Bottom-side pad size 0.45 mm circle

Alignment tabs 4 (one at each corner; pin-1 corner tab 2.0 × 1.5 mm, others 1.5 × 1.5 mm)

M-Grade Layer Stack

Layer Function

Top 84 ENIG die-attach pads + fiducials + reference designator silkscreen

Inner 1 (GND plane) Ground plane

Inner 2 (Power planes) VDD_CORE_1V0 + VDD_IO_1V8 + VDD_ANA_1V0 fanout

Bottom 144 ENIG socket-mating pads + tab-fill copper + pull-tab silkscreen

ACA Bond Zone

Parameter Value

ACA material Delo Katiobond LP686 (or equivalent FCOB ACA)

Cure temperature 90 °C (55 °C below polycarbonate softening point of 145 °C)

Cure time 15 minutes

Cure pressure 50 N/cm²

ACA thickness ~25 μm

Die alignment Vision-aligned bonder, ± 20 μm registration

Good-die-good-package yield target ≥ 99% at 10k volume

Housekeeping Components on INSET-PCB-M

Reference Value Manufacturer Part Number Qty

J1 Top-side die-attach pads (84 contacts, 1.0 mm pitch, ENIG) cri-one.com INSET-PCB-M-TOP 1

J2 Bottom-side socket pads (144-ball grid, 1.0 mm pitch, ENIG) cri-one.com INSET-PCB-M-BOT 1

D1 Semtech RClamp0854S 8-line TVS array (DNP on M-grade) Semtech RCLAMP0854S.TCT 1

C1–C4 100 nF X7R 0402 bypass (VDD_CORE_1V0) Murata GRM155R71H104KE14D 4

C5–C6 100 nF X7R 0402 bypass (VDD_IO_1V8) Murata GRM155R71H104KE14D 2

C7–C8 100 nF X7R 0402 bypass (VDD_ANA_1V0) Murata GRM155R71H104KE14D 2

C9–C11 4.7 μF X5R 0603 bulk (one per rail) Murata GRM188R60J475KE19D 3

PCB 4-layer FR-4 inset carrier (Tg 150), 12 × 12 mm — — 1

ACA Anisotropic conductive adhesive (25 μm paste) Delo Katiobond LP686 1

Pinned Socket — Specifications

Parameter Socket-M Socket-H

Accepts INSET-PCB-M (12 × 12 mm) INSET-PCB-H (30 × 30 mm)

Pin count 144 (12 × 12, some depopulated) 256 (16 × 16, some depopulated)

Pin pitch 1.0 mm 0.8 mm

Pin type Spring-loaded pogo Spring-loaded pogo

Pin material Beryllium copper, gold plated Beryllium copper, gold plated

Mating cycles (design target) ≥ 10,000 ≥ 100,000

Contact resistance ≤ 40 mΩ ≤ 30 mΩ

Retention Cam-lever cap (90° rotation) Cam-lever cap (90° rotation)

Retention force (design target) 144 N nominal 205 N nominal

Insertion force Zero (cam open) Zero (cam open)

Underside BGA ball count 144 (12 × 12) 256 (16 × 16)

Underside BGA ball pitch 1.0 mm 0.8 mm

Underside BGA ball material SAC305 SAC305

Package outline on host PCB 20 × 20 mm 35 × 35 mm

Signal Integrity (H-Grade, Design Targets)

Parameter Target

Insertion loss @ 5 GHz ≤ 1.2 dB per pin

Return loss @ 5 GHz ≥ 12 dB

Crosstalk (NEXT + FEXT) @ 5 GHz ≤ −20 dB

Contact resistance drift after 100k cycles ≤ 20% nominal

Die Cut Marks + IC Tabs — Three Classes of Cut

1. Scribe Lines

Parameter Value

Purpose Clean dice separation for hand-break (M-grade / education / bring-up)

Penetration ~50% through die thickness

Laser fluence 30% of full-cut fluence

Kerf width 10–20 μm

DICER opcode OP_SCRIBE (recommended 0x60)

2. Alignment Fiducials (3 per die)

Fiducial Location Shape Dimensions

Pin-1 Pin-1 corner Circle 100 μm diameter

Diagonal Diagonal corner Cross 100 × 100 μm, 20 μm arm width

Centre Die centre Square 200 × 200 μm

DICER opcode: OP_FIDUCIAL (recommended 0x62). Ablated to full recording-layer depth for reflectivity-change visibility.

3. IC Tabs

Parameter M-Grade H-Grade

Tabs per die 2 (pin-1 + opposite corner) 4 (one at each corner)

Pin-1 tab dimensions 1.5 × 1.0 mm 2.0 × 1.5 mm

Other tab dimensions 1.0 × 1.0 mm 1.5 × 1.5 mm

Tab depth 0.4 mm 0.6 mm

Tab material Same substrate polycarbonate as the die (cut from die outline)

DICER opcode OP_TAB (recommended 0x64)

Firmware delta (estimated) ~200 lines of C

Impact on DICER Production Time

Grade Outline-Only Dice Time With V2 Features Overhead

M-grade (full disc) 3–8 minutes 10–30 minutes 25–40% additional

H-grade (full disc) 4–12 minutes 6–15 minutes 25–40% additional

The Physical Card — WPD-ACCEL-CARD-4

Parameter Value

Bus interface PCIe 5.0 ×8

Form factor (4-socket) Half-height / half-length (HHHL), 167 × 111 mm

Form factor (8-socket variant) Full-height / full-length (FHFL), PCIe 5.0 ×16

PCB 10-layer, Panasonic Megtron 6 low-loss

Bus master AutoPhi 1Z-Edge WPD dual-persona (FCBGA-576, 25 × 25 mm)

Socket count 4 V2 pinned sockets (M-grade reference)

Hyperthreading fabric Star topology per Project 57 inventions 1455–1458

DDR4 buffer Micron MT40A512M16, DDR4-3200 ×16, 8 Gbit (NVMe write cache for CSD persona)

Boot / firmware flash Micron MT25QL512, 512 Mbit SPI NOR (both persona images)

Card ID EEPROM Microchip AT24C64 on PCIe SMBus

Per-socket VDD_CORE regulators 4 × TI TPS543C20 (12 V → 1.0 V buck)

Shared VDD_IO buck TI TPS62933 (1.8 V)

DDR4 rail regulators TI TPS53819 (1.2 V VDD + 2.5 V VPP)

Persona-select strap R1, R2 (0 Ω populated = CSD; DNP = ACCEL)

LED indicators D1 GRN (CSD active), D2 BLU (ACCEL active), D3–D6 YEL (per-socket occupied)

AUX power J6 PCIe 6-pin (optional, DNP if TDP

Schematic KiCad 10 — 89 components, 74 nets

PWR_FLAG markers 16 (one per power rail)

ERC result 0 errors, 0 warnings

BOM cost estimate ~$240 per card at 1,000-card volume (excludes AutoPhi 1Z-Edge + pinned sockets + inset PCBs)

Persona Selection (R1, R2 Strap Resistors)

R1 Populated? R2 Populated? Persona Windows Driver

Yes (0 Ω) Yes (0 Ω) CSD stornvme.sys (in-box) + Computational Programs extension

No (DNP) No (DNP) ACCEL Custom wpd_accel.sys KMDF driver

Yes No Reserved —

No Yes Reserved —

Power Domains (16 Rails)

Rail Nominal Source Consumers

12V 12 V PCIe edge Buck inputs

3V3 3.3 V PCIe edge Housekeeping, pull-ups

3V3AUX 3.3 V PCIe edge (aux) Flash + EEPROM (persistent)

VDD_CORE_0V85 0.85 V External regulator AutoPhi core

VDD_IO_1V0 1.0 V External AutoPhi I/O

VDD_MEM_1V1 1.1 V External AutoPhi memory

VDD_PLL_1V0 1.0 V External AutoPhi PLL

VDD_IO_1V8 1.8 V U8 buck All 4 sockets (shared)

VDD_ANA_1V0 1.0 V Buyer sources All 4 sockets (shared analogue)

SCKT[0–3]_VDD_CORE_1V0 1.0 V U4–U7 (per socket) Per-socket VDD_CORE

1V2_DDR 1.2 V U9 DDR4 buffer VDD

2V5_DDR 2.5 V U9 DDR4 buffer VPP

GND 0 V — Return

WPD-ACCEL-CARD-4 Full Bill of Materials

Ref Value Manufacturer Part Number Package Qty

U1 AutoPhi 1Z-Edge WPD dual-persona bus master cri-one.com AUTOPHI-1Z-EDGE-WPD FCBGA-576 25×25 mm 1

U4–U7 TI TPS543C20 per-socket VDD_CORE buck TI TPS543C20A0RVFR QFN-50 5×5 mm 4

U6 Micron MT40A512M16 DDR4-3200 ×16 8 Gb Micron MT40A512M16LY-062E:E BGA-96 10.5×10.5 mm 1

U8 TI TPS62933 shared VDD_IO buck TI TPS62933FDRLR QFN-13 3×3 mm 1

U9 TI TPS53819 DDR4 rails TI TPS53819ADSR QFN-32 5×5 mm 1

U10 Micron MT25QL512 512 Mbit NOR flash Micron MT25QL512ABB8ESF-0AAT SO-8 1

U11 Microchip AT24C64 card ID EEPROM Microchip AT24C64D-SSHM-B SOIC-8 1

J1–J4 V2 pinned sockets (M-grade) Yamaichi IC189-XXXX V2_SOCKET_M_144BALL 4

J5 PCIe 5.0 ×8 edge connector — — Card-edge 1

J6 PCIe 6-pin AUX power (DNP) Molex 45558-0002 Through-hole 1

C1–C12 100 nF X7R 0402 (AutoPhi bypass) Murata GRM155R71H104KE14D 0402 12

C13–C16 4.7 μF X5R 0603 (AutoPhi bulk) Murata GRM188R60J475KE19D 0603 4

C17–C30 100 nF X7R 0402 (housekeeping) Murata GRM155R71H104KE14D 0402 14

C31–C34 4.7 μF X5R 0603 (per-socket bulk) Murata GRM188R60J475KE19D 0603 4

C35–C36 22 μF X5R 0805 (DDR4 bulk) Murata GRM21BR61A226ME51L 0805 2

R1–R2 0 Ω persona-select strap Yageo RC0603FR-070RL 0603 2

R3–R4 10 kΩ persona strap pull-ups Yageo RC0603FR-0710KL 0603 2

R5–R6 10 kΩ I²C pull-ups Yageo RC0603FR-0710KL 0603 2

R7–R10 10 kΩ SPI boot flash pull-ups Yageo RC0603FR-0710KL 0603 4

R11–R16 330 Ω 0603 LED limiters Yageo RC0603FR-07330RL 0603 6

D1 LED GRN (CSD persona active) Vishay VLMTG7100-GS08 0603 1

D2 LED BLU (ACCEL persona active) Vishay VLMB1300-GS08 0603 1

D3–D6 LED YEL (per-socket occupied) Vishay VLMY1300-GS08 0603 4

FLG1–FLG16 PWR_FLAG (schematic only) — — — 16

PCB 10-layer PCIe 5.0 low-loss card — Panasonic Megtron 6 167×111 mm HHHL 1

Bracket PCIe standard bracket (single-slot) Intel MFC-04-05 — 1

WPD-CSD Persona — Computational Storage Device

Parameter Value

Protocol NVMe 2.0 over PCIe 5.0 ×8

Windows driver stornvme.sys (Microsoft in-box); no custom class driver required

Windows version Windows 11 24H2+ / Windows Server 2022+

Extension Computational Programs command set (NVMe TP4091)

Namespace layout 1 admin + N data namespaces (N = populated socket count)

PCIe class code 01h (Mass Storage) 08h (Non-Volatile Memory)

PCI vendor ID (reference) 0x1D7F (placeholder — buyer registers with PCI-SIG)

PCI device ID (reference) 0xC5D0

CSD Computational Programs Opcodes (Reference)

Command Type Opcode Function

Program Load Admin 0xE0 Uploads a .wpprog to device

Program Delete Admin 0xE1 Removes an uploaded program

Program List Admin 0xE2 Enumerates uploaded programs

Compute Submit I/O 0xD8 Submits a compute job against LBA range

Compute Status I/O 0xD9 Polls job status

Compute Result I/O 0xDA Retrieves job result

CSD Reference Performance Targets (Design, Not Measured)

Configuration Random 4 KB IOPS Sequential Throughput

4-socket M-grade 100,000 1 GB/s

8-socket H-grade 800,000 8 GB/s

CSD Reference Use Cases

Encrypted-at-rest storage with in-drive decrypt (only decrypted plaintext streams to host)
Compressed-at-rest storage with in-drive SQL / KV query engine
Video archive with in-drive frame-extraction / re-encoding
Log storage with in-drive grep / regex filter

WPD-ACCEL Persona — Computational Accelerator

Parameter Value

Bus PCIe 5.0 ×8

Windows driver Custom KMDF — wpd_accel.sys (buyer writes and signs via WHCP)

Windows class System / Other System (PCI class 08h 80h)

PCI device ID (reference) 0xAC10

Queue model Command / completion queue pair per socket (per die)

DMA WdfCommonBufferCreate , 4 KB alignment; PCIe 5.0 supports 2 MB and 1 GB IOMMU pages

Interrupt MSI-X vector per completion queue

Load balancing socket_hint = 0xFFFFFFFF for round-robin; pin to specific socket for latency-sensitive workloads

Optional backend DirectML for Windows AI framework / Windows Copilot / Windows AI Foundry

ACCEL IOCTL Interface

IOCTL Code Method Function

IOCTL_WPD_SUBMIT 0x800 METHOD_BUFFERED Submit compute job

IOCTL_WPD_WAIT 0x801 METHOD_BUFFERED Wait for job completion

IOCTL_WPD_RESULT 0x802 METHOD_OUT_DIRECT Retrieve job result

IOCTL_WPD_QUERY_SOCKETS 0x803 METHOD_BUFFERED Enumerate socket status

ACCEL Reference Use Cases

Bulk crypto — AES / SHA / hash operations offloaded from host CPU
DSP — FIR filter arrays, DFT/FFT, waveform generation
Small-model inference — INT8 CNN, small transformer heads, embedding lookups
Codec offload — H.264 / H.265 partial decode helpers

ACCEL Sample Launch Programs (from Project 57)

WPIC-AES-CORE — AES-128 encrypt
WPIC-SPI-DAC-01 — 12-bit SPI DAC waveform generation
WPIC-PWM-01 — 4-channel PWM
INT8 convolution kernel

Windows Driver Stack

Persona Driver Source Enumerates As Windows Class

WPD-CSD stornvme.sys (Microsoft in-box) + optional CP extension NVMe drive Storage

WPD-ACCEL Custom wpd_accel.sys (KMDF) Compute accelerator System

User-Mode SDK

Two DLLs, one shared C header ( wpd_sdk.h ):

DLL Persona Key Exports

wpd_sdk_accel.dll ACCEL wpd_accel_submit() , wpd_accel_wait() , wpd_accel_result() , wpd_accel_release() , wpd_accel_socket_status()

wpd_sdk_csd.dll CSD wpd_csd_upload_program() , wpd_csd_delete_program() , wpd_csd_list_programs() , wpd_csd_submit_compute() , wpd_csd_poll_status()

Common API: wpd_enumerate() , wpd_open_index() , wpd_close() . Cross-language wrappers planned: Python ( pywpd , ctypes), C++ (header-only RAII), C# (.NET P/Invoke), Rust ( wpd-rs crate).

On-Device Firmware

Firmware runs on the AutoPhi 1Z-Edge bus master. Language: C. Two persona images share a common base runtime; each is stored in NOR flash and selected at boot by the persona-strap resistors.

Firmware Module Structure

Module Path Function

shared/boot.c Cold boot, strap read, persona select

shared/pcie_root.c PCIe 5.0 ×8 endpoint bring-up

shared/hyperthreading.c Bus master hyperthreading fabric

shared/socket_mgmt.c Per-socket enumeration, VDD_CORE sequencing, TSENSE monitoring

shared/ddr4.c DDR4 buffer init + refresh

shared/flash.c NOR flash driver (Micron MT25QL512)

shared/logging.c Persistent event log + host telemetry

csd/nvme_front.c NVMe 2.0 admin queue + I/O queue front-end

csd/nvme_identify.c Identify Controller + Namespace responders

csd/nvme_readwrite.c Standard NVMe read / write / flush handlers

csd/nvme_compute.c Computational Programs command handlers (0xE0–0xE2 admin, 0xD8–0xDA I/O)

csd/program_registry.c Uploaded program storage + dispatch

csd/main_csd.c CSD persona main event loop

accel/mmio_queues.c Command / completion queue MMIO front-end

accel/job_scheduler.c Round-robin / hint-honouring job dispatch to sockets

accel/directml_backend.c Optional DirectML operator mapping

accel/main_accel.c ACCEL persona main event loop

Hyperthreading Dispatch API (Shared)

Function Purpose

socket_load_program() Stream write program to socketed die via HTH_PROG_LOAD opcode

socket_start_job() Start job on a specific socket via HTH_JOB_START opcode

socket_wait_completion() Wait for die completion signal

socket_read_result() Read result bytes from socket

Standards Followed

Standard Where Applied

PCI-SIG PCIe 5.0 CEM Card edge, lane routing (85 Ω differential, 5 mil intra-pair skew)

NVMe 2.0 CSD persona wire protocol

NVMe TP4091 (Computational Programs) CSD persona compute submit

Windows KMDF ACCEL persona driver framework

DirectML (optional) ACCEL persona AI framework backend

JEDEC BGA outline Pinned socket underside footprint on host PCB

IPC-6012 Class 2/3 Card + inset PCB fabrication

UL 94 V-0 Socket body plastic, copper-clad laminate

RoHS / REACH Socket compliance

IEC 60068-2-27 Mechanical shock (buyer certifies)

IEC 61000-4-2 ESD contact discharge ± 6 kV (buyer certifies)

Certification & Compliance (Buyer Scope)

Certification Body Scope

PCIe 5.0 compliance PCI-SIG Finished card physical + electrical

NVMe compliance (CSD) NVM Express Interop workshop, opcode assignment

Windows HLK Microsoft WHCP Storage Adapter (CSD) or System class (ACCEL)

Driver signing Microsoft Attestation (

UL 60950-1 / IEC 62368-1 UL / CE Consumer / commercial use

FCC Part 15 Class B / CE FCC / EU Consumer market

Portfolio Dependencies

Sibling Project Role

Project 57 — WritePhi Writer + dicer + blank family + design library — dies come from here

Project 18 — AutoPhi Future Bus master silicon architecture

Project 23 — AutoPhi 1Z Accelerator Reference die-side compute target

Project 39 — AutoPhi PCIe5-256 Optional portfolio-native host board

Project 44 — AutoPhi PCIe5-1536 Optional high-density host board

Project 58 is arms-length from Project 57 per portfolio firewall. Same architecture family (both use WritePhi dies + AutoPhi 1Z-Edge). Separate SKUs, separate contracts, separate revenue streams.

Pricing — Sellable-Parts Structure

The store sells downloadable engineering-package blueprints , not physical hardware. Buyer picks the specific blueprint(s) they want. Each sub-blueprint ships as its own self-contained zip.

Study Tier — Four Per-Part Blueprints

Personal + educational use only; no commercial rights.

SKU Name Contents Downloadable Price (USD)

WPD-STUDY-V2 WPD Study — V2 Package Blueprint V2 package overview + inset PCB + pinned socket + die cut marks + IC tabs specs wpd-v2-package.crione.zip $1,250

WPD-STUDY-CARDS WPD Study — Reference Cards Blueprint WPD-ACCEL-CARD schematic + INSET-PCB-M schematic + BOMs + SPECs wpd-accel-card.crione.zip $1,250

WPD-STUDY-WINDOWS WPD Study — Windows Driver Plans NVMe CSD driver plan + KMDF ACCEL driver plan + user-mode SDK plan wpd-windows.crione.zip $1,250

WPD-STUDY-FIRMWARE WPD Study — Firmware Blueprint On-device firmware overview (bus master + persona firmware) wpd-firmware.crione.zip $1,250

Full + Commercial + OEM Tiers

SKU Name Downloadable License Price (USD)

WPD-STUDY-FULL WPD Study — Full WPD Blueprint wpd.crione.zip Personal + educational $1,499

WPD-COMMERCIAL WPD Commercial Blueprint License wpd.crione.zip Build and sell + WHCP driver signing $49,999

WPD-BUILDHELP WPD Build-Help + Commercial License wpd.crione.zip + support voucher Commercial + inventor support + HLK guidance $500,000

WPD-OEM-ENGPKG WPD OEM Engineering-Package Acquisition wpd.crione.zip + contract PDF Full commercialisation + trademarks + hand-off $12,750,000

Also included at no extra charge inside All In One (20T) — the complete cri-one.com portfolio acquisition.

Downloadable Archive Details

Archive Size Files SHA-256

wpd.crione.zip ~90 KB 34 60f4ceafa922...c448

wpd-v2-package.crione.zip ~15 KB 9 6df5fb5d74c3...2dff

wpd-accel-card.crione.zip ~49 KB 13 e12af53dc1c3...7f19

wpd-windows.crione.zip ~12 KB 9 d227a61635b1...ef93

wpd-firmware.crione.zip ~6 KB 6 c926f1536bb7...4af3

What Is in the Package

The full engineering package ( wpd.crione.zip ) contains 34 files across the following categories:

Top-Level Documentation (10 files)

README.md — project overview and reading order
WPD_CONCEPT.md — vision document: why both personas share one card
PRODUCT_BRIEF.md — one-page buyer brief
SPEC.md — top-level device specification (revision 0.1)
STATUS.md — honest maturity report
LICENSE.md — what conveys, what is retained
STORE_LISTING.md — store listing brief
MANIFEST.json — machine-readable project manifest
HANDOFF.md — session state and pickup queue
CONTACT_INFO.txt — inventor contact details

V2 Package Hardware Specifications (4 files)

hardware/V2_PACKAGE_SPEC.md — V2 package overview (assembly flows: factory, buyer, field replacement)
hardware/INSET_PCB_SPEC.md — die-carrier PCB specification (M-grade + H-grade dimensions, ACA bond zone, IC tabs)
hardware/PINNED_SOCKET_SPEC.md — pinned socket specification (Socket-M + Socket-H, pogo pins, cam lever, BGA underside)
hardware/DIE_CUT_MARKS_SPEC.md — scribe lines, alignment fiducials, IC tabs ( OP_SCRIBE , OP_FIDUCIAL , OP_TAB opcodes)

Reference Schematics — WPD-ACCEL-CARD-4 (4 files)

hardware/WPD_ACCEL_CARD/wpd_accel_card.kicad_sch — KiCad 10 schematic (89 components, 74 nets, 221,947 bytes)
hardware/WPD_ACCEL_CARD/gen_schematic.py — Python generator (imports _factory.py from Project 57)
hardware/WPD_ACCEL_CARD/BOM.csv — bill of materials
hardware/WPD_ACCEL_CARD/SPEC.md — board-level specification

Reference Schematics — INSET-PCB-M (4 files)

hardware/INSET_PCB_M/inset_pcb_m.kicad_sch — KiCad 10 schematic (18 components, 20 nets, 51,432 bytes)
hardware/INSET_PCB_M/gen_schematic.py — Python generator
hardware/INSET_PCB_M/BOM.csv — bill of materials
hardware/INSET_PCB_M/SPEC.md — board-level specification

Windows Driver Plans (4 files)

windows/README.md — driver stack overview (persona-to-driver mapping, enumeration table, reference architecture)
windows/nvme_csd_driver/README.md — NVMe class driver plan (CSD persona)
windows/kmdf_accel_driver/README.md — KMDF driver plan (ACCEL persona, IOCTL definitions, DirectML backend)
windows/userspace/README.md — user-mode SDK plan (shared header + per-persona DLLs + code example)

Firmware Overview (1 file)

firmware/device_firmware/README.md — on-device firmware architecture (shared runtime + CSD persona + ACCEL persona, boot sequence, event loops, socket dispatch API)

Technical Figures (6 files)

figures/wpd_hero.svg — family hero diagram (both personas)
figures/wpd_v2_hero.svg — V2 package cross-section diagram
figures/wpd_cards_hero.svg — reference PCIe 5.0 card block diagram
figures/wpd_windows_hero.svg — Windows driver stack diagram
figures/wpd_firmware_hero.svg — on-device firmware architecture diagram
figures/gen_images.py — SVG figure generator

Documentation (1 file)

docs/JARGON_LEVELS.md — four explanations at different knowledge levels (Newcomer, Practitioner, Engineer, Architect)

What Conveys and What Does Not

What conveys with purchase:

The complete text of every file in the engineering package as delivered
Worldwide, non-exclusive commercialisation rights to make, use, and sell products built from the disclosed technologies (WPD-CSD, WPD-ACCEL, V2 package, inset PCB, pinned socket, cut marks + tabs)
The right to modify, extend, and derive works from the delivered materials

What does NOT convey (retained by the inventor at every tier):

The underlying patents, prosecution rights, and enforcement rights
The V2 package invention record
All Project 57 (WritePhi) IP — writer, dicer, blanks, design library
Master IP catalog entries
Framework filing USPTO Application No. 19/693,405
AutoPhi 1Z-Edge and related AutoPhi IP
Trademarks including “WPD-CSD”, “WPD-ACCEL”, “WPD-DEVICE”, “V2 Package”

This is not a patent licence and not a patent assignment. This is a documentation + commercialisation-rights transaction.

Field Replacement (Under 60 Seconds, Tool-Free)

Power down the host.
Rotate cam-lever cap open on the target socket.
Pop the inset PCB out (fingernail leverage on the designed pull tab, or standard IC extractor).
Insert a new inset PCB carrier.
Rotate cam-lever cap closed.
Power up host.

No cleanroom. No PCB rework. No soldering iron. Individual dies are user-replaceable in the field.

Terms

Available only to companies incorporated, headquartered, and primarily operating in the United States of America.
All transactions in USD only.
Final sale — all payments final, non-refundable, non-recoverable.
Governing law: State of Georgia, USA. Venue: Gwinnett County.
Communication by email and postal mail only. No phone calls, no brokers, no intermediaries.
The engineering package is provided as-is. Performance figures are design targets, not measured guarantees.
Liability limited to the amount actually paid for the package.

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

Diagram 'WritePhi Devices - one card, two Windows personas'

Footnotes

Product number 8508.
Family: fabrication writephi.
Purchase: When you buy, you buy the use of that blueprint only.

Reviews

Write Your Own Review