Extended catalog & full narrative — WritePhi-2 Complete Package

The extended dossier appended from the 2026-08-05 catalog snapshot. Prices in the body copy have been stripped; the live-store price on this page is the authoritative figure. Images have been omitted.

WritePhi-2 Complete Package

(USD). The full WritePhi-2 (Project 79) Design + Product License Package. Photonic quantum compute in a memory slot, engineered end-to-end.

What WritePhi-2 IS

WritePhi-2 puts a photonic quantum compute engine into a standard JEDEC DDR5 DIMM socket. Developers write designs in WritePhi-Q, a three-tier programming language: photonic primitives for the engineer, quantum gates for the algorithm developer, and memory-cell compute-in-memory tiles for the application developer. All three tiers lower through a single intermediate representation (PQIR) into the WritePhi optical-processing SDK (inventions 1443-1447), which produces a write program the WritePhi Writer inscribes onto a Q-Blank — a Blu-ray-envelope photonic substrate with a purpose-built recording chemistry.

The written disc is diced, edge-polished, coupled via a V-groove fibre array to a small CXL 3.0 bridge board carrying a photonic transceiver and a classical control CPU, and assembled into a WPQ-DIMM. Plugged into any CXL 3.0-capable server (Sapphire Rapids and later, EPYC 9004 and later, or any CXL 3.0 memory-expansion socket) the DIMM enumerates as a Type-2 memory-semantic device. The host maps its tile address space; writes trigger photonic quantum compute; reads pull classical results.

What is included in the Bundle

• Complete engineering documentation. CONCEPT, WRITEPHI_Q_LANGUAGE (the three-tier language + PQIR spec), SPEC (the DIMM hardware + CXL 3.0 protocol + Q-Blank recording-chemistry requirements + disc-coupling paths), STATUS (honest subsystem-by-subsystem maturity), WHY_NOW (the memory-shortage and domestic-manufacturing thesis), PLAYBOOK (an eight-phase buyer how-to from Q-Blank chemistry selection through pilot assembly-site standup), and STORE_LISTING.
• The wpqc reference compiler. Working Python compiler that parses a Tier-2 WritePhi-Q source, emits PQIR text with source-line annotations and stdlib version pins, and demonstrates the lowering discipline end-to-end. Ships with a Bell-pair example and the generated PQIR.
• Reference schematics and hardware specs. Bridge PCB component selection (CXL 3.0 controller, quad-core ARM Cortex-A55 or AutoPhi Modern soft core, 12-channel WDM photonic transceiver, V-groove fibre array footprint, DDR5 edge-connector fingers). Q-Blank recording-chemistry candidate matrix (Ormocer / chalcogenide / photorefractive sol-gel) with selection criteria.
• Manufacturing playbook. Phased buyer plan through chemistry selection (weeks 1-6), first-write bring-up (weeks 7-10), bridge PCB fabrication (parallel), first-DIMM assembly (weeks 13-16), first customer application (weeks 17-24), and pilot assembly-site standup (months 4-9). Sixteen direct manufacturing jobs per assembly site per shift, community-college-trainable.
• Priority-date documentation. Filing-ready records for Project 79 inventor-record entries 79-A through 79-H at 2026-08-04 priority.
• Worldwide commercialization rights for the manufactured WPQ-DIMMs.

Who buys the Bundle

Cloud & hyperscaler infrastructure teams looking for HBM-free memory-slot compute for the workloads that map to unitary operations — attention, low-rank matmul, FFT, search — without competing with everyone else for HBM3E allocation.

AI training & inference platforms that want quantum-matmul at photonic clock rates as a compute-in-memory offload, with the design pinned and versioned so the same Q-Blank produces the same numerics run after run.

Defense and signal-processing programs that need on-premises, air-gap-compatible photonic quantum compute with the disc written at the buyer's own site — no cloud dependency, no foreign fab dependency, no cryostat.

Research universities that want an accessible photonic quantum platform that fits in a workstation, without a dilution refrigerator or a physics-department overhead structure.

Why now

The HBM/DRAM oligopoly (three companies produce ~95% of DRAM globally) has 12-18 month lead times through the rest of the decade. Every AI training rack is memory-bandwidth-limited before it is compute-limited. Every defense buyer accepts whatever HBM the hyperscalers do not absorb. WritePhi-2's supply chain runs on a different substrate entirely: BDXL polycarbonate blanks (mature commodity, ~40% underutilized industry-wide because physical-media demand declined), commodity CXL silicon, standard PCB assembly. Not one line of the BOM requires HBM, DRAM, or a leading-edge silicon fab.

Payment structures

One-time payment at USD is the primary path. Also negotiable: installments over 3-60 months, milestone-based tied to Playbook phase exits, royalty structures on manufactured DIMMs, and revenue share on the WPQ-Library subscription revenue. Payment does not affect the IP retention rule.