Computational Storage
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
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The chip that puts compute behind the lock, not beside it.
A single-die NVMe SSD controller with the compute engine bolted onto the inside of the encryption boundary — not outside it. Plaintext never leaves the apparatus. The host fires a single NVMe doorbell. The answer comes back; the bytes don't.
Three pillars
Tweak = physical-page address
AES-256-XTS keyed by the packed physical-page address of the NAND page, not by the host LBA. Re-write the same plaintext after wear-leveling and the ciphertext changes. Forensic bind to physical location is automatic.
One FTL, one path
The compute engine reads through the same FTL and the same AES-XTS path the host uses. No parallel data path, no duplicated key store, no second tweak function. A reserved-CID arbiter shares the command port without leaking compute reads onto the host completion queue.
One doorbell, one CQE
The host invokes near-data compute through a single NVMe vendor opcode (0xC1). The engine parses the SQE, holds the CID, runs the op, and synthesises a single completion-queue event carrying the result. No side-channel control surface. Standard NVMe drivers talk to it.
The headline numbers
How it’s better
The chart below isn’t against any particular vendor — it’s against the assumptions that conventional computational-storage drives bake in. Where we say "typical," we mean the architectural shape you find in most shipping or published designs.
| Question | Project 50 (AutoPhi) | Typical computational SSD |
|---|---|---|
| What is the AES-XTS tweak? | Packed physical-page address (channel/die/block/page). Ciphertext binds to physical location. | Host LBA. Same plaintext at same LBA encrypts identically through wear-leveling. |
| Where does the compute engine read from? | The same FTL command port the host uses, through the same AES-XTS path. One source of truth. | A separate path, often bypassing the host’s FTL and either replicating keys or operating on ciphertext. |
| How does the host invoke compute? | A single NVMe doorbell write with vendor opcode 0xC1. Standard NVMe stack, no proprietary driver path. | Proprietary API, sidechannel mailbox, or a non-NVMe interface that bypasses the kernel block stack. |
| Where does the compute result come back? | As a single NVMe completion-queue event. Indistinguishable in shape from a normal completion. | Through a vendor-specific channel that the kernel NVMe layer doesn’t know about. |
| What stops compute reads from polluting the host CQE? | CID filter: reserved range 0xE000…0xEFFF. Compute reads are filtered before they ever reach the MSI-X path. | Usually doesn’t apply — the parallel path doesn’t share the CQE. |
| Are the keys readable after load? | No. Load once at power-on; no host-accessible port surfaces either key afterward. (WonderPhi AES, Commandment VIII.) | Varies. Self-encrypting drives commonly expose a key-wrap surface or a TCG/Opal interface that the controller can read. |
| What proves it works today? | Six iverilog testbenches passing end-to-end, named in the patent specification. Reproducible from the RTL. | Internal simulation, sometimes a tape-out demo, rarely published source. |
| What is on file? | USPTO non-provisional 19/710,460, filed 2026-06-17. 20 claims, 8 figures. | Mix of granted patents, pending applications, and trade secrets — varies by vendor. |
The point isn’t that any one of these distinctions is impossible to copy. The point is that the three together fit the host’s existing NVMe stack with one doorbell, one CQE, one path, and one key store. The seam that conventional designs leave at the boundary between “storage” and “compute” isn’t there.
What you actually get
Project 50 is offered as a design package, not shipping silicon. The components below are all in the as-filed record.
| Component | What it contains |
|---|---|
| Patent specification (filed) | 20 claims, abstract, 8 figures, reduction-to-practice section naming all six passing testbenches by file. |
| RTL package | NVMe engine, FTL core, AES-256-XTS inline path, ACE compute engine (SCAN/VOXEL/XFORM), ACE-to-FTL bridge, FTL command-port arbiter, behavioral NAND and DRAM models. |
| Testbench package | Six iverilog testbenches: host round-trip, encrypted round-trip, ACE hand-service, ACE structural, ACE doorbell, controller spine. |
| Firmware skeleton | Freestanding C for the in-die microcontroller blocks: regmap, ACE control, key-load sequence. |
| Reference simulator | Python behavioral model (sim/wonderphi/) bit-equivalent to the RTL, runnable on any laptop. |
| Documentation | Architecture description, WonderPhi lineage, walking-status report, this presentation wrapper. |
How it’s licensed
NO IP IS SOLD. IP RETAINED BY CRI-ONE. USE & PERMISSION ONLY. Three tiers, never a Full Acquisition:
Mathematical Deposition
Read-only access to the filed specification and the eight figures.
- Patent spec + claims + abstract
- All 8 USPTO figures
- Architecture overview
Evaluation License
Time-bounded rights for prospective implementers to run the RTL and prove the architecture themselves.
- Everything in Tier 1
- RTL package + testbench package
- Python reference simulator
- Walking-status report
Full Use & Copy License
Production rights to embody the invention in silicon. Inventor designation and patent priority stay with CRI-ONE.
- Everything in Tier 1 and Tier 2
- Firmware skeleton + integration support
- Right to tape-out under the patent
- Inventor named on resulting silicon
Patent record
Compliance & honesty
Patent-pending, not patented. "First to market" here means a documented public-offering record anchored by the USPTO application number above — not a determination of patent priority by the USPTO or any court. This is a design package, not shipping silicon. The reduction-to-practice testbenches run under open-source Icarus Verilog (version 12.0 or later).
Christopher Gabriel Brown — 1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA — Email: crioneaka@outlook.com. Email and postal mail only — no phone calls please.
