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WritePhi Design Toolkit - Python SDK + parametric family builders
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
Free download — the WritePhi Positioning Pack
A 13 KB self-authenticating zip — seven-pillar case, one-page executive summary, shareable quote blocks, filing reference. Print it, forward it, hand it to your team. No account required, no email gate.
SHA-256: e5b79f5eb179…62a26bbc
Why Only WritePhi Can Do This
Every player in silicon design owns part of the pipeline from idea to physical medium. WritePhi is the only shipping product that owns the whole pipeline as one atomic, verified, patent-covered operation. Seven things nobody else can do to a chip design tonight:
1Author chip topology as native X-Y-Z coordinates against physical dye layers
Every commercial EDA format is abstract layer numbers with no physical grounding. GDSII, OASIS, LEF/DEF — all abstractions the foundry has to map back to real geometry. .wscribe says “this transistor gate lives at x = 1.23 mm, y = 4.56 mm, on the middle recording layer of a BDXL disc at z = 0.175 mm” from the very first line. The medium is the coordinate system. That is a category nobody else authors in.
2Chain verification and optical write as one atomic operation
Every commercial EDA vendor gates on simulation. Every foundry gates on DRC and LVS. Nobody chains simulation pass → optical burner spins as one atomic operation where three orthogonal asserts (ROM byte-for-byte + ALU testbench + program semantics) must all pass before the disc gets pressed. That is exactly what USPTO utility patent application 19/731,098 covers.
3Land compute + firmware on ONE die from ONE source file
The industry treats synthesis and firmware bring-up as two universes. A commercial MCU has silicon from Vendor A and firmware from Vendor B stitched over JTAG. Our bake_mcu.py takes a compute design and a bytes payload and emits a single .wscribe where the ALU and the BIOS-ROM live on the same physical die at neighboring X-coordinates. One source file. One die. One disc. Verified together.
4Ship self-authenticating physical media
Every WritePhi disc ships with its own decoder, its own verifier, and its own SHA-256 manifest baked into the payload. Insert the disc into any Python-capable computer — the disc proves itself. No dongle. No online activation. No vendor account. The disc is the proof of authorship.
5Use consumer optical burners as the physical write path
Electron-beam lithography is $10 million and a cleanroom. Photolithographic mask sets are $500,000 and a foundry booking. LightScribe is public-domain but paints monochrome labels, not topology. WritePhi uses commodity DVD and Blu-ray burners — the same Primera Bravo, the same PTPublisher, the same $200 hardware — but points the beam at chip topology instead of album art. Public-domain physical write path, patent-covered software pipeline on top.
6Sell an EDA-scale toolchain as one-time-purchase Python
Commercial EDA is seat-licensed rental. Your designs live in proprietary formats you cannot open without an active license. WritePhi is a one-time purchase that runs on any Python interpreter, forever. Your designs are in plain-text .wscribe any editor can open, and a fully-documented .wpprog v2 binary format any Python script can parse. Your files never expire.
7Compress the chip-design feedback loop into a Sunday afternoon
Author → switch-level verify → bridge to .wscribe → compile to ISO → burn on the Bravo → readback verify → hold a chip-design disc in your hand. That entire loop is measured in one focused session, not tape-out cycles measured in weeks. Nobody else compresses the chip-design feedback loop that hard, because nobody else uses a consumer optical burner as the physical write step.
What this means competitively
Every player upstream and downstream has to route through WritePhi if the market decides that verified-topology-on-consumer-optical-media is a real category. Foundries own the fab but not the language. EDA vendors own the tools but not the medium. Optical-drive OEMs own the burners but not the topology. LightScribe owns the physics but not the verification gate. WritePhi controls the category because WritePhi invented the language the category is spoken in.
USPTO utility patent application 19/731,098 · Confirmation 5973 · Patent Center 78285110 · Framework filing 19/693,405
Design-production throughput
Comparison charts
Performance is compared to performance; the medium chart compares media cost only. No external vendor sells its IC or quantum design at any price — cri-one.com entries are the only designs on these charts that can be purchased. Full landscape + methodology: the Charts page.
Disc / storage media (cost of medium only)
Classical + hybrid IC tier (performance to performance)
Quantum tier (cost to operate, per hour)
WritePhi Design Toolkit
The Python SDK + CLI toolkit that generates every WPIC-* design on cri-one.com. For the same price as one design, get the tools to make all of them.
What ships
- writephi_sdk/writephi/ - Design, Simulator, TestBench, compile_design, 10 family builders
- tools/ - parametric_sweep, autoloop_v2 (multi-core), render_die, build_burn_payload, build_sweep_index, loop
- ic_designs_examples/ - 8 hand-written IC references including WPIC-ALU-08
- sweep_examples/ - 5 example sweep outputs showing what parametric_sweep produces
- Full README + LICENSE + USPTO 19/731,098 filing reference
Instant download. 174 KB zip. Zero pip dependencies. Stdlib Python 3.10+. Runs on Windows/Linux/Mac.
10 parametric family builders
writephi.families: counter_N, adder_N, register_N, mega_N, multiplier_N, fsm_N, memory_N, fifo_N, alu_N, mac_unit
Performance
- Switch-level CMOS simulator with 4,096-iter fixed-point solver
- .wpprog v2 compiler with 32-bit net IDs (up to 4 billion nets/design)
- Multiprocessing autoloop fans across every CPU core (80-core = 80x throughput)
- Generated 193 verified designs (5.1M FETs) in ~30 seconds on a 32-core run
- Every design ships with SHA-256 hash + full topology JSON + waveform snapshot
What this is
The factory - not one nail, but the hammer that drives every nail. The same tools cri-one.com uses to generate the WPIC-* library, packaged for your own use.
What is NOT conveyed
No intellectual property is conveyed. Ever. All patents, patent applications, copyrights, trade secrets, know-how, and other IP retained in full by the inventor. Buyer is granted the right to install, run, generate designs on Buyer's own machines, and study source for educational or internal research purposes. NO patent license. NO right to fabricate, tape out, or manufacture silicon. NO right to sell, sublicense, redistribute, or commercially exploit the toolkit or its outputs. Commercial exploitation requires separate written agreement with inventor.
Estimated ceiling and upgrade path (formal statement)
In addition to every other statement in this listing, the following performance envelope is formally disclosed to prospective buyers:
- Design size: approximately 10 million transistors per design before pure-Python
solve()becomes uncomfortable on typical hardware. - Format: the
.wpprog v2byte-stream format can address approximately 4 billion nets per design (32-bit net IDs). The bottleneck at large scale is the pure-Python solver, not the format. - C-inner-loop upgrade (~1 day of engineering work): approximately 50-100x faster solve throughput on the same designs.
- CUDA upgrade (~1 week of engineering work): approximately 1,000-10,000x faster solve throughput, sufficient to simulate 100 million-FET designs in seconds.
These are honest projections based on the current pure-Python implementation. Neither the C inner loop nor the CUDA kernel ships in the current release. Buyer is welcome to implement either upgrade under the terms of the No IP Conveyed clause (personal / internal research use only; no commercial exploitation without separate written agreement with the inventor).
Terms
- $20,000 USD
- USA only
- Instant download on checkout
- All IP retained by inventor
Filing: Verification-gated compile-and-optical-write pipeline covered by USPTO utility application 19/731,098 (filed 2026-07-05, Confirmation 5973, Patent Center 78285110). Framework filing 19/693,405 covers portfolio-wide claims across 45+ cri-one.com projects.
