WFA Specification + Reference Schematics
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
WFA-SPEC — WiFi Accelerator Specification + Reference Schematics ($9,999)
The evaluation tier of the WiFi Accelerator product line. The full patent-pending specification, the WFA-Node reference-board KiCad schematic, the layout-and-process notes, the foundry-engagement strategy, and every architecture document required to make a build / buy decision about a custom WiFi accelerator program — without committing to silicon, dev-kit hardware, or the full reference design at the higher tiers. The WFA-SPEC tier is engineered for the buyer's evaluation phase: the chip-program manager who needs the specification on her desk before she takes the design to her engineering team; the OEM product manager who needs the architecture documented before he writes the requirements document for his next router; the technology-analyst who needs the design-target evidence in writing before the legal team can shape an engagement.
The problem this addresses
Every team building dense-Wi-Fi cluster gear hits the same wall around eight cooperating peers per radio. Commodity Wi-Fi MCUs — ESP32-S3, Qualcomm AC silicon, MediaTek MT76 family, Intel AX — are excellent at being laptop radios and bad at being the radio inside a rack. The MAC scheduler treats every frame the same way. The TLS path adds tens of milliseconds to every new peer joining. The interrupt rate swamps the host CPU before the rack reaches double-digit nodes. The PHY's standard-compliant 802.11 implementation does its job; the surrounding architecture is the bottleneck.
Replacing the radio is a multi-year, multi-million-dollar program for any greenfield team — and for the right reasons: a real Wi-Fi PHY is hard, a real Wi-Fi MAC is harder, the Standard Essential Patent stack is real, the Wi-Fi Alliance trademark cert is real, and the FCC Part 15 cert is real per shipped product. WFA-SPEC delivers, at the evaluation price point, the design documentation a buyer needs to decide whether the right path for their organization is to adopt the WFA reference design (at the higher tiers), engage WFA as a design-house partner, or build a different solution from a different starting point.
What you get at this tier
- The WFA Specification document (
SPEC.md, ~30 pages typeset). The complete technical specification of the WFA product line: family-at-a-glance comparison of WFA-Node / WFA-Hub / WFA-Mesh; internal block diagram common across all three SKUs; per-block detail of the 802.11ax / 802.11be PHY, the fabric-aware MAC, the hardware fabric framing engine, the crypto cluster (SHA-256, HMAC-SHA-256, AES-256-GCM, X25519, TRNG), the NVRAM burst writer, the aggregated descriptor rings; host integration (SPI, PCIe); conformance and certification path; patent stance. - The WFA Product Brief document (
PRODUCT_BRIEF.md). The non-technical complement to the spec: the why, the what, the how, the design-target performance numbers, the status, the pricing tier structure. - The WFA Strategy document (
STRATEGY.md). The three-project relationship between WiFi Accelerators, UniPhi (the customer for WFA silicon), and AutoPhi (the contract foundry). The pricing rationale. The patent posture. The firewall between the three projects. - The WFA-Node reference-board KiCad schematic (
hardware/wfa_node/wfa_node.kicad_sch). The proposed WFA-Node integrated circuit drawn as a fifty-six-pin custom symbol with every pin labeled by function (power, ground, clock, reset, JTAG, host SPI, host I2C, QSPI flash, RF transmit / receive / TR-switch, status LEDs, watchdog, GPIO). All surrounding circuitry — forty-megahertz crystal, one-point-eight-volt LDO, one-point-two-volt RF buck, sixty-four-megabit QSPI NOR for event log, EUI-48 ID EEPROM, ten-pin Cortex JTAG header, status LEDs, decoupling, test pads, RF front-end, PCB antenna. KiCad-openable; export as SVG or PDF viakicad-cli. - The WFA-Node layout-and-process notes (
LAYOUT_HINT.md). The process target (22-nanometer mixed-signal, QFN-56, fabricated by AutoPhi as a contract foundry job), the die-area budget per internal block, the host-board layout discipline for the high-speed signals (40 MHz crystal placement, RF path length budget, QSPI length-matching, 50 MHz host-SPI termination, decoupling rules, JTAG header layout, TRNG analog discipline, RF ground stitching), and the silicon-bring-up checklist. - The WFA project manifest (
MANIFEST.json). Machine-readable summary of the SKU lineup, the relationships between the three projects, and the file index. - Two clarifying-question email exchanges with the inventor during the evaluation. The buyer's evaluator may email the inventor with up to two clarifying questions about the spec, the schematic, or the strategy. The inventor answers personally and in writing; the answers become part of the evaluation record.
Design target the spec backs
The numbers below are design targets, written into the specification at the register-transfer-level (RTL) contract level. They become measured numbers once first silicon comes back. Commodity-WiFi baselines are measured today on an ESP32-S3 running the UniPhi DC software fabric.
| Metric | Commodity (ESP32-S3) | WFA target |
|---|---|---|
| Deploy latency p99 | ~100 ms | <10 ms |
| mTLS handshake p99 | ~80 ms | <1 ms |
| Replication throughput (16 MB, N=3) | ~23 MB/s | >200 MB/s |
| Concurrent nodes per radio | ~8 practical | 64+ |
| Host CPU at saturation | ~70% | <10% |
What the spec lets a buyer's engineering team conclude
- Whether the WFA approach (hardware fabric framing, on-chip crypto, aggregated descriptor rings, fabric-aware MAC) fits the buyer's product line.
- Which of the three core SKUs (WFA-Node / WFA-Hub / WFA-Mesh) is the right starting point for the buyer's product, given its peer density, throughput target, host bus, and form factor.
- How the buyer's existing platform team would integrate the WFA host bus (SPI / I2C for WFA-Node; PCIe Gen3 ×1 for WFA-Hub; PCIe Gen3 ×2 for WFA-Mesh) — descriptor-ring layout, interrupt model, DMA region requirements.
- What the buyer's commercial path looks like: the cost-and-time tradeoffs of adopting the WFA reference design via BLUEPRINT-PACK versus engaging AutoPhi as the contract foundry for production silicon via FOUNDRY-PARTNER.
What is NOT included at the WFA-SPEC tier
- The right to build a shipping product based on the WFA design. WFA-BLUEPRINT-PACK is the production-ready tier; WFA-SPEC is evaluation.
- The RTL (register-transfer-level) source. The block diagram and the pin contract are documented; the synthesizable HDL stays with the inventor until BLUEPRINT-PACK.
- The design-verification vector library. The DV corpus is part of BLUEPRINT-PACK.
- The dev-kit hardware (ESP32-S3 + FPGA emulating WFA's host bus). WFA-DEV-KIT is the appropriate SKU for buyers who want to write drivers against the WFA protocol today.
- The channel to AutoPhi. Foundry engagement happens at WFA-FOUNDRY-PARTNER.
- Wi-Fi Alliance trademark. Not transferable from WFA; the buyer's organization joins the WFA membership program separately.
- FCC Part 15 certification. Per-product responsibility of the buyer's shipping product.
- Telephone or video support. Email only. Two clarifying questions are included.
- International sale. USA only. USD only.
System requirements
- A modern computer to read PDF and KiCad documents on. KiCad 8 or later if the buyer's engineer wants to open the schematic interactively; any reader for the PDF exports of the same schematic.
- A working email account at which to receive the deliverables packet.
How a buyer typically uses this tier
The buyer's evaluator opens the SPEC.md, reads the family-at-a-glance comparison, identifies the target SKU (Node, Hub, or Mesh), and walks the per-block detail. The evaluator opens the WFA-Node KiCad schematic, confirms the pin contract is sufficient for the buyer's host-side design, and reads the LAYOUT_HINT.md to understand the process target and the host-board discipline. The evaluator reads STRATEGY.md to understand the inventor's commercial framing and the three-project relationship between WFA, UniPhi DC, and AutoPhi. The evaluator may email up to two clarifying questions; the inventor answers in writing. The evaluator writes an internal recommendation and the buyer's leadership decides whether to proceed to BLUEPRINT-PACK, DEV-KIT, or FOUNDRY-PARTNER.
A typical evaluation closes within four weeks. The deliverables packet is retained in the buyer's archive for reference whether or not the buyer proceeds to a higher tier.
How to order
Email christopher@cri-one.com with the subject line WFA — WFA-SPEC. Identify the buyer's organization, the evaluator's name and title, and one sentence of context about the intended product. Payment arrangements by reply. Delivery is by email; the documents and the KiCad schematic file arrive once payment clears.
Postal contact:
Christopher Gabriel Brown
1341 Wellington Cove
Lawrenceville, GA 30043-5255
United States
Patent-pending. USA-only sales. United States Dollars only. Email-only contact.
