AutoPhi V18-Achievement -- Seed Series #41
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
AutoPhi V18-Seed Voxel Processor -- Seed Series #41
The spark that starts it all — the cheapest proof that the architecture works on real silicon — 3 physical qubits hybrid die at 95.3 mW, printable today on an open PDK.
Why this is worth what it costs
Nobody else sells working quantum-classical silicon on these terms. What you are paying for is 15+ years of hybrid quantum-classical R&D, publicly documented since 2010, patent-filed since 2012 — plus the finished mask set.
Competing quantum offerings arrive as a chip surrounded by a companion stack: separate memory controller, PCIe retimer, error-correction ASIC, security co-processor. This die integrates multiple core technologies onto one substrate — including LED power recycling and EM cooling with zero moving parts. Your board design loses parts, your power budget shrinks, and your bring-up time drops from years to months.
Real specifications
- 479.19 KFLOPS Kilo-class peak throughput, 0.002 TOPS AI acceleration
- 3 physical qubits at 93.961% gate fidelity
- 4x4 voxel grid (16 voxels), 2-layer stack
- CPU-only, Lab prototype form factor
- 0.148 GHz clock, 241.3 MB/s memory bandwidth
- 95.3 mW self-sufficient
- Fabricated at SkyWater, 130 nm node
What it is actually for
Target markets: Research labs, university quantum programs, prototyping & evaluation.
Applications: Quantum algorithm development, photonic circuit validation, academic research, proof-of-concept.
Readiness: Ready for OpenLANE — PDK available.
What ships in the license
- GDSII mask layout, foundry-ready
- Gate-level Verilog netlist
- Full RTL: light-CPU core, quantum-CPU core, hybrid top
- LEF / DEF library exchange files
- Synthesis, P&R, DRC/LVS scripts with passing reports
- FOUNDRY_HANDOFF_SIMPLE.txt — everything the fab needs to schedule the mask
- Performance projection sheet and manufacturing documentation
What you own after the sale
The mask set. Fab it at your foundry. Own the wafers.
The SKU line. Name it, price it, distribute it your way.
Derivative rights. Spin variants at other nodes without coming back to CRI-ONE.
Exclusive license for this implementation. No one else can ship this specific die — anywhere in the world — while you hold the license.
Priority-date defense
The foundational AutoPhi architecture is publicly documented from 2010 (Internet Archive) and patent-filed from 2012 (USPTO), under CRI-ONE’s name and independently verifiable. No prior art can invalidate the claims that come with your license.
Fab it where you already build
SkyWater. Standard commercial EDA flow (Synopsys / Cadence). Drops into the 130 nm PDK under NDA — no new tape-out tooling required.
© CRI-ONE. All rights reserved. Patents issued and pending. Unauthorized reproduction of the underlying designs is prohibited.
Extended catalog & full narrative — AutoPhi V18-Seed Voxel Processor -- Seed Series #41
The extended dossier appended from the 2026-08-05 catalog snapshot. Prices in the body copy have been stripped; the live-store price on this page is the authoritative figure. Images have been omitted.
Downloads immediately on checkout — the CD GDSII Generator (AES-256 encrypted). Open with 7-Zip, WinRAR, or macOS Archive Utility using password CRIONE99KEY. Founder Access Pass credit (code FAP99CREDIT) applies at checkout.
AutoPhi V18 Seed 41: 479.19 KFLOPS Kilo-class | 130nm | 3 Qubits | The spark that starts it all
Overview
The AutoPhi V18 Seed 41 is a kilo-class quantum-classical hybrid processor built on the 18-seed voxel DNA architecture at 130nm process technology. It delivers 479.19 KFLOPS peak performance with 0.002 TOPS AI acceleration across a 4x4 voxel grid (16 total voxels) stacked 2 layers deep (1 stack units of 18). Quantum subsystem: 3 qubits at 93.961% fidelity (error rate <6.039%). Clocked at 0.148 GHz with 241.3 MB/s memory bandwidth. Power envelope: 95.3 mW with 0% reduction vs 130nm baseline. Integrates 1/9 AutoPhi core technologies. Three-chromosome DNA encoding: 9-bit electron strand, 1 quantum instructions (atomic strand), 2 photon opcodes (light strand). Light-trigger initiated.
Key Specifications
| Performance | 479.19 KFLOPS (Kilo-class) |
| Process Node | 130nm |
| Clock Speed | 0.148 GHz |
| AI Acceleration | 0.002 TOPS |
| Quantum Subsystem | 3 qubits at 93.961% fidelity (error rate <6.039%) |
| Memory Bandwidth | 241.3 MB/s |
| Power Envelope | 95.3 mW |
| Voxel Grid | 4x4 (16 voxels, 2 layers, 1 stack units of 18) |
| Compute Type | CPU-only |
| Form Factor | Lab prototype |
| LED Power Recycling | 51.3% |
| DNA Encoding | 9-bit electron strand, 1 quantum instructions, 2 photon opcodes |
| Instruction Set | Red=ADD, Blue=SUB |
Target Markets
- Research labs
- university quantum programs
- prototyping & evaluation
Applications
- Quantum algorithm development
- photonic circuit validation
- academic research
- proof-of-concept
Manufacturing & Fabrication
| Foundry | SkyWater |
| PDK | sky130 (open PDK) |
| EDA Flow | OpenLANE (open-source) |
| Readiness | Ready for OpenLANE -- PDK available |
Manufacturing Steps
- Synthesize with OpenLANE + sky130 PDK
- Run P&R -> DRC/LVS
- Package GDSII per FOUNDRY_STANDARDS.md
- Submit to SkyWater for MPW or shuttle
Deliverables
- GDSII (mask layout)
- LEF (library exchange)
- DEF (design exchange)
- Gate-level netlist (Verilog)
- DRC report
- LVS report
- FOUNDRY_HANDOFF_SIMPLE.txt
- RTL (autophi_light_cpu_core.v + autophi_quantum_cpu_core.v + autophi_hybrid_cpu_top.v)
- Synthesis scripts
- P&R configurations
- Manufacturing documentation
- Performance projections
RTL Design Files
autophi_light_cpu_core.vautophi_quantum_cpu_core.vautophi_hybrid_cpu_top.v
Acquisition Path
This product is available through CGB's 4-step acquisition path. The current price is shown in your cart and on the live storefront page.
- Step 1 — Proof of Function: public, each.
- Step 2 — Mathematical Deposition: reading material under mutual NDA.
- Step 3 — Evaluation License: hands-on evaluation under NDA.
- Step 4 — Full Acquisition: full transfer of the design package at the price listed above.