AutoPhi Probability Accelerator — GOPS · Ronna · Quetta, 1,200 nano layers, host offload card, QBeam ExitPhi fabric (App# 19/722,805)
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
The AutoPhi Probability Engine packaged as a host-attached accelerator. Your CPU keeps running; probability work offloads to this card. Same ten-technology engine, same four scaling axes, same measured foot — now it has an address on your bus and a job in your rack.
The offload loop
2.1 Giga fixed-point probability-ops/s — 64 voxels, 130 nm, 150 µW, hash
D61C07EB…D3264697. Real silicon, not a projection.
Four scaling axes — on one card
The accelerator grows along four independent axes. Each multiplies the others:
← OUT → 64 → 480,000 voxels (wider grid per card) ↑ UP ↑ 1 → 512 deposition strata (deeper distributions) × ACROSS × ×1 → ×10⁸ (more cards × racks × facilities) ↓ SMALLER ↓ 130 nm → ~1.5 nm (more per mm²)
The master sauce
Every recipe on the ladder is this formula. The measured foot fills the first slot; each axis multiplies from there.
All ten technologies — ALL FOUR AXES
Every technology serves every scaling axis simultaneously. Not one tech per axis — all ten pushing all four directions at once on the card:
| Technology | OUT (wider) | UP (deeper) | ACROSS (fleet) | SMALLER (node) |
|---|---|---|---|---|
| 0 · Color Math ALU | tile identity | addresses strata | card unit | shrinks with node |
| 1 · LED Power Recycling | powers wider grid | optical budget/layer | rack watts | efficiency at node |
| 2 · Vertical Threading | parallel queries | spans all layers | multi-card pool | more threads/area |
| 3 · Chiplet Stacking | tile bonding | the stacking | multi-die card | finer pitch |
| 4 · Nanophotonic I/O | feeds wider grid | inter-layer light | card-to-card link | waveguide shrink |
| 5 · QEC Surface Code | trust at width | trust at depth | fleet consensus | decoder at node |
| 6 · EM Cooling | thermal at width | thermal at depth | rack cooling | hotspot at node |
| 7 · Quantum Battery | burst at width | burst at depth | facility buffer | density at node |
| 8 · QEU | search width | search depth = layers | fleet sweep | gates at node |
| 9 · Neuromorphic | sparse at width | sparse at depth | event routing | spike at node |
| 10 · QBeam | frame routing | stratum address | host interface | PHY at node |
The temptation of 1,200 nano layers
1,200 deposition strata on Intel 18A, standard die footprint. V20 Epiphany architecture on AES substrate (400 W/m-K thermal conductivity). Physical quantum mechanics: silicon quantum dots (3–10 nm), photon-driven energy storage (E=hf), LED nano-array (8×10¹&sup0; LEDs/cm², 250–300 nm), 84–98% recycling efficiency (Patent 18/370,908). QEC Surface Code gates the recycling loop. EM Cooling prevents thermal runaway. Self-powered — the quantum battery layers make their own energy via photon absorption → re-emission → next stratum loop.
Quantum depth
At 1,200 nano layers the QEU (Tech #8) searches a 1,200-dimensional probability field in hardware — 1,200 conditional layers deep. P(A|B|C|…|Z) nested 1,200 levels. Not just more ops/s — deeper questions answered in one shot. The ladder grows incrementally — each step proves the next is feasible.
| Strata | QEU search depth | What it can evaluate | Step |
|---|---|---|---|
| 1 (PHM01, today) | 1 conditional layer | P(A) — single-variable | BUILT |
| 6 (PHM06) | 6 conditional layers | Six-deep Bayes chain | ×6 |
| 12 (PHM-Q3) | 12 conditional layers | Compound discovery | ×2 |
| 50 | 50 conditional layers | Deep molecular search | ×4.2 |
| 100 | 100 conditional layers | Protein-fold depth | ×2 |
| 200 | 200 conditional layers | Climate-model depth | ×2 |
| 400 | 400 conditional layers | Genomic-field depth | ×2 |
| 800 | 800 conditional layers | Full materials science | ×2 |
| 1,200 (Temptation) | 1,200 conditional layers | Full field — Quetta depth | ×1.5 |
Progressive incremental adjustment: each step is a modest multiple of the last. No single leap — the architecture grows taller one proven increment at a time.
The ladder (signature rungs)
| Rung | Yield | Recipe (axes used) | Class |
|---|---|---|---|
| 1 | 2.1 GOPS | 64 voxels, 130 nm — the foot | (M) |
| ~43 | ~1.58 EOPS | OUT to 480K + SMALLER to ~1.5 nm | (P) |
| ~48 | ~9.45 EOPS | + UP to 6 strata (PHM06) | (P)(R) |
| ~57 | ~6.27 ZOPS | PHM06 + ACROSS ×663 | (P) |
| ~72 | ~17.0 YOPS | PHM-Q3 + ACROSS full fleet | (P) |
| 100 | 1 QOPS | Quetta — 10³⁰ ops/s | PEAK |
Golden-ratio ladder: 100 rungs at ×1.61758. Progressive incremental scaling from measured silicon through Ronna to Quetta peak performance.
The generational fade
| Gen | Node | Strata | Status |
|---|---|---|---|
| PHM01 | 130 nm | 1 | BUILT |
| PHM02–05 | 65 nm → 7 nm | 1–4 | (R) roadmap |
| PHM06 | 5 nm / 18A | 6 | (R) full stack |
| PHM-Q3 | 5 nm + hybrid | 12 | (R) aggressive |
What you are buying
The RTL design — not a card in a box. You license the complete accelerator design with worldwide commercialization rights: the color-math core, all ten technology integrations, the offload architecture, testbenches, hash-anchored GDSII (102 MB, DRC/LVS clean), and the OpenLane2 flow. You bring the foundry, the card, and the rack. Patents retained (QBeam PHY via ExitPhi USPTO App# 19/722,805).
QBeam ExitPhi fabric — integrated interconnect
Tech #10 is not just a protocol — it is a patented physical layer (ExitPhi, USPTO App# 19/722,805, filed 2026-06-27, 30 claims). The QBeam Transfer Card ships as a PCIe 5.0 x16 HHHL HBA built into the accelerator ecosystem:
| Attribute | Design target |
|---|---|
| Aggregate throughput | 400 GB/s bidirectional per card |
| Cut-through latency | 400 ns (doorbell → DMA write) |
| Ports | 4× QBeam lanes on bracket |
| Encryption | AES-256-GCM at link-layer, stateless |
| Virtualization | SR-IOV, 64 virtual functions |
| Silicon configs | 12 (APM01-D-QPHY through APM12-D-QPHY, 22 nm → 2 nm) |
| Thermal | CoolBeam-clocked PHY, −40 °C to +85 °C |
| Ordering | PipeBeam — guaranteed wire-order delivery at L1 |
No cables. No third-party silicon in the datapath. The QBeam PHY eliminates all copper and optical interconnect between AutoPhi boards. Supported topologies: point-to-point, star, ring, 2D torus, dragonfly. Classical bytes only on the wire — the quantum is in the physics of the silicon, not on the wire.
The quantum is real
AutoPhi uses physical quantum mechanics — not simulation, not classical approximation. Silicon quantum dots (3–10 nm) store energy via photon absorption at discrete Zeeman and Landau levels. The LED nano-array (8×10¹&sup0; LEDs/cm²) recycles 84–98% of emitted photons back into the next stratum. QEC Surface Code gates every recycling loop. EM Cooling prevents thermal runaway. The quantum battery layers generate their own power — photon emission → re-absorption → quantum coherence storage → next stratum. No external grid required at operating depth. Quetta is the target. The architecture delivers.
SKU CRIONE-AUTOPHI-PROBABILITY-ACCELERATOR · Non-exclusive license · Priced by doctrine: 78.75% below today’s compute affordability · Never free; never publicly hosted; AES-256 delivery, password by post. Offered to any qualified buyer except PRC/RF entities; subject to US export law. · © Christopher Gabriel Brown · cri-one.com