84-phantasmphi-cpu

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Asset valuation: $90,000,000,000. Project 84 · cri-one.com portfolio · Author: Christopher Gabriel Brown · 2026-08-21 A CPU by design. Project 83's QuettaPhantom proudly listed the three things it deliberately lacked — fetch, memory hierarchy, interrupts.

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Valuation

Generous asset valuation: $90,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

PhantasmPhi CPU — PHC01 "PhantomCore"

Project 84 · cri-one.com portfolio · Author: Christopher Gabriel Brown · 2026-08-21

A CPU by design. Project 83's QuettaPhantom proudly listed the three

things it deliberately lacked — fetch, memory hierarchy, interrupts.

Project 84 builds exactly those three, on purpose, on the same seeds:

Fetch — PC-driven fetch/decode/execute over the original

Light-Trigger-lineage ISA (32-bit words, 16 registers, not a RISC-V /

ARM / x86 copy — per the seed's own founding claim).

Memory hierarchy — register file (L0) → L1 instruction + data

scratchpads (1-cycle) → memory-mapped device tier (multi-cycle). Honest

labeling: caches are the PHC02 roadmap; no cache is claimed.

Interrupts — vectored (vector = word 2), three sources (timer,

phantasm-done, external), EPC/CAUSE/IE, EI/DI/IRET.

The ALU is the seed — every arithmetic instruction executes on

color_math_alu

(shared, not copied): ADD is Red, MUL is Yellow, DIV is Green — the CPU

computes in the same wavelengths as every AutoPhi core and every phantom.

The coprocessor is the phantom — Project 83's phantasm_math_engine

sits beside the CPU as a memory-mapped coprocessor with a completion

interrupt. The FPU-beside-the-386 story, made literal: the CPU runs the

program; the phantom answers the math; the interrupt joins them.

Proven (2026-08-21, first run)

rtl/tb/phantom_soc_tb.v runs a hand-assembled machine-code self-test

(rtl/sw/phantom_program.hex) that exercises every claimed feature and

judges its own correctness in software:

1. MUL 6×7 on the color ALU → store → load back through the hierarchy → verify

2. EI, arm the one-shot timer, spin → vectored timer interrupt taken,

ISR counts the tick, IRET returns to the spin

3. Wake the phantasm coprocessor via MMIO (deposition D05 KELLY,

p=0.75 b=1.0) → completion interrupt taken → software reads 32768

(0.5 in Q16.16, the proof-battery value) and verifies it

4. Debug protocol: tick count then PASS word → HALT

Result: PHANTOMCORE: ALL CHECKS PASS.

Price

**$425,000,000,000 USD per non-exclusive license — exactly 2× the

QuettaPhantom coprocessor wrap ($212,500,000,000), by owner's pricing

order of 2026-08-21: a CPU commands double its coprocessor.** The Project

83 doctrine chain is inherited: pegged to compute affordability, the

75 %-lower pledge, the multi-license structure, the Generational Law

(each PHC generation must list lower per unit of capability), no PRC/RU

entities, US export law, RTL is the only thing for sale, never free,

never naked.

Memory map (word addresses)

Build & verify

. ..\83-autophi-qbeam2\oss-cad-suite\environment.ps1
cd rtl
iverilog -g2005 -o ..\build\phantom_soc_tb.vvp tb\phantom_soc_tb.v phantom_soc.v phantom_core_cpu.v ..\..\83-autophi-qbeam2\phantasmphi-series\rtl\phantasm_math_engine.v ..\..\83-autophi-qbeam2\phantasmphi-series\rtl\phantasm_pack_rom.v ..\..\83-autophi-qbeam2\rtl\common\color_math_alu.v
vvp ..\build\phantom_soc_tb.vvp

Maturity — honest report

RTL-proven (L2) + SKY130-mapped. Simulated self-test passes; SKY130

mapping complete (build/phc01_sky130.log, official sky130_fd_sc_hd TT

liberty): 89,840 cells, 1,430,173 µm² (1.43 mm²). Honest note: the L1

scratchpads synthesize as flip-flops and dominate that area; PHC02 swaps

them for SRAM macros and shrinks the die substantially. Not yet: SDC, P&R (the Project 83 QEMU

forge is the staged path), tape-out, silicon. Multicycle core (~3–4

cycles/instruction at the seed ALU's pace); pipelining, caches, and the

pipelined-divider clock uplift are the PHC02 roadmap, priced per the

Generational Law. Firewall: Project 83 supplies the seed ALU and the

phantasm coprocessor at arm's length; no revenue or contracts co-mingle.

Contact

Christopher Gabriel Brown — Inventor · Author · Visionary

crioneaka@outlook.com · crioneaka@outlook.com

1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Email and postal mail only — no phone calls, no brokers, no intermediaries.

US companies only. USD only.

PHC02 "PhantomCore v2" — STATUS

Project 84 · PhantasmPhi CPU line · Second generation

Class: RTL-proven (L2). Simulated self-test PASSES end-to-end. 2026-08-22.

What PHC02 is

PHC01 built the CPU (fetch, memory hierarchy, interrupts) around the AutoPhi

seed ALU with the phantasm as an MMIO coprocessor. PHC02 keeps every ISA

promise identical and delivers three concrete engineering changes from the

PHC01 roadmap:

1. SRAM macro scratchpads replace the flip-flop arrays.

PHC01's L1 I/D scratchpads dominated 55 % of its 1.43 mm² die as raw

flip-flops. PHC02 wraps them in sram_1rw — a sync-read, sync-write

single-port SRAM interface that maps 1:1 to a sky130_sram_1rw macro at

OpenLane P&R substitution. Behavioral in simulation (SIM_INIT guard),

black-box in hardening.

2. Sequential divider dispatch removes DIV from the seed ALU's

combinational critical path.

PHC01 forced the OpenLane run at CLOCK_PERIOD 500 ns because

color_math_alu's combinational 64-bit divide was the critical path.

PHC02 introduces seq_divider.v (32-cycle restoring divide, non-

pipelined, divide-by-zero saturates like the seed) and routes the ISA

DIV opcode to it instead. The seed ALU still services ADD / SUB / MUL /

AND / OR / XOR / SHL — the fast path. DIV is slower per operation but

removes the register-timing anchor.

3. Two-cycle deterministic fetch to match sync SRAM semantics.

imem_addr is combinationally driven from pc; the FSM waits one

cycle (S_FETCH_ADDR) for SRAM to sample the new address, then one more

(S_FETCH_WAIT) to latch its output into ir. Straight-line cost:

2 cycles / instruction — same as PHC01, with the SRAM interface in the

loop.

Prefetch (overlap fetch of N+1 with execute of N) and true pipelining are

the PHC02.1 roadmap — this revision keeps the multicycle FSM for

simplicity and correctness.

What PHC02 is not (honest markers)

No pipelining. F/D/X/M/WB stages remain multicycle. PHC02.1 target.
No caches. The scratchpad is still the L1. A proper L1D/L1I cache

fronting a wider backing store is on the PHC03 roadmap.

No SKY130 P&R yet. OpenLane P&R is queued behind the QEMU forge; the

V2 and V3 coprocessor runs occupy the forge now. Real cell count and die

area will read from phantom_soc_v2/runs/phc02-forge/final/metrics.json

when it lands.

Yosys standalone area check is not fair. With sram_1rw behaving as

a synthesizable memory in the standalone Yosys pass (no SKY130 SRAM

macro library available), constant propagation folds the design in ways

the real OpenLane flow will not. The apples-to-apples number is the

OpenLane run.

Files (all new, side-by-side with PHC01)

rtl/phc02/
├── sram_1rw.v                 -- sync SRAM wrapper (256/1024 x 32 in this SoC)
├── seq_divider.v              -- 32-cycle sequential divider
├── phantom_core_cpu_v2.v      -- PHC02 CPU (multicycle FSM + divider dispatch)
├── phantom_soc_v2.v           -- PHC02 SoC (SRAM scratchpads + devices)
└── tb/
    └── phantom_soc_v2_tb.v    -- self-test bench (reuses PHC01 program)

The phantom_program.hex from PHC01 is reused unchanged.

Proven (2026-08-22, first PASS)

=== PHC02 PhantomCore v2 self-test (SRAM hierarchy + prefetch + dispatched divider) ===
[debug 0] 0x00000001 (1)
[debug 1] 0x00000001 (1)
timer interrupts observed: 1
phantasm coprocessor KELLY answer verified in software
PHANTOMCORE-V2: ALL CHECKS PASS

Debug protocol matches PHC01 exactly: two DEBUG_OUT writes, first is the

timer-tick count from the ISR, second is the PASS word 0x1. Same

hand-assembled phantom_program.hex. Sim wall time to HALT: 3.205 ms.

Build & verify

. D:\special\83-autophi-qbeam2\oss-cad-suite\environment.ps1
cd D:\special\84-phantasmphi-cpu\rtl
iverilog -g2005 -DSIM_INIT -o ..\build\phantom_soc_v2_tb.vvp `
    phc02\tb\phantom_soc_v2_tb.v phc02\phantom_soc_v2.v `
    phc02\phantom_core_cpu_v2.v phc02\sram_1rw.v phc02\seq_divider.v `
    ..\..\83-autophi-qbeam2\phantasmphi-series\rtl\phantasm_math_engine.v `
    ..\..\83-autophi-qbeam2\phantasmphi-series\rtl\phantasm_pack_rom.v `
    ..\..\83-autophi-qbeam2\rtl\common\color_math_alu.v
vvp ..\build\phantom_soc_v2_tb.vvp

SIM_INIT gates the $readmemh init inside sram_1rw; without it the

memory is X-initialized (real silicon boot state).

Generational Law reading

PHC02 must list per-unit-of-capability under PHC01's $425 B/license before

becoming a live SKU. The Generational Law is preserved on two axes:

Cycles per instruction on straight-line code: PHC02 = 2 c/i (same as

PHC01), but the removed combinational DIV means the clock can uplift

when real P&R replaces the 500 ns period. Effective ops/s rises.

Die area per unit of function: PHC02 replaces ~55 % of PHC01 area

(scratchpad FFs) with SRAM macro area, which at SKY130 shuttle shrinks

substantially per bit. Real number pending OpenLane P&R.

Absolute list price will be set at P&R landing; per-capability price must

be below PHC01's per the Generational Law. If the numbers do not close

below PHC01, PHC02 remains RTL-proven-only and does not open a SKU.

Not offered to PRC/RU entities.

This archive contains 2 documents. The complete folder ships as the product.

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