A $7B card, built one wafer at a time

People read a seven-billion-dollar price on a product page and either laugh or look away. I would rather they looked straight at it. The number is not a joke and it is not a boast. It is what the AutoPhi PCIe 5.0 1536 is worth, measured against the smaller things in its market, and it is written on the page so that anyone, with or without an account, can see it.

I want to write down, in one place, what that number is paying for. One wafer at a time. Where the money goes, in pieces small enough to argue with.

One wafer, measured

A wafer is a round plate of silicon, 300 millimetres across and about three-quarters of a millimetre thick. Roughly 70,000 square millimetres of it is usable area, once the edge is taken off. The AutoPhi die, drawn to a full reticle shot, is 858 square millimetres. Divided out, that is about seventy dies on each wafer, before any of them get thrown away for defects.

Some of them do get thrown away. At a mature seven-nanometre process the defect density runs around a tenth of a defect per square centimetre, which on an 858 square millimetre die gives roughly a one-in-two yield, so about thirty-five good AutoPhi dies walk off each wafer. At Intel 3, with the EUV optics still bedding in, call it twenty-eight. At Intel 18A on first ramp, closer to twenty. One wafer costs between nine and twenty-two thousand dollars depending on the node. Each good die, as silicon, lands between two hundred and sixty dollars and eleven hundred.

That is one wafer. The engineering around that one wafer, the mask set and the sign-off work and the EDA tools that print the shapes, is where the real money sits. On Intel 3 it is forty-five to sixty-five million dollars once, before the first wafer runs. That is what the gift raiser is paying for.

The eighteen chiplets

The AutoPhi die is not one monolithic block of logic. It is eighteen separate chiplets, stacked, each one carrying fifteen hundred CFET voxel layers. That makes twenty-seven thousand voxel layers through the stack from the bottom chiplet to the top. Each layer is a lattice of switching cells that can be read as a classical bit, as a photon state, or as the room-temperature quantum state the Normal Resonance work was designed to hold. Three strands running through the same silicon, which is why the chip is called a chain and not a processor.

On-package, next to the stack, sits the QBeam send and receive pair. The QBeam does not do compute itself. It is the wireless chain that moves bytes off the chip at the speed the chain inside produces them, so the PCIe lanes on the carrier board are no longer the ceiling. All of this fits in a forty by forty millimetre BGA-1536 package, which is the thing the carrier board was drawn around.

It is a lot to put on one piece of silicon. That is why Intel Foveros Direct matters, and why no other commercial packaging line can take the design as it is drawn.

Where the money goes

I picked Intel Foundry because the chip, as drawn, needs Foveros Direct. Foveros Direct is Intel's three-dimensional hybrid-bonding packaging line. It joins silicon to silicon face to face, copper pad to copper pad, with no solder in between. That is what the eighteen-chiplet stack needs. Nothing else on the market right now takes the design as it is drawn, which is why the brief that goes with this essay recommends Intel over TSMC on packaging grounds alone, before any CHIPS Act math is stacked on top.

On Intel 3, the production-ready EUV node, the engineering cost before the first wafer runs is forty-five to sixty-five million dollars. That is the mask set, the design closure work that gets an 858 square millimetre die signed off, and a year of EDA tools from the two or three vendors that sell the full flow. Foveros Direct packaging adds another eight to fifteen million in one-time cost. Together, call it sixty to eighty million dollars to get to first silicon in packaged form.

The carrier board is small by comparison. The twelve-layer Megtron 6 PCIe 5 add-in card, finished, qualified, built in prototype quantity, lands at a quarter to four hundred thousand dollars. A thousand-card production run runs two to three and a half million. The board is a solved problem. The chip is the mountain.

Stacked on top of all of this is the CHIPS Act. A twenty-five percent Investment Tax Credit on the fab's capex, which passes through as better wafer pricing. A DoE Loan Programs Office guarantee at near-Treasury rates for the Tier A size of the ask. A grant lane through the NSTC Microelectronics Commons for the beyond-CMOS parts, which is exactly what the three-strand chain is. These sit on top of each gift raiser dollar and roughly double its reach when the Intel path is picked. The TSMC path has none of these. Intel is the only door that opens them.

A gift, not a loan

I am not raising this as a loan and I am not selling equity. I am asking for a gift, in the amount the product is already listed for on the catalog page.

In exchange, when the first silicon ships, I send the patron their own copy of the complete engineering package. KiCad PCB file. Schematics. Netlists. Flat BOM. Specctra routing pair. The 1,536-ball pinmap. The thirty-three-script Python pipeline that forks the Texas Instruments reference into thirty-four input and output variants. All of it on an AES-256 encrypted Blu-ray. One copy per patron.

It is non-exclusive on purpose. Non-exclusive is one of my standing rules and it is not up for negotiation. More than one patron may pledge; each one receives their own copy; nobody buys the right to be the only one with it. The IP, the BGA-1536 package program and the routing pipeline stay with me, as the inventor. What a patron receives is the right to use the package I spent two years drawing, for their own research, or their own strategic non-exclusive position, or, at the top of the three pledge points, their own manufacturing and deployment of boards built against it. In the sizes already listed on the product page: two million, ten million, twenty million, or an amount of their own choosing.

I call it a gift raiser because that is what it is. It is the people who want this to exist, paying for it to exist, and getting a copy of it for themselves on the way out. There is no interest to pay back, no board seat to give up, and no clock running down on when they get what they paid for. The clock runs on the fab.

The link

The gift raiser lives at cri-one.com/crione-autophi-funding.php. The three pledge points and the custom amount are on that page, and so is a short form that lands in my own inbox. The product it is paying for is at cri-one.com/44-autophi-pcie5-1536.html, seven billion dollars written on it in full, patent pending under USPTO 19/835,210.

One wafer at a time. That is how this gets built. That is what the gift pays for.

— Christopher Gabriel Brown