54-exitphi-accelerators
Asset valuation: $5,000,000,000. Greater WiFi. Faster data-center wireless. A line of patent-pending WiFi6E / WiFi7 silicon designed for one job: make the data center over wireless real. Commodity WiFi controllers (ESP32-S3, ESP32-C6, MediaTek, Qualcomm AC) treat
Walk into a data center and look down. Under the floor and over the racks run the fibers, the copper data cables and the management cables, and every one is a thing to pull, label, trace and replace. ExitPhi is a family of WiFi 6E and WiFi 7 accelerator silicon built for one job: take all of it out. Only the power cord stays. The chip is the network.
Four reference ICs cover the range. WFA-Node is the single-stream endpoint for dongles, handsets and wearables. WFA-Hub is the four-by-four tri-band access-point accelerator serving sixty-four peers. WFA-Mesh is the eight-by-eight, three-radio backhaul that ties two hundred fifty-six peers across racks. WFA-Apex is the flagship, the only member carrying all nine proprietary on-die blocks, each patent-pending and owned by the inventor. Twenty-two configurations run from 22 nanometer planar dies to 3 nanometer fifty-layer chiplet stacks. Three subsystems complete it: CoolBeam, a phased-array antenna that cools the die while it transmits; PipeBeam, an antenna series that keeps packets in order; and QBeam, the wireless quantum send-and-receive chain.
This is for datacenter operators who want the cable plant gone and for silicon buyers who want an architecture to take to a foundry. The work sits at step 5.5 of 12 on the engineering ladder: the architecture ships now as a foundry-partner deliverable, and silicon in hand is twelve to twenty-four months out depending on configuration. The inventor retains the IP. The buyer walks away with the four IC designs, the reference boards and the subsystem specifications, with the filed thirty-claim application standing behind them.
Description
ExitPhi IC — Wireless Datacenter Accelerator Silicon Family
Patent-pending. U.S. Non-Provisional Utility Patent Application No. 19/722,805, Confirmation No. 4017, Patent Center No. 77974071, filed 2026-06-27 via USPTO Patent Center under 35 U.S.C. § 111(a). Title: Integrated Wireless Datacenter Fabric with Phased-Array Cooling Antenna, Order-Preserving Antenna Series, and Quantum-Teleportation Protocol atop a Shared Classical Channel . 30 claims (6 independent, 24 dependent). Related to, but separate from, U.S. Application No. 19/717,706 (UniPhi DC). Inventor: Christopher Gabriel Brown, pro se, sole inventor, no assignment of record at filing. IP fully retained.
Overview
ExitPhi IC is a patent-pending family of WiFi 6E / WiFi 7 accelerator silicon designed for one goal: make the data center over wireless real . Every fiber, every copper data cable, every management cable — gone. Only the power cord stays. The chip is the network.
The public-facing brand is ExitPhi . Internal engineering artifacts use the WFA-* prefix. Three sibling brands: UniPhi (command-center software), ExitPhi (wireless-exit silicon), AutoPhi (foundry + canonical RTL source). Each is a separate company-shaped entity with its own IP, catalog, and revenue. No source, IP, or revenue is co-mingled.
The family comprises four reference ICs (WFA-Node, WFA-Hub, WFA-Mesh, WFA-Apex) and 22 pre-defined configurations spanning 22 nm through 3 nm process nodes, from single planar dies to 50-layer chiplet stacks. Three subsystem technologies — CoolBeam (phased-array antenna that simultaneously cools the die), PipeBeam (order-preserving linear antenna series), and QBeam (wireless quantum-to-quantum teleportation protocol) — complete the architecture. QBeam is the only wireless quantum-to-quantum fabric on the market.
Current status: step 5.5 of 12 on the engineering ladder. Architecture is shippable today as a WFA-FOUNDRY-PARTNER deliverable. Silicon-in-hand is 12–24 months away depending on configuration.
The Four Reference ICs
IC Standard Bands Streams Peak PHY Rate Concurrent Peers Process Package Host Bus Power (typ.)
WFA-Node 802.11ax (WiFi 6E) 6 GHz 1 × 1 SISO 1.2 Gbps 1 22 nm QFN-56, 7 × 7 mm SPI (50 MHz) + I2C ~150 mW
WFA-Hub 802.11ax (WiFi 6E) 2.4 / 5 / 6 GHz 4 × 4 MU-MIMO 4.8 Gbps 64 22 nm QFN-88, 8 × 8 mm PCIe Gen3 × 1 ~1.2 W
WFA-Mesh 802.11be (WiFi 7) 2.4 / 5 / 6 GHz simultaneous 8 × 8 across 3 radios ~30 Gbps agg. 256 across racks 16 / 12 nm BGA-256, 12 × 12 mm PCIe Gen3 × 2 ~5 W
WFA-Apex 802.11be+ (WiFi 7 MLO) 2.4 / 5 / 6 GHz + CBI link 8 × 8 + 9 proprietary blocks flagship flagship 5 nm FCBGA-196, 15 × 15 mm PCIe Gen4 × 4 + DDR5-6400 ~35 W peak
WFA-Node Reference Board
Single-stream WiFi 6E endpoint / client accelerator. Fits in USB-C dongles, handsets, wearables, IoT devices. Board form factor: 60 × 40 mm, 4-layer FR-4 PCB. Operating temperature: −20 to +70 °C.
RF Frontend Johanson 2450BM15E0002 6 GHz balun; integrated inverted-F PCB antenna (U.FL alternate)
Boot / Storage Winbond W25Q64JV 64 Mbit QSPI NOR (firmware + event log); Microchip 24AA02E48 ID-EEPROM (EUI-48)
4 × 4 MU-MIMO tri-band access-point accelerator. Board form factor: 160 × 100 mm, 4-layer FR-4 PCB. Operating temperature: 0 to +70 °C.
8 × 8 tri-radio mesh backhaul + fronthaul accelerator. Board form factor: 200 × 140 mm, 6-layer FR-4 PCB. Operating temperature: 0 to +65 °C.
8 × 8 WiFi 7 (802.11be) flagship accelerator with all 9 proprietary blocks feature-gated in. Board form factor: 240 × 160 mm, 8-layer hi-Tg FR-4 PCB. Operating temperature: 0 to +65 °C.
Radio — 6 GHz WiFi 7 8 × 8 MLO; 8 × Skyworks SKY85850 FEM (chain #7 reserved for CBI); 4096-QAM via QLA block
Power Supply 12 V from host; Vicor DCM4823 200 W isolated; TI TPS543C20 buck bank (3V3 12 A, 1V8 12 A, 1V2_RF 6 A, 1V1_DDR 24 A, 0V9_CORE 24 A)
Debug 20-pin ARM JTAG; 6-pin UART; 8 × LEDs (WiFi7/5/2.4, ACT, ASSOC, CBI-LOCK, DFS-LOCK, FAULT); reset + recovery pushbuttons
Each block is individually patent-pending and owned by the inventor. None are available on the open market. The WFA-Apex is the only IC in the family that carries all nine.
# Block Full Name Function
1 FMR Fabric Framing Engine JSON-Lines + length-prefixed binary tunnel framing at line rate
2 FMA Fabric-Aware MAC EDCA + Airtime Fairness + 4-class traffic scheduler (CONTROL / TUNNEL / APP / QUANTUM)
3 CRY Crypto Cluster SHA-256 + HMAC-SHA-256 + AES-256-GCM + X25519 + TRNG
4 NVR NVRAM Burst Writer Deterministic event-log persistence via external QSPI NOR;
Reads JSON-Lines control frames and length-prefixed binary tunnel frames directly off the RX descriptor at line rate. Drops malformed frames at line rate. Surfaces parsed frame objects to the host via a 64-entry ring per direction. Wire protocol is bit-for-bit interoperable with the software uniphi.dc.fabric implementation — the rack can run a mix of WFA-accelerated and software-only members during rollout. Throughput target: >10 M frames/sec parsed at the engine.
X25519 50,000 ops/s mTLS handshake key exchange; pre-computes shared secret during certificate parsing
Classifies traffic by inspecting the HELLO frame's flow tag. Four traffic classes with dedicated EDCA-equivalent priority:
QUANTUM 2-bit QBeam teleportation payloads Highest PipeBeam for ordered; CoolBeam for max diversity
Airtime Fairness (ATF) is enforced per fabric peer ID so one noisy node cannot starve the rest of the rack.
NVRAM Burst Writer
A dedicated DMA engine + QSPI controller that owns an external W25Q64JV (or similar 64 Mbit to 256 Mbit QSPI NOR). On every event-log append via host doorbell: reads prepared JSON event from host-DMA region, appends to in-flash log, issues synchronous flash write (block-erase if needed), ACKs host only when durable. End-to-end fsync target: .
- High-priority ring: one interrupt per frame for CONTROL class (latency-critical).
- Aggregated ring: one interrupt per K frames (K configurable, default 32) for TUNNEL + APP traffic.
At 64-peer hub saturation, host CPU utilisation stays under 10%.
CoolBeam — The Antenna That Cools
An 8 × 8 phased-array antenna whose radiating patches are simultaneously the cold-side terminals of a thermoelectric Peltier pump. RF radiates outward. Heat pumps upward. Same metal. Same layers. One structure, two jobs. CoolBeam solves antenna detuning and thermal ignition at the same physical location.
Pellet alloy Bi 2 Te 3 (consumer tier) or proprietary high-ZT (premium tier, AutoPhi trick #5)
CoolBeam transforms WiFi from omnidirectional broadcast (99% wasted radiated power) into a point-to-point beamformed mesh . A rack with 1,000 WFA-equipped chips can sustain ~30,000 simultaneous beamformed peer-to-peer links without interference. Each link uses ~1% of the power for ~100 × the link budget.
CoolBeam is mandatory for Stack-25, Stack-50, and Stack-100 configurations. The three CoolBeam layers occupy the topmost chiplet layers of the stack.
PipeBeam — Order-Preserving Antenna Series
A sequence-locked linear antenna array where packets enter element 1, exit element N, and arrive in the exact order they were sent — enforced by hardware at the physical layer, not by software at the transport layer. No reorder buffer. No TCP-class retransmit. No upper-layer sorting tax.
Each PipeBeam element contains five sub-blocks:
- Radiating patch — 4 mm × 4 mm copper, same physical form as CoolBeam
- Sequence latch — single-cycle hardware FIFO stage with monotonic position tag
- Time-slot gate — per-element clock divider; no central scheduler
- Position-tag comparator — refuses to transmit until the previous element acknowledges completion; single-wire adjacent-element handshake
- Local Peltier pellet — same 0.3 W cooling cell as CoolBeam
PipeBeam unlocks: quantum-circuit gate dispatch, drone-swarm command relay, database WAL streaming, sub-frame-timed live media, and deterministic real-time control. Standard WiFi MIMO does not guarantee in-order delivery at L1. PipeBeam does.
QBeam — Wireless Quantum-to-Quantum Teleportation
QBeam carries quantum information between ExitPhi chips — not by transmitting fragile coherent quantum states through the air, but by quantum teleportation atop the classical WFA channel. Pre-shared entanglement pairs live in the quantum-battery layers (AutoPhi trick #6); Bell measurement on chip A + 2 classical bits over CoolBeam or PipeBeam + Pauli correction on chip B = one teleported qubit. The wireless link itself carries only two classical bits per teleported qubit.
The 22 configurations span from 22 nm planar single-band through 3 nm 50-layer chiplet stacks. Each has a canonical 44-line FOUNDRY_HANDOFF.md document. Representative configs:
CFG-21 (Stack-50) Apex stack 3 nm + 50 layers ~15 × 15 mm, ~2.5 mm tall 1.75 TB/s ~50 ns 9 of 9 × 3 = 405 instances
CFG-22 (Stack-25) Apex stack 3 nm + 25 layers ~13 × 13 mm, ~1.3 mm tall 870 GB/s ~25 ns 9 of 9 × 3 = 135 instances
Stack configurations trade latency for throughput: each photonic layer adds ~1 ns of propagation. Latency-bound workloads (HFT, defence) take Stack-25; throughput-bound workloads (datacenter ingest, AI training) take Stack-50.
Interrupt rate vs. commodity at same load 1 × 0.5 × (halved by descriptor-ring aggregation)
These are design targets, not measured. They are written into the spec at the RTL contract level and will become measured once first silicon comes back.
For reference: all published quantum systems on Earth as of 2025 combined deliver less than 0.01 Q-TOPS. Stack-50 delivers 7,500 × that on one chip.
AutoPhi Process Tricks Integrated
The stacked configurations integrate all 9 AutoPhi process tricks under separate foundry sub-agreement:
CFG-04 thin RTL pin contract: 6 Verilog modules, 345 lines total , all parsing clean with balanced begin/end and parentheses. These are 40–80 line pin-contract stubs; real AutoPhi production RTL files are ~200 lines each.
Module File Lines Purpose
wfa_phy wfa_phy.v 47 802.11ax 4 × 4 MU-MIMO PHY interface (CSD encoding, LDPC, 1024-QAM, OFDMA, beamforming)
wfa_mac wfa_mac.v 43 Fabric-aware MAC scheduler with round-robin + priority bypass; 8-peer depth, configurable TXQ
wfa_fabric wfa_fabric.v 60 Fabric framing engine; JSON-Lines (state ST_JSONL) + binary tunnel (state ST_BINARY); MAX_LINE = 4096
wfa_crypto wfa_crypto.v 62 Crypto cluster command interface; 6 opcodes (SHA, HMAC, AES_E, AES_D, X25519, TRNG); 256-bit payload bus
wfa_pcie wfa_pcie.v 53 PCIe Gen3 × 1 host bus; 256-bit payload; NVMe-style queue model
wfa_top wfa_top.v 80 Top-level integration: instantiates PHY + MAC + Fabric + Crypto + PCIe; STREAMS = 4 parameterised
wfa_qbeam wfa_qbeam.v 98 Quantum teleportation orchestrator; Bell measurement (side A) + Pauli correction {I, X, Y, Z} (side B); QUBITS = 256, ENT_POOL_DEPTH = 768,000, up to 24 simultaneous Q2Q channels
wfa_entanglement_store wfa_entanglement_store.v 73 Pre-shared entanglement pair pool manager; dual block memories (A halves + B halves); low-water alarm at pool/16; boot-time refill + per-teleport consume paths
Total RTL across the package: 8 Verilog modules, 516 lines .
Python Reference Simulator and Test Suite
wfa_sim.py (236 lines): functional model of the WFA backbone + 9 proprietary blocks + AutoPhi-trick interfaces. Bit-exact for crypto and event-log hash chain; cycle-approximate elsewhere. Models: EventLog (SHA-256 hash-chained), DPRBlock (lowest-RTT path picker), ULFBlock (loop-refusing firewall), CLOBlock (closed-loop envelope), CryptoCluster (SHA-256 + HMAC-SHA-256), EntanglementStore (768,000-pair capacity), QBeam (teleportation orchestrator), WFAChip (backbone assembler with deploy/replicate API).
Test suite (301 lines across 2 files): 14 testbenches passing in ~0.013 s.
TB1: NVRAM Burst Writer hash chain holds across 1,000 writes + detects tamper. TB2: deploy() returns sequential IDs. TB3: ULF refuses re-entering routes. TB4: CLO engages closed-loop posture, refuses deploys when engaged. TB5: DPR picks lowest-RTT peer. TB6: config target matrix — throughput ramps monotonically, planar latency improves with process shrink, stack latency grows with layers, every config beats ESP32-S3 baseline (100 ms). TB7: QBeam teleports one qubit + 1,000 qubits consuming the pool. TB8: QBeam pool exhaustion returns failure; refill restores capacity.
Total schematic records: 7,941 . All brackets balanced.
- 4 per-IC handoffs (Node, Hub, Mesh, Apex)
- 22 per-configuration handoffs (CFG-01 through CFG-22, including Stack-25 and Stack-50)
Each document covers: handoff summary, submission steps, required deliverables (GDSII, LEF, DEF, gate-level netlist, DRC, LVS, RTL, synthesis scripts, P&R configs, BOM, performance projections), IP valuation notes, and compliance/NDA terms.
26–35 Quantum-classical hybrid lanes (trick #7); Bell measurement + Pauli correction hardware
36–38 Quantum-battery storage (trick #6); ~768,000 entangled half-pairs; QEC (trick #4) at ≥99.998%
1–10 Integrated wireless datacenter fabric system (stacked-chiplet IC, CoolBeam + PipeBeam + QBeam + fabric-aware MAC + crypto cluster)
11–13 CoolBeam dual-function phased-array antenna structure (RF radiator + Peltier cold-side electrode, bias-tee separation, material group)
14–16 PipeBeam order-preserving linear antenna series (sequence latch, time-slot gate, position-tag comparator, egress verification)
17–21 QBeam wireless quantum-teleportation method (entanglement pre-distribution, Bell measurement, classical transmission, Pauli correction, QEC re-request)
22–24 Cable-free datacenter chassis and rack (sole attachment is AC power conductor; no data cable, optical transceiver, or fiber)
25–30 Dependent claims: CoolBeam/PipeBeam coexistence on same top layers; 8 RF chains × 3 bands = 24 Q2Q channels; M × N chip aggregation; quantum-battery thermal coupling; fabric-framing engine bit-for-bit interop; process node group (22–3 nm)
Licensing Model
The inventor retains ownership of the IP permanently . This is not a sale of the IP and is not an assignment. Buyers receive (1) the blueprints and (2) a license to use the IP. No tier ever includes the patent rights, the right to resell the design, or the right to claim authorship.
SKU Name Anchor Price (USD) What Buyer Gets
WFA-SPEC Specification + Reference Schematics $9,999 Evaluate the design: SPEC.md, datasheet, reference schematic PDFs. Digital delivery. No production use.
WFA-DEV-KIT Developer Kit $24,999 Commodity hardware (ESP32-S3 + FPGA dev board) running WFA host-bus emulation. Build drivers against the wire protocol today. Internal R&D only.
WFA-BLUEPRINT-PACK Full Reference Design $499,999 Schematic + RTL spec + DV vector library + integration guide. Perpetual non-exclusive licence to use, modify, and ship products. Sub-licensing prohibited.
WFA-FOUNDRY-PARTNER Foundry Partner $4,999,999 Everything in BLUEPRINT-PACK + channel to AutoPhi fabrication + bring-up support + 2 years inventor email support. Production-quantity silicon path.
- Cost-to-replicate: estimated $3–$7 billion to reach functional equivalence from zero.
- Comparable-transaction: ARM at ~$54B; Mellanox at $6.9B; AutoPhi Future at $7T.
- Discounted cash flow: multi-hundred-billion to multi-trillion range under conservative assumptions.
- Opportunity cost: $50k–$200k per rack saved in cabling; $5B–$20B at hyperscale (100k racks).
- Strategic value: eliminates a category of physical infrastructure no competitor has eliminated; carries quantum compute at a scale no competitor offers.
- Patent enumeration: 46+ enumerated assets (9 proprietary blocks + 9 AutoPhi tricks + seed voxel + CoolBeam + 4 schematics + 22 configs).
The warranty follows a seven-step Defects-and-Remedies Procedure : Notice (30 days) → Acknowledgement (5 business days) → Inspection (30 days) → Cure (60–90 days) → Re-trial (30 days) → Escalation (binding arbitration, AAA or JAMS) → Award (enforceable in U.S. District Court, Northern District of Georgia). Liability cap: the price paid for the deliverable. Excluded: consequential, lost-profit, indirect, punitive damages.
DV Vector Library Posture
Full DV (Design Verification) is intentionally not in this repository . The DV corpus defines what "right" means; it is the most valuable and most NDA-encumbered tier of the deliverable. The Python reference simulator (14 passing testbenches) is the public-facing equivalent. Canonical DV falls to AutoPhi source under NDA on buyer engagement, scoped per buyer tier.
STRATEGY.md Three-project relationship (UniPhi / ExitPhi / AutoPhi), pricing tiers, patent stance
Board Specs + BOMs SPEC.md per board (4 files) WFA-Node / Hub / Mesh / Apex board specifications
FOUNDRY_HANDOFF.md per board (4 files) Silicon pin/pad contracts at canonical 44-line scale
Config Handoffs FOUNDRY_HANDOFF.md × 22 CFG-01 through CFG-22 (22 nm to 3 nm Stack-50)
RTL (Verilog) CFG-04 thin RTL (6 modules) 345 lines: wfa_phy.v, wfa_mac.v, wfa_fabric.v, wfa_crypto.v, wfa_pcie.v, wfa_top.v
Subsystem Documentation hardware/COOLBEAM.md CoolBeam integrated antenna + Peltier cooling specification
Generators & Scripts hardware/gen_schematic.py KiCad schematic generator for all 4 reference boards
Figures & Diagrams figures/fig01.svg through fig10.svg 10 patent figures (referenced in patent application)
Patent Documents EXITPHI_NONPROVISIONAL.docx; sb0015a.pdf; aia0001.pdf; N417 exitphi(1).pdf USPTO filing documents and forms
Machine-Readable MANIFEST.json Project manifest: SKUs, product line, relationships, file index
Store Listings store/descriptions/*.html (4 files) + store/index.html Magento-ready HTML descriptions for all 4 commercial tiers
Total files on disc: 102. Total Verilog: 8 modules, 516 lines. Total Python: 6 files. Total SVG: 13 figures. Total KiCad schematic records: 7,941. Total foundry handoff documents across the portfolio: 26.
How this is delivered
This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
© 2026 Christopher Gabriel Brown. All rights reserved.
Photo
Footnotes
- Product number 8504.
- Family: accelerators adapters.
- Purchase: When you buy, you buy the use of that blueprint only.