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51-pcie8-standard - Performance

$884,148.75

In stock

SKU

2082

CS-51 Performance: data fans out from the NAND controller to six ACE tiles, the reduced result rides the ring and leaves through the IO tile, animated picture

Asset valuation: $12,000,000,000. Master index of all projects: PROJECTSINDEX. Sibling: 50-pcie8-standard — the secure-storage anchor (CS-50). This project is its scale-out + performance variant (CS-51). Last edited: 2026-06-18 Status: L0 (Concept / Roadmap) — scaffold, no RTL bring-up yet; CS-50 su

For the curious

Imagine the CS-50 drive, then imagine a fleet of them pulling together. CS-51 is the scale-out and performance member of the AutoPhi computational-storage family: a single-die or multi-chiplet circuit that fuses encrypted NVMe storage with programmable near-data compute, aimed at hyperscale fleets and AI-pipeline preprocessing. It inherits the filed CS-50 substrate and adds N-channel FTL parallelism, an N-instance AutoPhi Compute Engine fabric with tree or ring reduction, a chip-to-chip peer arbitration plane, five named AI-pipeline kernels, post-quantum hybrid key wrap and TPM-class confidential attestation. The host link is PCIe 8.0 x4 at about 256 GB/s per direction, with an E1.L target form factor of 32 to 64 TB per drive.

This is a soft-IP product, the same class as a licensed processor core, packaged as a whole chip design rather than one block. The buyer receives the engineering blueprints and foundry-handoff artifacts and fabs the silicon on their own foundry account. The bundle is 1,166 files, each SHA-256 checksummed, and every refutable claim is machine-verifiable from one command, twelve checks. The multi-channel FTL arbiter and the ACE scale-out fabric pass their iverilog testbenches, and the Python simulator passes its eighteen self-tests. The status is concept and roadmap, with no RTL bring-up yet. The CS-50 substrate is patent-pending under U.S. Application 19/710,460; the CS-51 extensions are scoped for a continuation-in-part before the PCT window closes in June 2027. Patent ownership stays with the inventor. The buyer walks away with the design, the proofs and the lineage from WonderPhi through CS-50 to this.

Details

Description

51-pcie8-standard — Performance (SKU 2082)

Patent Status: Patent pending. The CS-50 substrate is covered by USPTO Non-Provisional Utility Application 19/710,460 , filed 2026-06-17 (confirmation number 3169, Patent Center number 77534311), under 35 USC 111(a). Title: “Computational-Storage Apparatus with Inline AES-XTS Encryption Tweaked by Physical-Page Address and a Near-Data Compute Engine Sharing a Single Translation-Layer Command Port.” Additional family applications: USPTO 19/693,405 (CGB Framework umbrella, filed 2026-05-30, confirmation 5107, Patent Center 76837851—20 claims, names AutoPhi under Deposition 3: Voxel Resonance); USPTO 19/646,681 (Hyper Quantum Map, filed 2026-04-14, confirmation 7276); USPTO 19/540,453 (Integrated Technology Portfolio umbrella—Software for Data + Cri-One hardware family). CS-51-specific extensions (N-port FTL arbitration, N-instance ACE fabric, peer arbitration, post-quantum hybrid, confidential attestation) are scoped for a Continuation-in-Part (CIP) filing under 35 USC 120 before the CS-50 PCT window closes 2027-06-17. CIP draft: 26 claims across 6 independent claim families. All applications pending examination. Inventor: Christopher Gabriel Brown .

Overview

CS-51 is the scale-out and performance member of the AutoPhi computational-storage chip family—a single-die (or multi-chiplet) integrated circuit that fuses secured NVMe solid-state storage with programmable near-data compute, targeting hyperscale fleets and AI-pipeline preprocessing workloads. It inherits the filed CS-50 substrate (physical-page-tweaked AES-256-XTS encryption, reserved-CID single-port FTL arbitration, vendor-opcode 0xC1 doorbell invocation) and extends it with N-channel FTL parallelism, an N-instance AutoPhi Compute Engine (ACE) fabric with tree/ring reduction, a chip-to-chip peer arbitration plane, five named AI-pipeline kernels, post-quantum hybrid encryption (CRYSTALS-Kyber KEM key wrap), and TPM-class confidential attestation.

This is a soft-IP product —the same product class as ARM Cortex, Synopsys DesignWare, or Cadence Tensilica—packaged as a complete computational-storage chip design rather than a single IP block. The buyer receives engineering blueprints and foundry-handoff artifacts; they fab the silicon on their own foundry account. Patent ownership stays with the inventor.

The complete bundle comprises 1,166 SHA-256-checksummed files : 1,128 files from the frozen CS-50 baseline plus 124 CS-51-specific extension files. Every refutable claim in the package is machine-verifiable via a single command ( python verify.py —12/12 checks green).

Lineage

WonderPhi (Project 36, the universal driver in software) → CS-50 (Project 50, the driver fused with secured storage and one ACE on one die) → CS-51 (Project 51, multi-channel secured storage + N ACE instances + peer fabric on the same substrate) . The WonderPhi constitution version is 1.0.0 PERMANENT , inherited from CS-50.

Host Interface and Physical Specifications

Parameter Specification

Host link PCIe 8.0 ×4 (~256 GB/s usable per direction)

Controller DRAM HBM3e on-substrate (8–16 GB, ~1.2 TB/s)

Packaging Multi-chiplet UCIe (Universal Chiplet Interconnect Express) G2 substrate, 25 mm × 35 mm canonical

Target form factor E1.L (24-die NAND, 32–64 TB capacity per drive)

BGA package BGA-1536 (0.50 mm pitch; 384 power balls, 384 ground balls, 64 PCIe Gen8 differential pairs, 128 UCIe single-ended, 16 sideband)

Capacity target 4 TB (8 TB stretch) per CS-50 baseline; 32–64 TB at E1.L

Process node target ACE tiles: TSMC N3; IO and NAND-CTRL tiles: N5/N6; HBM3e: vendor node

Power envelope Standby: 2.5 W; Active: 15.0 W per compute tile; Burst: 40.0 W total peak

Thermal Worst-case 95 °C junction at 65 °C ambient

OpenLANE2 design name cs51_top

Clock period (design target) 0.500 ns (2 GHz)

Clock port host_clk

Die area (OpenLANE2 target) 800 × 800 µm (placement density 50%)

Inline AES-256-XTS Encryption with Physical-Page Tweak

The AES-XTS path is interposed between the FTL and the NAND media. Every write payload is encrypted, and every read payload is decrypted. The tweak input is the packed physical-page address (PPA) —not the host logical block address. The PPA is a 25-bit identifier: 3-bit NAND channel selector, 2-bit die selector, 12-bit block selector, and 8-bit page selector. Two 256-bit cryptographic keys (data key Key1 and tweak key Key2) are loaded at power-on and never appear on any host-readable port.

Encryption formula per block j within a data unit:

T_base = AES-256-enc(Key2, PPA-derived tweak) T_j = T_base · α^j in GF(2^128) C_j = AES-256-enc(Key1, P_j XOR T_j) XOR T_j

Decryption is the inverse. Because the tweak is the PPA, ciphertext at rest is bound to its physical location: relocating the same plaintext from PPA P1 to PPA P2 yields different ciphertext because T_base(P1) ≠ T_base(P2). The AES-256 core passes NIST Known-Answer Tests and IEEE 1619 XTS-AES-256 test vectors.

Multi-Channel FTL Command Arbiter

Parameter Specification

Module autophi_multichannel_ftl.v (6,405 bytes)

Testbench autophi_multichannel_ftl_tb.v (11,736 bytes)

Status Passing —4/4 iverilog test cases

Test cases (1) N=2 host-priority; (2) N=2 bridge-after-idle; (3) N=4 round-robin (3 bridges, 6 fires); (4) N=4 host preemption

Input command ports N (parameterized)

Output port Single FTL command port

Arbitration policy Host strict-priority + round-robin among N−1 bridge ports with rotating priority pointer

CID semantics Reserved-CID range (0xE000–0xEFFF, 4,096 distinct CIDs) inherited from CS-50

Ready-signal property Ready outputs are functions only of the FTL ready signal, not of masters' valid signals—eliminates circular dependency through the NVMe engine's doorbell-pulse-style valid output

N-Instance ACE Scale-Out Fabric

Parameter Specification

RTL module autophi_ace_scaleout.v (11,930 bytes)

Testbench autophi_ace_scaleout_tb.v (12,738 bytes)

Status Passing —5/5 iverilog test cases

Test cases (1) N=1 SCAN; (2) N=4 SCAN matches N=1; (3) N=1 VOXEL; (4) N=4 VOXEL associativity; (5) N=4 uneven striping (count=15)

Architecture N instances of CS-50 autophi_compute_engine.v (instantiated unchanged) + tree reducer for SCAN/VOXEL/XFORM

Start handshake 2-cycle handshake to avoid event-ordering race

Reducer topologies Binary tree (depth ceil(log2(N))) or ring reducer

Python simulator: ace_scaleout.py (20,297 bytes)— 18/18 self-test PASS . Covers all 8 compute operations at N=1 (byte-identical to CS-50 reference) and N=4 (VOXEL, SCAN, VECTOR_DOT, TOPK, ARGMAX, EMBED_LOOKUP, SOFTMAX byte-identical; XFORM Merkle fold documented).

AI-Pipeline Kernel Set

CS-51 adds five named AI-pipeline kernels to CS-50's existing VOXEL, SCAN, and XFORM operations, all invoked through the same NVMe vendor opcode 0xC1:

Kernel Operation ace_op Selector

VOXEL Fold payload bytes into a fixed-bin histogram (inherited from CS-50) 1

SCAN Predicate-match: return LBAs whose payload contains a host-supplied needle (inherited from CS-50) 2

XFORM Streaming transform / Merkle fold (inherited from CS-50) 3

VECTOR_DOT Signed integer inner product between payload bytes and a host-supplied query vector (CS-51 new)

TOPK Return top-K records by host-supplied scoring function (CS-51 new)

ARGMAX Return the LBA with the largest score (CS-51 new)

EMBED_LOOKUP Fetch fixed-prefix embeddings by global token ID—stripe-local indexing via (global_token_id − stripe_base_lba) (CS-51 new)

SOFTMAX Numerically-stable softmax probabilities across a stripe (CS-51 new)

Chip-to-Chip Peer Arbitration

Parameter Specification

RTL module autophi_peer_arb.v (12,717 bytes)

Testbench autophi_peer_arb_tb.v (9,044 bytes)

Status Passing —2/2 iverilog test cases

Test cases (1) 2-peer SUM reduction (100+7=107); (2) 2-peer SUM (1000+234=1,234)—with point-to-point peer fabric crosswiring + mock local ACEs

Framing 128-bit logical peer frame (tag / src / desc / payload)

Election Primary die = lowest non-faulted PEER_ID

Degenerate path Reduces to N=1 single-die mode cleanly

PCIe Peer-to-Peer Transport Bridge

Parameter Specification

RTL module autophi_p2p_bridge.v (8,845 bytes)

Testbench autophi_p2p_bridge_tb.v (14,907 bytes)

Status Passing —6/6 iverilog test cases

Test cases (1) TX encap format; (2) TX tag increment; (3) RX decode match; (4) RX reject non-MWr (silent drop—10 cycles, peer_rx_valid never asserts); (5) RX reject wrong-BAR (silent drop); (6) Loopback pair (A.peer_tx → A.tlp_tx → B.tlp_rx → B.peer_rx)

Architecture Two-FSM bridge: 128-bit peer frame → single 256-bit MemWr TLP (4DW header in low half, payload in high half); inverse on RX

Parameters THIS_BAR , PEER_BAR , REQUESTER_ID (per-instance differentiation)

Security Non-MWr TLPs and MWr TLPs to a non-matching BAR are silently dropped

Peer-Fabric Topology Model

Simulator: peer_fabric.py (13,506 bytes)— 24/24 self-test PASS . Five topologies modelled:

Topology N=2 (µs) N=8 (µs) N=32 (µs) N=64 (µs)

TREE 1.30 2.10 3.80 5.65

RING 1.18 1.57 2.79 4.40

HOST_MEDIATED 1.55 3.35 10.55 20.15

UCIE_INTRA_PKG 1.07 1.38 2.58 4.18

CXL_CACHE 1.55 2.85 5.05 7.15

Verdict: UCIe intra-package wins at every N≥2. RING is the multi-package fallback. At N=64, UCIe is 4.8× faster than HOST_MEDIATED on the reduction path.

UCIe Chiplet Architecture

The canonical CS-51 package is a UCIe G2 substrate carrying multiple tile types:

Tile Count Process Node Function

ACE Compute 2–12 (6 canonical) N3 AutoPhi Compute Engine instances + per-tile reducer fragment

IO 1 N5 PCIe 8.0 ×4 PHY + MAC + TLP + NVMe engine

HBM3e 1 Vendor 8 GB stack, ~1.2 TB/s bandwidth

NAND CTRL 1 N5 FTL + inline AES-XTS + multi-channel arbiter

UCIe peer-fabric lane 4 — 32 GT/s per lane intra-package

Variant SKUs:

SKU ACE Count HBM Target Deployment

CS-51-S 2 4 GB Edge / single-host

CS-51-M 4 8 GB Datacenter mid-tier

CS-51-L (canonical) 6 8 GB Hyperscale fleet

CS-51-XL 12 16 GB AI-pipeline preprocessing optimized

AI-Pipeline Performance Comparison (Design Targets)

Benchmark script: benchmarks/ai_pipeline_demo.py (8,210 bytes). Workload: per-query retrieval over a ~0.93 GiB embedding table (1,000,000 records × 1,024 bytes each); Top-K = 32; batch = 64 queries; per-query result = 512 bytes.

Metric Traditional Gen5 NVMe SSD CS-51 (design target)

Approach Host reads full table region over PCIe, CPU runs Top-K + dot + softmax Near-data EMBED_LOOKUP + TOPK + VECTOR_DOT + SOFTMAX across 6 ACE tiles, UCIe reduction

PCIe read bandwidth ~14 GB/s (Gen5 sequential best-case) ~256 GB/s (PCIe 8.0 ×4 usable)

Data crossing PCIe bus ~1 GB (entire table) ~32 KB (reduced result only)

Latency speedup Baseline ~38× lower latency

PCIe traffic reduction Baseline ~31,250× less data on the bus

Disclaimer: CS-51 numbers are design targets sourced from peer_fabric.py (24/24 self-test PASS) and published UCIe link rates. CS-51 silicon does not yet exist; numbers are not measured.

Post-Quantum Hybrid Encryption

Parameter Specification

Bulk encryption AES-256-XTS with physical-page tweak (unchanged from CS-50)

DEK wrap Hybrid: classical AES-Key-Wrap under cKEK concatenated with CRYSTALS-Kyber-encapsulated shared secret

Kyber parameter set At least Kyber-768 (NIST PQ level 3); Kyber-1024 selectable for level 5

Standards NIST FIPS 203 (ML-KEM / CRYSTALS-Kyber); NIST SP 800-56C Rev. 2; NIST SP 800-38F (AES-KW)

Wrap storage Wrapped DEK at a fixed PPA on NAND, itself encrypted under AES-XTS with that fixed PPA as tweak

Recovery Boot-time requires both classical cKEK authentication and successful Kyber decapsulation against host-attested trust anchor

Backwards compatibility Classical-only wrap detectable from wrap header; supported in legacy mode

Forward compatibility Wrap header carries a 16-bit primitive-set identifier for future PQ primitives

Security budget: Effective DEK security ≥2 128 even with one primitive broken (classical or post-quantum). Bulk AES-256-XTS: 2 256 classical / 2 128 quantum (Grover). Kyber-768 KEM: 2 252 classical / 2 166 quantum.

Confidential Storage Attestation

Parameter Specification

Trust root Hardware-rooted fused identity key burned at manufacture; not user-replaceable; DICE-compatible

Attestation algorithm Hybrid signature: EdDSA over Ed25519 (classical) + Dilithium-3 (post-quantum)

Report magic 0x434E50_413531 ("CNFA51")

Report size ~3.5 KB (244 bytes header + Ed25519 signature + ~3,300 byte Dilithium-3 signature)

Report contents Firmware SHA-256 hash, bootloader SHA-256, encryption-mode identifier ( "PPAES-XTS" ), wrap-format identifier ( "KYBR_HYB" ), host-supplied nonce, device serial, attestation pubkey, Dilithium pubkey ID

Key-release gating DEK derivation refuses unless host supplies key-release secret bound to a verified attestation report via HKDF(host_master, attest_pubkey, firmware_hash, "cs51-confidential")

Signing time (Dilithium-3) ~20 ms bit-serial at 100 MHz (boot-time only)

Ed25519 signing time ~5 ms at 100 MHz

Interop targets CCC RATS (Remote Attestation Procedures, RFC 9334); TCG SED (legacy support); TCG DICE; Intel TDX / AMD SEV-SNP / Arm CCA chaining; NVIDIA H100 confidential computing chaining; FIPS 140-3 Level 3

NVMe Vendor-Opcode Invocation

The host invokes any ACE operation through a single NVMe doorbell write with vendor opcode 0xC1 . The 256-bit submission-queue entry layout:

SQE Bit Range Field Meaning

[7:0] opcode 0xC1 — ACE invocation

[10:8] ace_op 1=VOXEL, 2=SCAN, 3=XFORM (+ CS-51 AI ops)

[31:16] CID Host-supplied command identifier

[63:32] NSID NVMe namespace identifier

[95:64] ace_count Number of LBAs the engine traverses

[191:96] reserved Future extension

[231:192] ace_lba Starting logical-block-address (low 40 bits)

[255:232] reserved Upper SLBA bits

A separate 128-bit parameter buffer ( ace_param ) accompanies the doorbell write. The NVMe engine synthesises a single completion-queue event (CQE) carrying the ACE result back to the host. Host-visible ABI is unchanged from CS-50—fan-out across N ACE instances and peer dies is transparent.

Inherited CS-50 RTL Modules

Module Function Status

autophi_aes256_xts.v Inline AES-256-XTS encryption/decryption with physical-page tweak Passing (NIST KAT + IEEE 1619 vectors)

autophi_aes256_core.v AES-256 encrypt/decrypt core Passing

autophi_aes_inline.v AES inline data-path wrapper Passing

autophi_aes_path.v AES path routing Passing

autophi_aes_sbox.v AES S-Box Passing

autophi_compute_engine.v Single-instance ACE (VOXEL/SCAN/XFORM) Passing

autophi_ace_bridge.v ACE-to-FTL bridge with reserved-CID marking Passing

autophi_cmd_arb.v Single-port FTL command arbiter Passing

autophi_ftl_core.v Flash Translation Layer (L2P mapping, sequential allocator) Passing

autophi_nvme_engine.v NVMe engine (doorbell, SQE decode, CQE synthesis) Passing

autophi_nvme_cpl_tlp.v NVMe completion TLP assembler Passing

autophi_pcie8_top.v PCIe 8.0 controller top-level Passing

autophi_pcie8_phy.v PCIe 8.0 physical-layer abstraction Passing

autophi_pcie8_mac.v PCIe 8.0 MAC + LTSSM Passing

autophi_pcie8_tlp.v Transaction Layer Packet parser/assembler Passing

autophi_gc_engine.v Garbage-collection engine Passing

autophi_ldpc_ecc.v Low-density-parity-check ECC block Passing

autophi_nand_model.v Behavioural NAND model Passing

autophi_dram_model.v DRAM controller model Passing

autophi_sd_native.v SD native interface Passing

autophi_sd_spi.v SD SPI interface Passing

autophi_sd_crc.v SD CRC module Passing

CS-50 Testbenches (Inherited, All Passing)

Testbench What It Tests Result

autophi_nvme_e2e_tb.v Host-to-host round-trip (write then read through L2P + NAND model) 5 PASS / 0 FAIL

autophi_walk_encrypted_tb.v Encrypted round-trip through AES-XTS path 8 PASS / 0 FAIL

autophi_walk_ace_tb.v Near-data SCAN with testbench-serviced fetches 3 PASS / 0 FAIL

autophi_walk_ace_real_tb.v Structural SCAN through bridge + arbiter + FTL 5 PASS / 0 FAIL

autophi_walk_ace_doorbell_tb.v Doorbell-invoked SCAN via vendor opcode 0xC1 5 PASS / 0 FAIL

autophi_pcie8_testbench.v Full controller-spine power-up (PHY, MAC, TLP, NVMe, FTL, GC, LDPC, AES, ACE) PASS (link-up asserted)

autophi_aes256_xts_tb.v AES-256-XTS NIST KAT + IEEE 1619 vectors PASS

autophi_aes256_xts_sector_tb.v AES-256-XTS sector-level test PASS

autophi_aes_inline_tb.v AES inline data-path test PASS

autophi_compute_engine_tb.v Single-instance ACE compute engine PASS

autophi_walk_tlp_loopclose_tb.v TLP loopback closure PASS

autophi_sd_native_tb.v SD native interface PASS

autophi_sd_spi_tb.v SD SPI interface PASS

Three-Layer WonderPhi Driver Stack (CS-51 Extensions)

Hardware — Verilog RTL

Module File Size State

N-port FTL arbiter autophi_multichannel_ftl.v 6,405 bytes Passing (4/4)

N-instance ACE + tree reducer autophi_ace_scaleout.v 11,930 bytes Passing (5/5)

Chip-to-chip peer arbitration autophi_peer_arb.v 12,717 bytes Passing (2/2)

PCIe P2P transport bridge autophi_p2p_bridge.v 8,845 bytes Passing (6/6)

Firmware — Freestanding C

Module Files State

Fan-out scheduler autophi_fw_scaleout.c (1,098 B) / .h (1,342 B) Stub

Peer-fabric controller autophi_fw_peer.c (1,754 B) / .h (1,500 B) Stub

Host Software — Linux C Drivers

Module Files State

Scale-out driver extension wonderphi_drv_scaleout.c (819 B) / .h (1,057 B) Stub

Reference user-space tool wonderphi_scaleout_example.c (922 B) Stub

Python Simulator Suite

Module Size Status Self-Test

ace_scaleout.py 20,297 bytes Passing 18/18 PASS (all 8 ops at N=1 byte-identical; N=4 VOXEL/SCAN/VECTOR_DOT/TOPK/ARGMAX/EMBED_LOOKUP/SOFTMAX verified)

peer_fabric.py 13,506 bytes Passing 24/24 PASS (5 topologies × multiple N values including UCIe + CXL variants)

multichannel.py 1,414 bytes Stub RTL version is canonical implementation

Foundry-Handoff Bundle Structure

The CS-51 handoff bundle mirrors the canonical foundry-handoff template designed for the Zettaflop-1Z accelerator (Project 23). The cri-one-pcie8-ssd-performance/handoff/ directory contains:

Directory Contents

rtl/ 23 synthesis-clean RTL modules (CS-50 inherited + CS-51 new)

testbench/ 14 testbench files (all passing under iverilog 12+)

docs/ 12 architecture, strategy, and specification documents

legal/ Tier 1 / Tier 2 / Tier 3 license terms + patent references

foundry_handoff/ Placeholder structure for DEF, GDSII, LEF, netlist, reports (DRC/LVS/timing/power), synthesis-clean Verilog

openlane/ OpenLANE2 flow configuration ( config.json targeting cs51_top )

package_design/ UCIe substrate specification

synthesis/netlists/ Post-synthesis netlist placeholder

scripts/ build_bundle.py (1,536 B), verify_bundle.py (2,389 B)

Verification and Build

Tool What It Verifies Result

python verify.py All refutable claims: RTL testbenches, simulator self-tests, benchmark, tapeout manifest checksums, document cross-references, compliance rules 12/12 PASS in

Prerequisites: Python 3.10+ (stdlib only, no external dependencies); iverilog 12+ for Verilog testbenches.

CIP Claim Families (Draft — 26 Claims)

Independent Claim Subject Dependent Claims

Claim 1 N-port FTL command arbiter with strict host priority + round-robin Claims 2–5

Claim 6 N-instance ACE fabric + tree/ring reducer on single die or UCIe chiplets Claims 7–11 (including 7 named kernel claims)

Claim 12 Chip-to-chip peer arbitration with single-doorbell fan-out Claims 13–15 (UCIe, CXL, runtime transport selection)

Claim 16 Post-quantum hybrid AES-XTS substrate (Kyber KEM + AES-KW) Claims 17–18

Claim 19 Confidential attestation tied to AES substrate —

Claim 20 AutoPhi family data-plane convergence (ties 19/710,460 and 19/646,681) —

Claims 21–22 Means-plus-function claims (N-stream arbitration, N-result reduction) —

Claim 23 Cartridge-on-die + Software-for-Data stack convergence (ties 19/540,453) Claims 24–26

Acquisition Tiers

Tier Price What Ships

Tier 1 — Mathematical Deposition $9,500 Patent spec + 20 claims + 8 figures + architecture overview + strategic docs (read-only, non-redistributable)

Tier 2 — Evaluation License $950,000 All of Tier 1 + complete RTL + Python sim + reference firmware + Linux driver. 90-day hands-on, NDA-gated. Fee credits to Tier 3.

Tier 3 — Full Use & Copy License $95,000,000 Complete foundry-handoff bundle (all of Tier 2 + KiCad + sign-off scripts + test patterns + tape-out manifest). Production rights to fab + ship + sublicense within field. Patent stays with inventor.

Full Acquisition Negotiated Tier 3 + patent assignment

CS-51 Family SKUs:

SKU Price

CS-51-PF (Peer-Fabric + VOXEL Mathematical Deposition) $250,000,000

CS-51-AI (AI-Pipeline Mathematical Deposition) $95,000,000

CS-51 Complete Scale-Out Bundle (PF + AI) $300,000,000 ($45M discount)

AutoPhi Engine (Board-Level PCB Automation)

The package includes the autophi_engine/ Python package—a board-layout automation engine with RAG-driven design-rule enforcement. Modules:

Subpackage Module Function

rag/ rules.py PCB design-rule database

rag/ stackup.py PCB stackup definitions

rag/ io_configs.py I/O configuration rules

rag/ components.py Component library

rag/ netlist.py Netlist generation

rag/ placement.py Component placement rules

rag/ routing.py Routing rules

rag/ superbase.py Superbase database interface

rag/ ti_knowledge.py TI reference knowledge base

rag/ ti_adj_catalog.py TI adjustable-output device catalog

rag/ project_ecosystem.py Project ecosystem context

layout/ board.py Board outline and layer management

layout/ router.py Trace routing engine

layout/ via_stitcher.py Via stitching for ground planes

layout/ placer.py Component placement engine

layout/ zone_filler.py Copper zone fill

output/ gerber.py Gerber file generation

output/ kicad_pcb.py KiCad PCB output

verify/ drc.py Design-rule checking

(root) engine.py Top-level automation engine

The engine includes 6 KiCad footprints in footprints/AutoPhi.pretty/ : TPS7A4700_RGW, LP3878_NGT, DS160PR810_NJX, AutoPhi_BGA256, DS280BR810_ZBF, TPS735_DRV, TPD4E004_DRY, PCIe_x16_Edge.

The TI references RAG knowledge base contains documentation for: DS160PR810, DS280BR810, LP3878-ADJ, MSP430F5529, TPS7A47, TPS735, TPS757, TPD4E004, SLLA335, SLLA414A, and hundreds of indexed application notes (SLYT-series, TIDU796, TIDRD10–TIDRD13, TIDUBG6, SNLU273, SSZT072, SLYP173).

Reference Design Files

The tidrd14/ directory contains the TI reference design TIDA-00423 schematic ( TIDA00423_Schematic.DSN ) and the accompanying Important Notice for Reference Designs (PDF).

The part-stock-mcp/ directory contains a parts-inventory MCP server (TypeScript/Node.js) with package.json , tsconfig.json , and Claude-settings template for integration.

What Is in the Package

1,166 SHA-256-checksummed files total (1,128 CS-50 baseline + 124 CS-51 extension, with overlapping handoff copies counted in the extension manifest)
CS-50 frozen baseline ( cri-one-pcie8-ssd/ ): 35 Verilog RTL modules, 10 firmware source + 10 header files, 4 Linux driver files, 7 Python simulator modules, 5 KiCad production BOMs/CPLs (M.2 22110), 5 architecture docs, filed patent application (DOCX + MD + 8 figures)
CS-51 extension ( cri-one-pcie8-ssd-performance/ ):
4 new Verilog RTL modules + 4 testbenches (all passing: 4/4 + 5/5 + 2/2 + 6/6 = 17/17 iverilog tests)
4 firmware C/H stubs (scaleout + peer)
2 Linux driver stubs + 1 example tool
3 Python simulators (ace_scaleout 18/18 PASS, peer_fabric 24/24 PASS, multichannel stub)
1 AI-pipeline benchmark script
17 strategy / architecture / specification Markdown documents
CIP claim draft (26 claims, 6 independent families)
Complete foundry-handoff directory (23 RTL + 14 testbench + docs + legal + OpenLANE2 config + UCIe substrate spec + foundry report placeholders)
Magento import CSV for store integration
5 build/verification/inventory scripts
verify.py (14,489 bytes)—single-command package truth-keeper, 12/12 PASS
AutoPhi Engine ( autophi_engine/ ): 19 Python modules, 6+ KiCad footprints, TI reference RAG knowledge base with 25+ component datasheets and 80+ indexed application notes
Patent documents: non-provisional application (31,786 bytes MD + 48,027 bytes DOCX), 20 apparatus/method claims, 8 USPTO figures, inventor depositions, prior-art queries, patent audit findings
Reference design: TI TIDA-00423 schematic (OrCAD .DSN)
Parts inventory MCP server (TypeScript)

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

The same 'PHANTOM SPEED' PCIe Gen 8.0 M.2 SSD with a steel plate 'PHANTOM PCIe Gen8 x4 / UNIT 7 - AUBURN, GA'

Footnotes

Product number 8501.
Family: autophi pcie cards.
Purchase: When you buy, you buy the use of that blueprint only.

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