42-software-driven-data

Description

42 — Software-Driven Data: Custom Storage Hardware & Software for Data

Status: L2 (Designed) — KiCad schematics, BOMs, mechanical and power documentation on file; Software for Data component at L3 (Prototyped) with 40 passing unit tests and 7 passing demos

Patent notice: Patent pending. Designs originally conceived alongside the AutoPhi family may relate to umbrella application US 19/540,453 (“Integrated Technology Portfolio”). Additional filings in the inventor’s portfolio include applications 17/687,656, 63/552,008, 29/839,062, 29/892,202, 17/454,808, 17/454,807, 18/650,137, 18/460,559, 18/370,908, 18/219,732, 19/031,884, 19/177,547, and others — see the full patent portfolio for scope and coverage. All rights to seek additional patent protection are expressly reserved by the inventor.

Licence: Proprietary and Confidential — © 2026 Christopher Gabriel Brown. All rights reserved.

Source IP corpus: Buy Invent A1–A1752 (1,752 inventor-authored entries, © 2017–2019 Christopher G. Brown)

Overview

This package holds three custom storage and accelerator hardware designs plus one software product under the Cri-One brand. Each hardware design is self-contained with its own KiCad project, datasheets, mechanical drawings, and architecture notes; the software product is a working pure-Python reference implementation. Together, the four sub-projects span the entire storage stack — from a pocket-sized encrypted USB vault through an enterprise SATA hot-swap SSD and an FPGA-based PCIe compute-plus-storage card, to the application-layer software that manages, encrypts, tags, and recalls data across all of them.

The product-as-a-whole is anchored on A649 (2017): “software software please make my software software information and data management creation and business software… an easy and re-sell able application package maker and formatted.”

Sub-projects 4 (cri-one-2-5-vault, cri-one-l3-ssd, cri-one-pcie-accelerator, cri-one-software-for-data)

Render specification 1 (photorealistic product-photography spec with negative prompts and generation settings)

Sub-Project 1: Cri-One 2.5″ Vault — Portable Encrypted NVMe Drive

A custom 2.5″ form-factor external NVMe SSD with a physical power switch . The enclosure wraps a standard M.2 2280 NVMe drive behind a USB 3.2 Gen 2×2 bridge, delivering approximately 2 GB/s sustained throughput over a single USB-C cable. When the slide switch is off, the drive is fully unpowered — the host sees a clean USB disconnect event, and the SSD draws exactly 0 W.

PCB dimensions 80 × 50 mm, 4-layer, 1.6 mm thick (JLC04161H-3313 impedance-controlled stack-up)

Power switch C&K JS202011SCQN SPDT slide switch — cuts VBUS upstream of all downstream components

Indicators Green power LED (Kingbright KP-1608SGC, 0603) + WS2812B-Mini RGB activity LED (3535 SMD)

Estimated BOM cost (qty 5) ~$245 including PCB, assembly, M.2 SSD (Samsung 990 Pro 2 TB), and 3D-printed shell

BOM Summary (26 line items)

USB SuperSpeed pairs (4 diff pairs, 10 Gbit/s per lane) 90 Ω differential 5/5 mil ≤5 mil intra-pair, ≤50 mil inter-pair

PCIe Gen 3 ×2 pairs (4 diff pairs + REFCLK) 85 Ω differential 5/9 mil ≤5 mil intra-pair, ≤100 mil inter-pair

cri-one-2-5-vault.kicad_pro / .kicad_sch / .kicad_sym / .kicad_prl KiCad 9/10 project with symbols and schematic

notes/layout-guidelines.md 4-layer stack-up, impedance rules, DRC targets, placement sketch (219 lines)

notes/mechanical.md 2.5″ enclosure dimensions, 3D-print specs, assembly procedure (136 lines)

_gen_schematic.py / _fix_footprints.py Schematic generator and footprint correction scripts (694 lines combined)

Sub-Project 2: Cri-One L3 SSD — Custom 2.5″ SATA Hot-Swap Drive

A from-scratch custom 2.5″ SATA SSD designed to slot into HPE ProLiant Smart Carrier sleds via the standard SAS/SATA backplane. The architecture uses a hardware SATA-to-managed-NAND bridge chip — no FPGA, no firmware to write , no Phison or SMI partnership required. The flash translation layer, wear levelling, ECC, and bad-block management are all handled inside the eMMC chip’s built-in controller; the bridge chip provides fixed-function SATA protocol translation via mask-ROM firmware.

Connector SATA 22-pin edge (15-pin power + 7-pin data), gold-finger pads on PCB (ENIG finish, 30° chamfer)

Data interface SATA III differential pairs — 100 Ω impedance, ≤5 mil length matching

Storage medium Managed NAND (eMMC) — Kingston EMMC256G-W729-T01U, 256 GB, BGA-153 (11.5 × 13 mm)

Bridge chip Marvell 88SA8052 (sourcing in progress; JMicron JMB389/390 as documented fallback)

Design state v0 design exploration — architecture, mechanical, power, tentative BOM on file; blocked on bridge-chip datasheet

Includes bridge chip (Marvell 88SA8052, sourcing), 256 GB eMMC (Kingston BGA-153), 2× buck regulators (TPS62823), LDO for 1.8 V VCCQ (TPS73218), power supervisor (TPS3823-33), optional Smart Carrier EEPROM (DS24B33), activity LED, decoupling capacitors (100 nF × 8, 10 μF × 4, 22 μF × 2, 100 μF tantalum × 2), pull-up resistors, inductors, and optional crystal. Custom JLCPCB PCB with ENIG gold-finger SATA edge, plus 3D-printed or modified stock 2.5″ enclosure and HPE Smart Carrier sled.

Plan A — Alternative bridge chip JMicron JMB389 (CF/SD-to-SATA) or JMB390 (SD-to-SATA) Public

Plan B — MCU-based SATA target STM32H743ZIT6 (Cortex-M7 480 MHz with SATA controller) + eMMC via SDIO Public, full ecosystem

Plan C — Drop to L2 build M.2-SATA-to-2.5″-SATA carrier (2-weekend project) N/A

mechanical.md SFF-8201 dimensions, SATA connector pinout, HPE Smart Carrier compatibility matrix, mounting holes (153 lines)

power.md Power tree, buck regulator selection, hot-plug staggered-ground sequence, power-good supervision (120 lines)

A custom HHHL (Half-Height Half-Length) PCIe card that is both a compute accelerator and a 1 TB persistent storage device. Eight RISC-V soft cores, 1 GB DDR3 working memory, 1 TB on-board eMMC, a Lattice ECP5-85F FPGA, and PCIe Gen 2 ×4 host connectivity — all on a single-slot, low-profile card with no auxiliary power connector. Built entirely on an open FPGA toolchain (Yosys + nextpnr + Project Trellis). Spiritual successor to the Intel Xeon Phi 3120A, but with on-board SSD inside.

PCIe edge connector x16 mechanical (89 mm, 164 pins), x4 electrical (32 pins wired), ENIG + 30° chamfer, 1.6 mm PCB

FPGA Lattice ECP5-85F (LFE5UM5G-85F-8BG381C) — 84K LUTs, 3.7 Mbit BRAM, 4× 5G SerDes, 381-pin caBGA (17 × 17 mm)

Soft CPUs 8× VexRiscv RV32IM @ 100–150 MHz, 5-stage pipeline, ~1,500 LUTs/core, 4 KB I-cache + 4 KB D-cache each

Working memory 1 GB DDR3-1600 (Micron MT41K512M16HA-125:E, FBGA-96, 16-bit interface, 12.8 GB/s peak)

Compute accelerator Host writes RISC-V code + input data to BAR2/BAR4; 8 cores execute in parallel using DDR3; host reads results via DMA. Use cases: matrix math, crypto, signal processing, custom kernels.

1 TB block storage Host accesses 1 TB of eMMC as a standard block device via PCIe. Exposed as raw blocks; host chooses the filesystem (ext4, XFS, ZFS, BTRFS).

Computational storage Card reads eMMC, RISC-V cores filter/process on-card, only results sent to host. A 100 MB log scan moves 100 MB internally but returns only the 5 KB of matches.

BAR0 64 KB LiteX MMIO — register file, DMA descriptors, eMMC controller regs, RISC-V reset/run controls

Key components: Lattice ECP5-85F FPGA ($45), Micron DDR3 1 GB ($8), 4× Kingston 256 GB eMMC ($60 total), Winbond 128 Mbit SPI flash ($1.50), 5× buck regulators (TPS54620, TPS62085 ×2, TPS62823, TPS73218), TPS3823 power supervisor, TPS24700 hot-swap controller, SY58608 clock buffer, 4× WS2812B-Mini activity LEDs, Noctua NF-A4x10 fan ($15), low-profile PCI bracket ($3), 80× decoupling capacitors, 30× bulk capacitors, and JLCPCB 6-layer impedance-controlled PCB with ENIG finish and gold-finger chamfer.

architecture.md Full block diagram, memory map, data paths, storage architecture, clock domains, boot sequence 225

mechanical.md HHHL dimensions, PCIe edge-connector spec, bracket, internal layout, heatsink/fan, server compatibility matrix 172

bom-tentative.csv 36-line-item BOM with costs and status flags 36

QUICKSTART.md 10-phase bring-up guide from toolchain install to custom HDL accelerators 241

cri_one_accelerator.py LiteX SoC target — CRG, custom HDL slot, 8-core VexRiscv, DDR3, PCIe, eMMC, WS2812B LEDs, fan PWM 359

cri_one_platform.py Pin-assignment stub for custom HHHL board 520

firmware/hello.c RISC-V “hello world” — UART driver, DDR3 memory test, custom-accelerator loopback, LED blink 164

firmware/matmul_kernel.c Matrix-multiply compute kernel for RISC-V cores —

host-driver/cri_one_driver.c Linux PCIe kernel module skeleton — probe, BAR mapping, /dev/cri_one0 chardev, ioctl for firmware load / core start-stop, mmap for DDR3 319

notes/risc-v-cores.md VexRiscv vs Rocket vs BOOM vs CV32A6 vs NEORV32 vs PicoRV32 comparison 182

HPE Server Slots Compatible?

A working reference implementation of Cri-One Software for Data — pure Python, standard library only, no external dependencies for the core runtime. Software for data that does not lose what it stores, that lets people and AI work on the same scenarios at the same time, and that can be packaged, shipped, and resold as a unit. The software component is at L3 (Prototyped) with 40 passing unit tests across 5 test files and 7 passing demo scripts.

Scenario-level redundancy (not byte-level) erasure.py A1647–A1650 (“quantum RAID processing / memory / service / scale”)

Silent-corruption detection (end-to-end Merkle tree) cartridge.py A1059, A246, A170, A1515, A1556

Double-failure rebuild array.py A222, A234, A246, A260, A1229, A1672

Human + AI write tagging without silent loss conflict.py, mciau.py A1229 (“MCIAU… instructional software that tells the AI what to do”)

Hot add / subtract cartridges live array.py A246 (“raid multi sd flash card device… addition and subtract able”)

Format-doubling encryption envelope envelope.py A376 (“format doubling… encrypted then translated”)

License envelope with kill-switch license.py A1239–A1243 (“data code kill switch agreement”)

Real Claude AI agent in the co-work loop agents/anthropic_agent.py, agents/orchestrator.py A1229

0x083–0x0B3 48 bytes Section offsets and lengths (manifest, scenario block, license envelope)

Inner (per-scenario) Each scenario payload + embedding K_scen = SHAKE256(master_key || cartridge_uuid || scenario_uuid, 32) HMAC-SHA256(K_scen, plaintext)

Outer (per-cartridge) CSV-styled manifest K_manifest = SHAKE256(master_key || cartridge_uuid || “manifest”, 32) Footer HMAC keyed by K_manifest

Conflict Resolution Policy (Human + AI, A1229)

Critical invariant: No conflicting write is silently dropped. Every conflict results in either an explicit merge or a preserved fork.

Collaborative RAID Array Protocol

An array of M cartridges: K data shards + (M−K) parity shards. Two-parity scheme: P0 = XOR of all data shards; P1 = XOR of cyclically-shifted data shards. Tolerates loss of any 2 cartridges without scenario loss (RAID-6 in spirit but operating on scenario chunks rather than disk blocks). Fixed 4 KiB chunk size, single-byte cyclic shift for P1 in the reference implementation.

tests/ (5 files, 40 test methods) test_core, test_array, test_conflict, test_recall, test_agent 726

demos/ (7 scripts) Build cartridge, build array, silent corruption, double-failure rebuild, human/AI conflict, hot add, real AI agent 673

What the buyer gets: The complete cri-one-software-for-data/ source tree — perpetual, irrevocable, worldwide, non-exclusive, royalty-free, sublicensable licence to run, modify, fork, redistribute, and incorporate into commercial offerings. The buyer owns every modification and derivative work.

What the licensor retains: (1) The Buy Invent A1–A1752 corpus (© 2017–2019 Christopher G. Brown) — referenced for provenance only via A-number citations, not part of the distribution. (2) Any patent that may issue from the method-claim filing (possible umbrella coverage under US 19/540,453). (3) The “Cri-One” and “Buy Invent” trademarks. A non-assertion covenant covers the buyer’s use of the source code as delivered.

What ships in lieu of the corpus: sample_corpus.txt — 25 synthetic entries in the same format so demos and tests run out of the box.

README.md Master index with sub-project table, maturity notes, patent status, quick navigation

PLAYBOOK.md Internal playbook — identity, hook lines, reply patterns, status and gaps

MANIFEST.json Machine-readable package manifest (name, title, inventor, maturity, file categories)

RENDER_SPECIFICATION.md Photorealistic render spec — 3 camera views, generation settings (1344 × 896, DPM++ 2M Karras, CFG 5.0), negative prompt

google_patents_search_list.txt 215 USPTO application references across the inventor’s full patent portfolio

sales-pitches/businesscartridge26_STORE_PRODUCT_DESCRIPTION.html Existing storefront listing for the Software for Data component

sales-pitches/businesscartridge26_PRODUCT_CARD.md Product card summary

datasheets/ (2 PDFs) Marvell 88SA8052 product brief (2015-09), Marvell 88SF9xxx product brief (2011-04)

• cri-one-2-5-vault/ — KiCad 9/10 project (6 KiCad files), JLCPCB-ready BOM (26 components), 2 DXF mechanical drawings, schematic block diagram, pin-level netlist, layout guidelines with impedance rules, mechanical spec with 3D-print dimensions, and 2 Python generator scripts (694 lines)
• cri-one-l3-ssd/ — Architecture block diagram, SFF-8201 mechanical spec, power tree with hot-plug analysis, tentative BOM (23 components), datasheet-hunt strategy, and three-tier fallback plan
• cri-one-pcie-accelerator/ — LiteX SoC target in Python (359 lines), platform stub (520 lines), RISC-V firmware in C (164 lines), Linux PCIe kernel-module skeleton in C (319 lines), Python userspace tool, 6-core comparison study, LiteX setup guide, 36-component BOM, and 10-phase quickstart
• cri-one-software-for-data/ — 12 Python modules (2,358 lines), 5 test files with 40 unit tests (726 lines), 7 demo scripts (673 lines), architecture specification with binary format and protocol definitions, commercial source licence, pyproject.toml packaging, and sample corpus

Total source code: 5,330 lines of Python + 744 lines of C . Total documentation: 4,839 lines of Markdown across 28 files.

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

© 2026 Christopher Gabriel Brown. All rights reserved. “Cri-One,” “Cri-One Software for Data,” “Cri-One Collaborative RAID,” “Cri-One Business Cartridge,” and “Buy Invent” are product designations of the inventor. Patent pending.

Photo