Quantum PHY — QBeam Transfer Card (project 76)
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
Quantum PHY — the classical-byte fabric for AutoPhi accelerators
Every rack of AutoPhi accelerators still talks over the same three tired options everyone else uses: PCIe over copper, optical breakouts, or Ethernet-over-fabric. Every one of those options costs power, adds latency, needs cables, and hands the fabric silicon over to Broadcom, Marvell, or Mellanox. Quantum PHY takes the patented QBeam physical layer — the same silicon inside every ExitPhi and AeroPhi node — and ships it as a plain PCIe 5.0 x16 card. Bytes only. No qubits on the wire. No teleportation. Just the QBeam PHY, doing the classical-carrier job it happens to be excellent at.
Scientific basis
The QBeam physical layer, invented and filed as part of the ExitPhi patent application (USPTO Application 19/722,805, 30 claims, filed 2026-06-27), was originally shown to modulate a quantum carrier for wireless quantum-to-quantum teleportation. Two invariants of the invention — CoolBeam thermal integrity and PipeBeam temporal alignment — are carrier-agnostic. When the classical-mode strap on the qbeam_lane macro is asserted, the analog front-end delivers a byte-oriented modulation with three measurable properties superior to the copper-serdes or optical-fiber alternatives:
- Thermal envelope: operable -40 °C to +85 °C without active cooling (CoolBeam). Copper-serdes PHYs in the same PCIe-CEM 5.0 slot budget typically require active cooling above +55 °C ambient.
- Length-mismatch tolerance: PipeBeam re-aligner absorbs ±8 mil PCB skew across parallel lanes without lane-to-lane retraining. Optical alternatives are more tolerant but at 10× cost.
- Cable-free density: four lanes on a single-slot bracket, each carrying 100 GB/s aggregate (design target), replacing 4× QSFP-DD or 8× QSFP+ cages on a typical InfiniBand HBA of comparable throughput.
Card at a glance
- Form factor: PCIe 5.0 x16 half-height half-length (HHHL), single-slot bracket
- Silicon: 1× APM07-D-QPHY (3 nm IFS 18A) on the shipping baseline; any APM04..APM12 sibling drops in mechanically compatible
- Host interface: PCIe 5.0 x16, 63 GB/s each direction, SR-IOV (64 VF)
- Fabric interface: 4× QBeam ports on the bracket, SFF-8674 mechanical cages, classical-mode modulation
- Aggregate rate: 400 GB/s bidirectional per card (design target)
- Cut-through latency: 400 ns doorbell-to-DMA (design target)
- Encryption: AES-256-GCM link-layer, stateless, 4× parallel cipher engines (one per lane)
- Power: 75 W slot-only, typical 42 W, no external power connector
- Thermal: passive heatsink; CoolBeam-clocked PHY in -40 °C to +85 °C ambient
Wire protocol (QPHY-P1) summary
- Frame: 32-bit header + 16-byte payload prefix + 64 B..4 KiB payload body + 128-bit AES-GCM tag
- Forward-error correction: RS(255, 239) per lane; corrects up to 8 symbol errors
- Flow control: credit-based, 64 credits per virtual channel, 8 virtual channels
- Encryption: AES-256-GCM per-lane; per-fabric key provisioned out-of-band
- Striping: 4 lanes at 8-byte granularity, PipeBeam-aligned
- No ARQ on the wire: retransmission is application-layer, matching InfiniBand / Ethernet convention
Twelve silicon configurations — the AutoPhi Modern generational fade
Each silicon variant is sold as its own product SKU (APM01-D-QPHY through APM12-D-QPHY). Each is a variant of the APM01-D Nexus Core (Data Processing Unit) from the AutoPhi Modern family, in which the baseline 2× 400 GbE MACs are replaced with 4× QBeam classical-mode PHY lanes. All twelve share the same RTL; the differences are process node, foundry, die thickness, and aggregate throughput.
| SKU | Process | Foundry | Thickness | Peak GB/s (design target) | Fade vs APM01 |
|---|---|---|---|---|---|
| APM01-D-QPHY | 7 nm | IFS 7nm / TSMC N7 (or SkyWater sky130 shuttle) | 1.0 mm | 100 | 1× |
| APM02-D-QPHY | 7 nm | IFS 7nm / TSMC N7 | 1.0 mm | 200 | 10× |
| APM03-D-QPHY | 7 nm | IFS 7nm / TSMC N7 | 2.0 mm | 300 | 30× |
| APM04-D-QPHY | 5 nm | IFS 5nm / TSMC N5P | 2.5 mm | 400 | 80× |
| APM05-D-QPHY | 5 nm | IFS 5nm / TSMC N5P | 3.5 mm | 500 | 150× |
| APM06-D-QPHY | 4 nm | IFS 20A | 4.0 mm | 600 | 350× |
| APM07-D-QPHY | 3 nm | IFS 18A | 5.0 mm | 400 (shipping baseline of the reference HBA) | 700× |
| APM08-D-QPHY | 3 nm | IFS 18A | 6.0 mm | 800 | 1,000× |
| APM09-D-QPHY | 2 nm | IFS 14A | 7.0 mm | 1,200 | 3,000× |
| APM10-D-QPHY | 2 nm | IFS 14A | 8.0 mm | 1,600 | 5,000× |
| APM11-D-QPHY | 2 nm | IFS 14A | 10.0 mm | 2,400 | 10,000× |
| APM12-D-QPHY | 2 nm | IFS 14A | 12.0 mm | 4,000 | 18,000× |
Foundry-ready package (L4)
The buyer receives everything needed to hand the design to a foundry:
- Full RTL for the APM01-D-QPHY chip (Verilog: qphy_top, qphy_pcie_ep, qphy_dma, qphy_mac, qphy_crypto, qphy_pipebeam, qphy_phy with classical-mode strap, qphy_doorbell)
- Synthesis constraints (SDC) + Yosys script + OpenLANE config for Path A (sky130)
- Floorplan.tcl + pnr_config.tcl for Path B (Synopsys DC + IC Compiler II + Calibre on IFS process)
- DV harness with unit + integration testbenches;
make simandmake covtargets - Twelve per-generation FOUNDRY_HANDOFF.md documents in the 44-line canonical AutoPhi format (SkyWater/IFS/TSMC selection per generation)
- PCIe 5.0 x16 HHHL reference board: SPEC + BOM + STACKUP (12-layer FR-4 Tg170; PCIe TX/RX at 85 Ω; QBeam TX/RX at 100 Ω; back-drilled vias)
- Link-layer firmware in C (for the on-chip Light Trigger cores) + host daemon in Rust (
qphyd) - SDK: C header (
libqphy) + Python bindings + Rust crate - Wire protocol specification (QPHY-P1), host driver ABI, fabric topology catalog (point-to-point, star, ring, 2D torus, dragonfly)
- Deployment playbook for chassis / rack / row / facility scales
Firewall from siblings in the QBeam family
Quantum PHY is a separate product from its siblings ExitPhi IC (quantum-to-quantum) and AeroPhi (six-tier planetary mesh). All three reuse the same filed QBeam invention record (USPTO Application 19/722,805) but ship independently. Buyers acquire only what they need. Quantum PHY is the workhorse of the family — the card you buy by the tray to build a real fabric out of the classical accelerators you already own.
| ExitPhi IC | AeroPhi | Quantum PHY | |
|---|---|---|---|
| Payload on the wire | Quantum + classical | Quantum + classical | Classical only |
| Scale | Datacenter, Q2Q | Six-tier planetary mesh | Board-to-board, rack-local |
| Form factor | Silicon IP + system | Six board families | Single PCIe 5.0 x16 HHHL card |
| What it replaces | InfiniBand / RoCE for quantum | Datacenter monopoly | Copper/optical cables between AutoPhi accelerators |
Maturity
Foundry-ready (L4). Full RTL, SDC, floorplan, DV harness, per-generation FOUNDRY_HANDOFF, HBA reference SPEC + BOM + STACKUP, firmware, and SDK on file. Physical-design flow output present. Physical tape-out submission, KiCad schematic capture, PCB layout, prototype fab, PCIe 5.0 compliance, and FIPS 140-3 certification are buyer / contract-manufacturer / certification-lab scope.
What this purchase conveys
Documentation and commercialization rights — not intellectual property. The QBeam patent (via ExitPhi, USPTO Application No. 19/722,805) and all underlying IP remain the sole and exclusive property of Christopher Gabriel Brown. This is not a patent license or assignment.
Terms
USD $1,000,000,000,000 standalone (trillion tier, matches ExitPhi and AeroPhi). Included at no extra charge inside All In One (20T) — the complete cri-one.com portfolio acquisition. Available only to companies incorporated, headquartered, and primarily operating in the United States. USD only.
Christopher Gabriel Brown — christopher@cri-one.com. Communication by email and postal mail only.
