Inside the GDSII

A 38-second read-along · Christopher Gabriel Brown

63 of 71 AutoPhi designs are built end-to-end as RTL plus pre-GDSII plus GDSII. This piece walks through one of them, layer by physical layer.

one chip, laid out

13 PHYSICAL LAYERS

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One AutoPhi die, laid out. This is the top-down view: thin coloured rails crossing a dense substrate. One of sixty-three designs built end to end in open EDA, each one with every physical layer rendered as a picture.

The layers lift apart. The flat image splits into its thirteen SKY130 drawing layers — diffusion, polysilicon, local interconnect, metal one through metal five, plus the via layers that connect them. Each one in its own colour.

Each layer has its own job. Diffusion holds the transistor active areas. Poly is the gates. Local interconnect li1 wires them together. Metal one through metal five carry signals across the die. The vias punch through.

Thirteen layers. Every one, rendered.

The IP is the chip →Vertical threading →The 3D stack →