39-autophi-pcie5-256
Asset valuation: $3,600,000,000. Components: U7, U11 (ADS1115 ADCs) + U13 (24LC256 EEPROM) + U18 (BQ25798 charger) Strategy: All four sit on the shared I2C bus (SMCLK/SMDAT). They don't need dedicated BGA pins for the bus itself — only for interrupts and address
A chip should not have to wait on the board underneath it. Product 39 is that board: a full PCIe x16 add-in card drawn around a custom 256-ball AutoPhi package in its QSFP28 optical configuration. Sixteen lanes run from the gold fingers through four linear redrivers to the package, built to the Gen 5 target of 32 gigatransfers per lane - 64 gigabytes per second each way - with the redrivers validated at Gen 3 against the TI reference. The other sixteen high-speed pairs leave through two QSFP28 cages behind a Gen 4 retimer, so the card has an optical way out as well as the slot.
Around the package sits what a card needs to stand on its own: a 16-bit DDR3 chip, a seven-rail power tree fed from the slot's twelve volts, a battery charger with USB-C, and an MSP430 management MCU that reads the power-good chain and passes it to the FPGA. All 64 management GPIOs are spoken for. The schematic is ERC-clean across both the 256 and 1536 board targets, 27 hierarchical sheets deep, and the PCB has the BGA-256 footprint placed with a routing plan documented.
This is for datacenter operators and engineering buyers who want a card design they can open and build on, not a datasheet. The buyer walks away with the KiCad 10 schematic and PCB sources, the 56-script Python pipeline that generates and maintains them, the custom floorplan plugin and the signal-integrity reference data. The AutoPhi package and the patents behind it stay with the inventor.
Description
Status: Active design — schematic ERC-clean (0 errors / 0 warnings across both 256 and 1536 board targets), 27 hierarchical sheets, 20-sheet generated schematic tree, PCB layout with BGA-256 footprint placed, multi-phase routing plan documented.
Overview
Product 39 is the BGA-256 variant of the AutoPhi v19 PCIe 5.0 accelerator board in its QSFP28 optical configuration. It is a full PCIe x16 add-in card design built around a custom 256-ball BGA FPGA/ASIC package (20 × 20 mm, 1.0 mm pitch), carrying four TI DS80PCI810 8-channel linear PCIe redrivers (two banks of 8 lanes each completing a full x16 link), a DS280BR810 Gen 4 retimer, DDR3 memory (16-bit single-chip on BGA-256; 64-bit four-chip on the companion BGA-1536), a TI BQ25798 battery charger with USB-C, an MSP430F5529 management MCU, dual QSFP28 optical cages with Amphenol connectors, and a complete power tree with seven voltage rails. The design is captured in KiCad 10, generated and maintained by a 56-script Python pipeline, and ships with a custom KiCad floorplan plugin, signal-integrity reference data, and all schematic/PCB source files.
The BGA-256 package provides 48 high-speed I/O (HSIO) differential pairs and 64 management GPIOs. HSIO pairs 0–31 carry PCIe lanes (16 TX + 16 RX), pairs 32–47 carry QSFP28 optical lanes. Management GPIOs 0–23 serve I2C, SPI, JTAG, UART, and sideband signals; GPIOs 24–61 are allocated to 16-bit DDR3 (38 pins); GPIOs 62–63 provide charger interrupt and status. All 64 GPIOs are consumed at 100% utilisation on the BGA-256 variant.
PCIe generation target Gen 5 (design rules and channel budget); redrivers validated at Gen 3 per TI TIDU796
Edge connector J5 — standard PCIe x16 gold-finger (BUS_PCIexpress_x16 footprint), 164 pins (82 per side)
Reference clock 100 MHz from Si5351A (U14) — CLK0 output, single-ended LVCMOS with 50 Ω REFCLK_N termination or optional LVCMOS-to-HCSL buffer
Sideband signals PCIE_PERST_N, PCIE_WAKE_N, PCIE_CLKREQ_N, SMCLK, SMDAT, PRSNT1#/PRSNT2# (tied to GND per spec)
PCIe Signal Path and Conditioning
Each of the 16 PCIe lanes traverses the following differential signal path (TX direction example):
BGA TX pad (APH_HSIO_PAIR_nn_P/N) → AC coupling cap (0.1 µF 0402 X5R 16 V) → DS80PCI810 INB input → DS80PCI810 OUTA output → AC coupling cap → J5 PCIe edge connector TX pad
The RX direction is the mirror: J5 RX pad → AC cap → DS80PCI810 INA → DS80PCI810 OUTB → AC cap → BGA RX pad. This creates 8 AC coupling capacitors per lane (4 sides × 2 differential lines), for a total of 128 AC coupling caps across all 16 lanes. All caps are identical: 0.1 µF 0402 X5R 16 V.
Redriver / Retimer Ref Package Lane Assignment Role
DS80PCI810 (8-ch linear redriver) U3 NJY0054A (54-pin) Lanes 0–3 (bank A) PCIe x16 path, first 4-lane bank
DS80PCI810 U6 NJY0054A Lanes 4–7 (bank A) PCIe x16 path, second 4-lane bank
DS80PCI810 U17 NJY0054A Lanes 8–11 (bank B) PCIe x16 path, third bank; PCIE_SMCLK/SMDAT sideband
Redriver configuration (per TIDU796 compliance baseline): Pin mode (ENSMB low); VOD Level 6 (VODA1/VODB1 = 1, VODA0/VODB0 = 0 via 1 kΩ strap resistors); EQ to be derived per-channel via SI simulation (TIDU796 Gen 3 Level 1 is the reference, not a direct copy); RXDET float for auto-detect. Per-retimer decoupling: 8 capacitors (10 µF bulk + 1 µF mid + 0.1 µF fine on VIN pin 24, plus 0.1 µF on each VDD pin 9/14/36/41/51) × 4 retimers = 32 decoupling caps .
256-Bit BGA Interface
Reference designator U15 (BGA-256 variant); U16 (BGA-1536 variant, 44 × 30 mm, 0.9 mm pitch)
HSIO differential pairs 48 pairs (96 balls): pairs 0–15 = PCIe TX, 16–31 = PCIe RX, 32–47 = QSFP28
GPIO_24–61 DDR3 16-bit interface 38 DDR_A0–A14, DDR_BA0–BA2, DDR_CK_P/N, CKE, CS_N, RAS_N, CAS_N, WE_N, ODT, RESET_N, DQ0–DQ15, DQS0/1_P/N, DM0/1
VTT termination 0.75 V (TPS51200 sink/source LDO, U53) Same + 23 fly-by termination resistors (39 Ω 0402)
+3.3V 3.3 V TPS75725 (1 A LDO) U1 KTT TO-263-5+EP 12 V → 3.3 V; EN tied to +12 V (always-on)
+3.3V_B 3.3 V TPS7A4700 (precision ANY-OUT LDO) U42 RGW VQFN-20 12 V → 3.3 V; ANY-OUT strapping: 3P2V + 0P1V = 3.3 V
+5V 5.0 V TPS75725 U22 KTT TO-263-5+EP 12 V → 5.0 V
+2.5V_B 2.5 V TPS735 (200 mA LDO) U43 DRV WSON-6 3.3V_B → 2.5 V (DS280BR810 retimer core supply)
+1.5V 1.5 V TPS62080 (3 A buck) U52 SON-8 (2.5 × 2.5 mm) 3.3 V → 1.5 V; 2.2 µH inductor; DDR3 VDD/VDDQ
+1.0V 1.0 V LP3878-ADJ + ADP1706-1V0 U38/U46, U20 NGT / TSOT-23-5 3.3 V → 1.0 V (FPGA core)
VTT_DDR 0.75 V TPS51200 (3 A sink/source) U53 VSON-10 1.5 V → 0.75 V; REFIN from VDDQ/2 divider
Power-good chain: wired-OR of PG_3V3 (U1), PG_5V (U22), and PG_1V5 (U52) into a single PWR_GOOD_ALL signal, pulled up to +3.3 V via 10 kΩ. On BGA-256 (no free GPIO), PWR_GOOD_ALL is read by the MSP430 MCU and forwarded to the FPGA via I2C or MCU_IRQ.
Cage connector QSFP28 stacked 2 × 1 cage (Amphenol), custom footprint QSFP28_STACKED_2x1_PLACEHOLDER.kicad_mod
High-speed lanes 4 lanes per port × 2 ports (BGA-1536); 1 port (BGA-256, constrained by pin budget)
ESD protection U25, U26 (TPD4E004) on QSFP sideband; U45, U48 (TPD4E004) inline on QSFP high-speed pairs
Sideband signals Q0_MODSEL_N, Q0_RESET_N, Q0_MODPRS_N, Q0_INT_N, Q0_LPMODE, plus shared I2C (SMCLK/SMDAT)
Power supply to cage +3.3V_B
U49 MSP430F5529 LQFP-80 (12 × 12 mm, 0.5 mm pitch) Board management MCU — telemetry, fan control, retimer config, USB serial, LED PWM dimming, power-good monitoring, I2C master to EEPROM/ADCs/charger/clock-gen I2C, SPI, UART, JTAG, USB 2.0
U7 ADS1115-A MSOP-10 (3 × 3 mm, 0.5 mm pitch) 4-channel 16-bit I2C ADC for power/thermal telemetry (address 0x48) I2C (SMCLK/SMDAT)
U11 ADS1115-B MSOP-10 Second 4-channel ADC (address 0x49) I2C
U13 24LC256 SOIC-8 (3.9 × 4.9 mm) 256 kbit I2C EEPROM for board configuration/calibration (address 0x50) I2C
U8 W25Q128JV SOIC-8 128 Mbit SPI flash for FPGA bitstream / MCU firmware SPI (MOSI/MISO/SCK/CS)
U14 Si5351A MSOP-10 3-channel I2C clock generator: CLK0 = 100 MHz PCIe REFCLK, CLK1 = 100 MHz system, CLK2 = 10 MHz auxiliary; driven from 25 MHz crystal I2C
U18 BQ25798 QFN-24+EP (4 × 4 mm, 0.5 mm pitch) Multi-chemistry battery charger with USB-C input, MPPT, I2C configuration I2C + dedicated INT/STAT to FPGA GPIO_62/63
U10 QFN-48 (unidentified) QFN-48 (7 × 7 mm, 0.5 mm pitch) Suspected multi-rail PMIC (likely 1.8 V source) Pending identification
U12, U50 TSSOP-28 (unidentified) TSSOP-28 (4.4 × 9.7 mm) Suspected PCA9685 16-channel PWM controllers I2C
U24, U26–U28 SFH2400 (0805 / 2012 Metric) Optical photodetectors for thermal/light sensing — +3.3 V
J5 BUS_PCIexpress_x16 Connector_PCBEdge:BUS_PCIexpress_x16 PCIe x16 edge connector (164 pins)
J1 BATT_LIION JST_PH_B2B-PH-K 1x02 P2.00mm Li-ion battery connector for BQ25798 charger
J2 PWR_8p_2.54 PinHeader 2x04 P2.54mm Vertical JTAG / SWD programming header (TDI, TDO, TMS, TCK, RST, TEST, VCC, GND)
QSFP cage QSFP28 stacked 2 × 1 QSFP28_STACKED_2x1_PLACEHOLDER Amphenol QSFP28 optical transceiver cage
REF**1 CONN38_1888617-1_TEC CONN38_1888617-1_TEC 38-pin TE Connectivity Peltier TEC connector
01 01_central_processor.kicad_sch BGA FPGA/ASIC with full pin wiring U15 (BGA-256), U16 (BGA-1536) rewrite_sheet_01.py
02 02_pcie_retimers_redrivers.kicad_sch 4× DS80PCI810 redriver instances + DS280BR810 retimer U3, U6, U40, U41 rewrite_sheet_02.py
03 03_pcie_x16_edge_connector.kicad_sch PCIe x16 edge connector J5 with full 164-pin mapping J1, J5 rewrite_sheet_03.py
04 04_power_tree.kicad_sch Power regulators and voltage distribution U1, U6, U7, U12, U13, U14, U42, U43 —
05 05_compute.kicad_sch Compute-domain regulators and logic U20 (ADP1706-1V0), U30, U44 —
06 06_telemetry_clock.kicad_sch Telemetry ADCs and clock generation U21, U22, U23, U24, U29 —
07 07_optical_thermal.kicad_sch Optical photodetectors and thermal ESD U25, U26, U27, U28 —
08 08_esd_protection_array.kicad_sch ESD arrays, MCU, LDOs U45–U50 —
09 09_bracket_i_o_connectors.kicad_sch Bracket I/O: power header, SoM mezzanine, microSD J2, J3, J4 —
10 10_mounting_test.kicad_sch Mounting holes and test points MH1–MH6, TP1–TP6 —
11 11_passives.kicad_sch Bulk passives, supercaps, LED drivers, PCIe edge, DDR3 chips CS1–CS4, D1–D4, J5, U9/U17–U19/U31–U39 —
12 12_retimer_decoupling.kicad_sch 32 per-retimer decoupling capacitors 28 components gen_retimer_decoupling.py
13 13_pcie_ac_coupling.kicad_sch 128 PCIe AC coupling capacitors 128 components gen_ac_coupling.py
14 14_ddr3_aux.kicad_sch DDR3 VREF dividers, pull-ups, reset, DS80 straps 22 components gen_ddr3_aux.py
15 15_power_supplements.kicad_sch TPS62080 1.5 V buck + TPS51200 VTT 13 components gen_power_supplements.py
16 16_ddr3_flyby_term.kicad_sch DDR3 fly-by termination (1536 only, 23 resistors) 23 components gen_ddr3_flyby.py
17 17_ddr3_chip.kicad_sch DDR3 U4 complete wiring (96-ball FBGA) 1 IC + lib_symbols gen_ddr3_chip.py
18 18_boot_eeprom_leds.kicad_sch Boot EEPROM, power LEDs, test points (Group A) 16 components gen_boot_eeprom.py
19 19_power_tree_main.kicad_sch TPS75725 main 3.3 V + ADP1706 1.0 V (Group B) 11 components gen_power_tree_main.py
20 20_clock_si5351.kicad_sch Si5351A clock generator + 25 MHz crystal (Group C) 6 components gen_clock_si5351.py
21 21_charger_usbc.kicad_sch BQ25798 charger + USB-C connector (Group D) — gen_charger_usbc.py
25 25_power_filter.kicad_sch Power filtering (ferrites, supercaps, sense resistors) — gen_power_filter.py
26 26_heatsink_mounting.kicad_sch Heatsink mounting and Peltier TEC connector — gen_heatsink_mh.py
Schematic generators gen_retimer_decoupling.py Generates sheet 12: 32 per-retimer decoupling caps (8 per DS80PCI810 × 4)
gen_boot_eeprom.py Generates sheet 18: W25Q128JV boot flash + 24LC256 EEPROM + LEDs + test points
gen_charger_usbc.py, gen_esd.py, gen_telemetry.py, gen_mcu.py, gen_power_filter.py, gen_heatsink_mh.py, gen_qsfp_cage.py Generators for sheets 21–27
Schematic rewriters rewrite_sheet_01.py Regenerates sheet 01 (BGA U16 full pin wiring with 48 HSIO + 64 GPIO)
PCB/placement place_from_csv.py Two-phase KiCad scripting-console placer: 52 absolute anchors + 230 pin-relative entries
Netlist verification join_pinout_vs_netlist.py Cross-checks pinout CSV against KiCad netlist; reports unconnected/mismatched nets
prepare_variant_join_inputs_from_board.py Prepares per-variant join inputs from PCB exports
Wiring and cleanup link_bga_hsio_to_retimers.py Links BGA HSIO pads to DS80PCI810 retimer inputs
Utility / analysis sheet_uuids.py Sheet UUID registry (27 sheets mapped for both 256 and 1536 projects)
The package includes a custom KiCad 10 action plugin ( autophi_floorplan_plugin/ ) with five tabs:
Tab Function
Diagnose Read-only board analysis: signal lengths, overlaps, mounting-hole violations, routing summary
Floorplan Algorithmic placement engine with preview-before-apply; moves footprints and clears tracks
Keepouts PCIe edge connector dual-keepout (above-pads no-vias, below-pads no-tracks/no-vias) + no-via ring around each mounting hole
Net Mappers Standard pinout application: PCIe x16 spec → J5, DDR3 x16 spec → U4/U9/U19/U31, BGA HSIO → retimers, BGA power/IO mapping
About Reference information
Plugin files: __init__.py , plugin.py (action-plugin entry point), floorplan_engine.py (algorithmic placement), keepouts.py (keepout zone generation), net_mappers.py (standard pinout mapping), diagnostics.py (board analysis), place_new.py (new-component placement), _test_standalone.py (standalone test harness).
TIDU796 (TI TIDA-00423) tidu796_design_rules_for_autophi.txt Gen 3 compliance test report for DS80PCI810 — pin-mode strap philosophy, RXDET, VOD/EQ baseline values
PCIe conditioning table pcie_conditioning_ref_table.txt Per-redriver instance lane assignments, strap alignment, BOM cross-check
Netlist + routing plan NETLIST_AND_BOARD_ROUTING_PLAN.txt 6-phase board bring-up plan covering ERC, netlist export, board sync, routing order, pinout verification
Power/AC bypass spec POWER_AC_BYPASS_SPEC.md Definitive spec for power tree additions (B.1–B.9), retimer decoupling (Section C), and PCIe AC coupling (Section D, 128 caps)
Wiring checklist SCHEMATIC_WIRING_CHECKLIST.md Pin-level wiring tables for PCIe x16, DDR3 x64, FPGA assignments
IC-to-FPGA batches 1–4 IC_TO_FPGA_BATCH_{1,2,3,4}.md Exhaustive per-pin wiring tables for all peripheral ICs with BGA GPIO budget tracking
Net label map NET_GLOBAL_LABEL_MAP.tsv 2,368-row mapping of short G_ global labels to canonical net names (SHA-256 based)
KiCad schematics (.kicad_sch) 33 27 hierarchical sheets (256 + 1536 variants) + index schematics + good copies + schematic copies
KiCad PCB layouts (.kicad_pcb) 10 256 and 1536 variant boards, good copies, archive copies
KiCad footprint modules (.kicad_mod) 29 21 custom AutoPhi.pretty footprints + standard-library overrides
Python scripts (.py) 56 Schematic generators, rewriters, PCB placers, netlist verifiers, wiring linkers, floorplan plugin
Data files (.tsv) 43 Pin maps, net label maps, sheet review tables, join reports
Data files (.csv) 14 Placement coordinates (52 anchors + 230 pin-relative), pinout results, parts RAG index
Documentation (.txt) 70 Device footprint descriptions, design rules, routing plans, sheet review tables, join reports
Documentation (.md) 10 Power/AC bypass spec, wiring checklist, IC-to-FPGA batches, ERC notes, session resume notes
Log files (.log) 30 ERC runs, DRC reports, build logs
Project files (.kicad_pro, .kicad_prl) 5 KiCad 10 project settings for 256 and 1536 variants
Backups (.zip, .bak*) 40 Incremental backups, pre-reset PCB archives, variant removal backups
This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
Photo
Footnotes
- Product number 8487.
- Family: autophi pcie cards.
- Purchase: When you buy, you buy the use of that blueprint only.