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30-autophi-on-demand-three

$2,357,730,000.00

In stock

SKU

2059

AutoPhi On-Demand Three: the V20 Epiphany chip grows tier by tier on its PCIe card, from Seed to Epiphany, animated picture

Asset valuation: $2,400,000,000. Master index of all projects: PROJECTSINDEX. Last edited: 2026-05-02 Status: Largest aggregation in the catalog — 68,000+ files of EDA, RTL, reports, and source projects Maturity (per PACKAGEARCHITECTURE.md): L4 (Tape-out / Mass-Manufacturable) — full physical-desig

For the curious

Imagine ordering a chip the way you order a part from a catalog: name the envelope and the process node, and back comes a buildable design with its calculation rate and its performance per cost, per watt and per area already worked out. That is the on-demand idea, and V20 Epiphany is its third generation.

The chip at the centre does everything itself: no companion ICs, no external controllers, no third-party silicon. A 36 mm by 36 mm die stacked 12 mm tall, 50 to 550 layers by tier, on an AES two-element alloy substrate at a 1.5 nm node, clocked from 4 to 16 GHz by Light Trigger, on a full-height, full-length PCIe 5.0 x16 card. The card has a 300 W budget and a net draw of 38.6 W once nine integrated technologies do their work: LED power recycling, vertical threading, chiplet stacking, nanophotonic data flow, quantum error correction, electromagnetic cooling with no moving parts, quantum battery layers, a quantum-classical hybrid interface and a neuromorphic engine. Instructions travel as light, with wavelength as the opcode.

This is the largest aggregation in the AutoPhi catalog: 68,612 files across six sub-projects, from the original architecture through a 1,000-part on-demand catalog to the V20 design itself, with 9,979 Verilog RTL files, 1,003 GDSII layouts and the synthesis, placement and timing output of a real physical-design flow, not just documentation. It is for a datacenter operator or an engineering buyer who wants the whole AutoPhi production pipeline as it stands, patent pending, with the filings in the inventor's name.

Details

Description

AutoPhi On-Demand Three — V20 Epiphany (SKU 2059)

Patent Status: Patent Pending. USPTO application numbers 18/370,908 (AutoPhi: Quantum battery integration & electromagnetic propulsion IC), 19/540,453 (Integrated Technology Portfolio — umbrella), 19/177,547 , 19/445,644 , 19/449,352 , and 19/555,525 (referenced in deposition subtree). Additional patent references: 29/839,062 (Light Trigger), 3561 2876 (Cold Light Micro Chip with digital optics & varied colored laser semiconductor), 1026 (Battery with electrical generator and recycle / LED Recycle), 1096 (Electromagnetic Cooling — Method), 1097 (Electromagnetic Cooling — Apparatus), 1098 (Electromagnetic Cooling — System). All filings by inventor Christopher Gabriel Brown . Filed — Pending Review; approval probability 70–90%. See canonical PATENT_PORTFOLIO.md and N417_FILING_RECEIPTS.md for the full portfolio.

Overview

The third-generation AutoPhi On-Demand package, code-named V20 Epiphany , is the largest aggregation in the AutoPhi catalog: 68,612 files spanning RTL, EDA flow output, physical layout, documentation, data, images, source code, and chemistry/bio deliverables. Maturity level is L4 — Tape-out / Mass-Manufacturable , representing a real production-scale ASIC physical-design output, not merely a documentation set.

V20 Epiphany bundles six sub-projects into a single deliverable pipeline — from original architecture through a 1,000-part on-demand catalog through the latest V20 Epiphany design iteration. A buyer who acquires this bundle gets the entire AutoPhi production pipeline as it stands .

The “on-demand” concept: the AutoPhi family produces buildable chip variants on demand from the seed-matrix calculator . You supply envelope and node; you get calculation (FLOPS) and performance per exchange (per dollar, per watt, per area). The product is the ratio of instruction set (from size) to calculation and performance per exchange.

Package Contents — Six Sub-Projects

Sub-Project Role Files

18-autophi-future/ AutoPhi Future architecture — concept, seed voxel flow, Blu-ray foundry build, pitch materials, RAG sources 127

23-zetta-flops/ Zetta-Flops bundle — RTL, synthesis, testbenches, OpenLANE configs, GDSII, foundry handoff, nine technologies 68

24-parts-future/ Parts Future — 1,000-configuration voxel catalog with 183 full part folders (datasheets, foundry handoff, spec.json, sales briefs) 954

26-autophi-on-demand-two/ Predecessor On-Demand Two — second-generation on-demand content 23

27-mathmatical-depositions/ Mathematical Depositions record — 10 mathematical depositions + 18 product depositions, PDFs, SVGs, PNGs 141

30-v20-epiphany/ V20 Epiphany — third-gen 12 mm chip on PCIe card, 1,000 SKU part folders, AES substrate, board integration 5,023

Additionally: sales-pitches/ (23 files including 10 Proof-of-Function documents in HTML and PDF), plus root-level LICENSE, MANIFEST.json, CITATION.cff, CHANGELOG.md, CONTACT_INFO.txt, PRIOR_ART_LED_RECYCLING.md, README.md, and PLAYBOOK.md.

File-Type Breakdown (All 68,612 Files)

Extension Count Category

.json 14,815 Generated configurations / manifests

.md 13,095 Documentation (Markdown)

.v 9,979 Verilog RTL

.txt 8,923 Text files

.rpt 7,072 EDA reports

.tcl 2,219 Synthesis / PnR flow scripts

.log 2,016 Flow execution records

.def 1,545 Physical placement (DEF)

.sdc 1,497 Timing constraints

.lef 1,032 Library Exchange Format

.png 1,032 Images

.svg 1,011 Vector graphics

.gds 1,003 GDSII layout

.sdf 432 Standard Delay Format

V20 Epiphany — Physical Architecture

V20 Epiphany is designed around one principle: a single chip does everything . No companion ICs, no external controllers, no third-party silicon. The 12 mm tall package integrates all compute, power management, thermal control, memory interface, and I/O onto a single AES substrate die stack.

Parameter Specification

Die Size 36 mm × 36 mm (1,296 mm² per layer)

Chip Height 12 mm

Layer Count 50–550 (tier-dependent, incremental)

Layer Pitch 18–200 µm (tier-dependent)

Process Node 1.5 nm (TSMC A16 / Intel 18A compatible)

Clock Range 4–16 GHz (Light Trigger technology)

Substrate AES (two-element alloy)

PCIe Interface PCIe 5.0 ×16 (512 GT/s)

Card Form Factor Full-Height Full-Length: 268 mm × 111 mm × 70 mm

Total Power Budget 300 W (75 W slot + 225 W auxiliary)

Net Power (after all optimisations) 38.6 W

BGA Ball Pitch 0.4 mm

BGA Ball Count ~8,100 (90 × 90 array)

Wafer Size 300 mm standard

Companion ICs Required Zero — all custom, all on-die

AES Substrate Properties

Property AES Silicon Advantage

Bandgap 0.8 eV (Direct) 1.12 eV (Indirect) Direct bandgap enables photonic integration

Electron Mobility 12,000 cm²/V·s 1,500 cm²/V·s 8× Silicon

Hole Mobility 8,000 cm²/V·s 450 cm²/V·s 17.8× Silicon

Thermal Conductivity 400 W/m·K 150 W/m·K 2.7× Silicon

Cost $5.00/kg $1.50/kg Competitive

Vertical heat flow: 400 W/m·K × (36 mm × 36 mm) / 12 mm = 51,840 W/K thermal conductance. Even at 200 kW compute load: only 3.86 °C temperature rise across the full stack.

Nine Integrated Technologies

# Technology Key Specification Patent(s)

1 LED Power Recycling 90% capture efficiency; 42% net power reduction; 16-bit photon level sensing 1026

2 Vertical Threading 12,000+ TSVs/mm²; 125 TB/s inter-layer bandwidth; 18 data layers × 64-bit —

3 Chiplet Stacking 50–550 active layers in 12 mm height; 18 chiplets per stack; up to 28 stacks —

4 Nanophotonic Data Flow 1,400 TB/s total; 2,800 optical channels × 256-bit × 0.5 TB/s each; WDM control —

5 Quantum Error Correction 99.998% accuracy; 1,400 logical qubits; 1 MHz error correction cycle; 32-bit per qubit —

6 Electromagnetic Cooling 97% efficiency; 32 independent thermal zones; zero moving parts; near-zero power 1096, 1097, 1098

7 Quantum Battery Layers 20 battery layers; 1,500 Wh capacity; 75 MW burst power —

8 Quantum-Classical Hybrid Single-cycle handoff latency; 64-bit quantum + 64-bit classical data width —

9 Neuromorphic AI Engine Spiking neurons on-die; event-driven; near-zero idle power; 32-bit spike interface —

Three-Chromosome DNA Architecture

Chromosome Width Description

Electron 512 bits Classical instruction encoding

Atomic 64 quantum gate types Quantum gate instruction set

Photon 18 opcodes Optical computation operations (Color Mathematics)

Photon Opcode Table (18 Opcodes)

Colour Opcode Function

Red 0x01 ADD

Blue 0x02 SUB

Green 0x03 MUL

Yellow 0x04 DIV

Cyan 0x05 LOAD

Magenta 0x06 STORE

White 0x07 BRANCH

UV 0x08 QGATE

IR 0x09 SYNC

Orange 0x0A MEASURE

Violet 0x0B ENTANGLE

Lime 0x0C NEURON

Teal 0x0D DMA

Pink 0x0E SECURITY

Gold 0x0F SANITARY

Silver 0x10 CTRL

Amber 0x11 FUSE

Indigo 0x12 PHOTON_PIPE

Photon Chromosome Encoding: wavelength (λ) = opcode; polarisation (pol) = operand/phase; path = address; intensity (I) = magnitude. DNA-style compact, replicable three-strand chromosomes.

FLOPS Performance — 10 Tiers, 1,000 SKUs

FLOPS formula: Base_Threads × Clock × Ops_Per_Cycle × 2 (Light Trigger) × Mirror_Efficiency × Vertical_Threading × 2 (GREEN MUL) × 2.5 (AES substrate)

Tier Name Layers Config IDs SKU Range Earned FLOPS

1 Seed 50–95 0001–0100 APV20-EPH-0001 to 0100 300 EFLOPS – 1.08 ZFLOPS

2 Sprout 100–145 0101–0200 APV20-EPH-0101 to 0200 1.15 – 2.08 ZFLOPS

3 Sapling 150–195 0201–0300 APV20-EPH-0201 to 0300 2.17 – 3.50 ZFLOPS

4 Branch 200–245 0301–0400 APV20-EPH-0301 to 0400 3.67 – 5.48 ZFLOPS

5 Canopy 250–295 0401–0500 APV20-EPH-0401 to 0500 5.72 – 8.15 ZFLOPS

6 Crown 300–345 0501–0600 APV20-EPH-0501 to 0600 8.48 – 11.72 ZFLOPS

7 Summit 350–395 0601–0700 APV20-EPH-0601 to 0700 12.16 – 16.39 ZFLOPS

8 Zenith 400–445 0701–0800 APV20-EPH-0701 to 0800 16.94 – 22.45 ZFLOPS

9 Apex 450–495 0801–0900 APV20-EPH-0801 to 0900 23.16 – 30.16 ZFLOPS

10 Epiphany 500–550 0901–1000 APV20-EPH-0901 to 1000 31.07 – 40.38 ZFLOPS

Lowest baseline: Tier 1 Seed #0001 (50 layers, 4 GHz) = 877 PFLOPS . Highest baseline: Tier 10 Epiphany #1000 (550 layers, 16 GHz) = ~3.2 ZFLOPS standalone. With REV-5 Accelerator: ~6.7 ZFLOPS .

System FLOPS vs NVIDIA H100

V20 Seed #0001 (minimum) 877 PFLOPS 877×

V20 Seed #0001 (16 GHz GREEN) ~120 EFLOPS 120,000×

V20 Epiphany #1000 (maximum) ~3.2 ZFLOPS 3,200,000×

V20 + REV-5 Accelerator ~6.7 ZFLOPS 6,700,000×

Board Integration — PCIe Card Height Budget

Component Height (mm)

PCIe connector + edge contact 8.0

PCB substrate 1.6

BGA / package interposer 1.5

V20 Epiphany chip 12.0

Thermal interface material 0.5

EM Cooling structure 15.0

Clearance / bracket 31.4

Total 70.0 (fits within standard PCIe envelope)

The 12 mm chip uses only 17.1% of the 70 mm height budget. Power margin: 38.6 W net vs 300 W PCIe budget = 261.4 W available . Compatible with any standard ATX/EATX motherboard with a PCIe 5.0 ×16 slot. Up to 4 cards in standard EATX configuration.

Chip Series Tiers — COGS Arc

Tier Name COGS Band CPU GPU DPU All-in-One Use Case

1 Entry Low Primary — — No Edge, client, proof

2 Mid Low–Mid Yes Small — No Edge, client

3 Pro Mid Yes Full Optional No Workstation, server

4 Peak Expensive Yes Max Full No Datacenter

5 Unified Mid Yes Yes Yes Yes Complete unit (single die CPU+GPU+DPU)

6 Volume Low Yes Yes Yes Yes Volume production; COGS back down

AES COGS Paths: $20K AES COGS — 1B volume, 3 nm, 240 dies (5–10 year path). $5K AES COGS — 10B volume, 1 nm, 12 dies (10–15 year path).

Seed Matrix — Formulas in the Open

The seed matrix turns envelope and node into a seed. Formulas:

Formula Description

S = H × W Total die area (mm²)

N v = S / a v Voxel count (area / area per voxel)

C = N v × f v Total calculation (FLOPS)

ρ = C / S FLOPS per mm² density

P per_dollar = C / AES Performance per dollar

P per_watt = C / power_w Performance per watt

Inputs: scenario_id, node_nm, H_mm, W_mm, a_v_mm2, f_v_flops, power_w, aes_usd. Outputs: S_mm2, N_v, C_flops, rho_flops_per_mm2, P_per_dollar, P_per_watt. Template CSV and example JSON ship with the seed. Any size. Truncated OK.

Example scenario (130 nm): H=20 mm, W=20 mm, a_v=0.31 mm², f_v=1×10&sup9; FLOPS → S=400 mm², N_v=1,290, C=1.29×10¹² FLOPS, ρ=3.225×10&sup9; FLOPS/mm², P_per_dollar=6.45×10&sup7;, P_per_watt=3.225×10&sup9;.

The Metal Tree and the Seed

The chip is structured as a metal tree (not metaphor — structure): roots that intake (light, power, anchor); trunk and vascular system that send (data, control, quantum state, power along waveguides and wires); parts that turn light energy emission into electricity; parts that cool and support.

Voxel types: INTERCONNECT, LIGHT, BLANK, HYBRID, QUANTUM, IO, MEMORY, CROSS, ENERGY, COOL_SUPPORT. Tree roles: SEND, ENERGY, COOL_SUPPORT.

The seed is the minimal canonical specification: chip series (tiers + COGS bands), voxel roles and tree mapping, photon chromosome encoding, nine technology elements, and performance/COGS summary. One definition, many harvests. Reproducibility: same seed, same inputs, same result. Version the seed; version the chips.

Foundry Packages — Five Major Foundries

Package Foundry Nodes Status

package_tsmc TSMC 7 nm, 5 nm, 3 nm Awaiting NDA/PDK

package_samsung Samsung Foundry 14LPE, 7LPP, 5LPE Awaiting NDA/PDK

package_intel Intel Foundry (IFS) 14 nm, Intel 3, 20A/18A Awaiting NDA/PDK

package_skywater SkyWater 130 nm (open PDK) Ready for OpenLANE

package_gf GlobalFoundries 180 nm open, 12LP, 22FDX Awaiting PDK

Each package follows FOUNDRY_STANDARDS.md: GDSII, LEF, DEF, netlist, DRC/LVS reports, FOUNDRY_HANDOFF_SIMPLE.txt, and AUTHOR_CONTACT_INFO.txt.

Executable Seed Voxel — OpenLANE2 Flow

Parameter Value

RTL Module autophi_voxel_blank (from Project 27)

Pin Count 655 pins

Die Area (130 nm) 560 × 560 µm

Clock Port clk

Clock Period 10 ns

Placement Density 45%

PDK SkyWater 130 nm (sky130) via volare

Output GDSII + LEF in seeds/

Growth Path Same RTL → 5 nm / 3 nm when foundry PDK obtained

Build tool options: Nix ( OPENLANE_USE_NIX=1 ), Docker ( OPENLANE_USE_DOCKER=1 ), or venv. Nix patch ( openlane2-disable-doCheck.patch ) provided for flake build. Completed OpenLANE2 runs dated 2026-02-07 are included (runs RUN_2026-02-07_22-31-18 and RUN_2026-02-07_23-32-54 ).

Zetta-Flops Accelerator (23-zetta-flops)

RTL Module Description

autophi_light_cpu_core.v Light CPU core (colour-coded operations)

autophi_quantum_cpu_core.v Quantum CPU core (16-instruction creative set)

autophi_hybrid_cpu_top.v Hybrid CPU top-level (Light + Quantum unified)

autophi_accelerator_interface_adapter.v Accelerator interface adapter

autophi_scale_accelerator_integration.v Scale accelerator integration

ZETTAFLOP_1Z_ACCELERATOR_top.v 1Z Accelerator top-level

Includes 6 testbenches, 4 Yosys synthesis scripts ( synth_all.ys , synth_hybrid_cpu.ys , synth_light_cpu.ys , synth_quantum_cpu.ys , ZETTAFLOP_1Z_ACCELERATOR_synth.ys ), OpenLANE configs for 130 nm / 14 nm / 7 nm ( config.json , config.tcl , config_14nm.tcl , config_7nm.tcl ), GDSII layout, test vectors, package design specification, and manufacturing flow documentation.

25 GB Blu-ray Foundry Build System

The Python build script ( build_bluray_foundry.py , 304 lines) assembles 25 GB Blu-ray-ready packages. Build types: tsmc , samsung , intel , skywater , gf , all-foundries , 24-full , or future-only (Performance + COGS docs only when source unavailable). Every build includes:

Foundry handoff packages with FOUNDRY_HANDOFF_SIMPLE.txt
Performance_And_COGS/ folder (PERFORMANCE_AND_COGS_SUMMARY.md, CHIP_SERIES_CPU_GPU_DPU.md, CODE_NAME_ACTUAL_BRONZE.md)
Seeds/ folder (GDSII/LEF when present)
MANIFEST.txt with SHA-256 checksums (optional --sha256 )
DISC_README.txt

Multiple verified Blu-ray build outputs are included: BluRay_all-foundries_20260207 (26 files, 45,964 bytes), BluRay_all-foundries_20260227 (26 files), BluRay_future-only_20260227 (7 files, 12,947 bytes), BluRay_future-only_20260314 and variants.

Mathematical Depositions (27-mathmatical-depositions)

Ten original mathematical depositions with formulas rendered as SVG, PNG, and PDF:

Harmonic Decay
Entropic Bridge
Voxel Resonance
Photon Chromosome Encoding
Recursive Growth Bound
Zero-Point Fabrication
Golden Spiral Convergence
Quantum Counting Paradox
Thermal Noise Floor
Dimensional Fold

Plus 18 product depositions (Autocar, Vitamins, Jet, War Satellite, Quantum Battery, Superdome, Pagers, Nuclear Recycling, Smart Shoe, Semiconductor, Landfill Truck, Chemical Cooker, Small Nuclear, Communications Satellite, NewStar, Brain Chemistry, Landfill Center, AutoPhi Combined). Complete backup available as PDF and ODT/ODF documents (CGB_Mathematical_Depositions_Complete_2026.pdf).

Parts Catalog (24-parts-future + 30-v20-epiphany)

24-parts-future: 183 full part folders following the APV18 naming convention (e.g., APV18-ENT-0201-65NM , APV18-MIC-0053-130NM , APV18-AQC-0921-1.5NM ). Each folder contains: DATASHEET.md, FOUNDRY_HANDOFF.md, README.md, SALES_BRIEF.md, and spec.json. Includes 1,000-configuration CSV ( 1000_voxel_configurations.csv ), catalog generators ( generate_1000_configs.py , generate_sales_catalog.py , generate_magento_catalog.py , generate_ai_easy_catalog.py ), product images for all tiers (Seed, Entry, Mid, Pro, Peak, Unified, Volume, AQCHS, Mini, Micro series), and a product finder (HTML).

30-v20-epiphany: 1,000 SKU folders following the APV20-EPH naming convention (APV20-EPH-0001-1.5NM through APV20-EPH-1000-1.5NM). Each folder contains: DATASHEET.md, FOUNDRY_HANDOFF.md, README.md, and spec.json. SKU generator scripts: generate_all_skus.js and sku_config.py .

Scripts and Build Tools

Script Language Purpose

build_bluray_foundry.py Python 25 GB Blu-ray package builder (3 copies across sub-projects)

build_bluray_foundry.bat Batch Windows wrapper for Blu-ray build

build_to_24_bluray_test.bat Batch Build to 24_bluray_test output folder

run_seed_openlane_wsl.sh Bash OpenLANE2 seed voxel build in WSL (2 copies)

apply_openlane2_nix_patch.sh Bash Apply Nix doCheck disable patch for OpenLANE2 flake

generate_7t_seed_wordpress_import.py Python Generate 50 WordPress articles (WXR) for the 7T seed

build-autophi-future-wxr.py Python Build AutoPhi Future WordPress export (WXR)

generate_all_skus.js JavaScript Generate all 1,000 V20 Epiphany SKU folders

sku_config.py Python SKU configuration for V20 Epiphany

build_1000_parts.py Python Generate 1,000 V18 parts with datasheets and handoffs

Pitch Materials and Sales Documentation

17 HTML pitch pages across the bundle:

pitch/index.html — Sales pitch: one seed, every foundry, metal tree, tiers, AES, Blu-ray
pitch/deep-dive.html — Deep dive: metal tree, seed, photon chromosome, chip series, executable seeds
pitch/deep-dive-exhaustive.html — Full exhaustive reveal (22 sections)
pitch/deep-view-7t.html — Deep view for 7T ask
pitch/deposition.html — Full deposition (HTML)
pitch/sales-pitch-complete.html — Complete one-page pitch
pitch/sales-description.html / sales-description-embed.html — Store-ready sales descriptions
pitch/miracle-calculation.html — The miracle we call calculation
pitch/valuation.html — Indicative valuation
pitch/essay-19-into-18.html — The unrational change: 19 into 18
pitch/logical-sales-pitch.html — Logical sales pitch (exhaustive)
WordPress import files: 3 WXR files for automated article import
10 Proof-of-Function documents (HTML + PDF) in sales-pitches/

Prior Art Disclosure

PRIOR_ART_LED_RECYCLING.md provides full transparency on third-party patents overlapping the LED Power Recycling element, including US 4,775,876 (1988), US 2012/0305059 A1, US 2002/0170591 A1, and US 2007/0085100 A1. The defensible novelty is the nine-element integrated processor , not LED recycle in isolation.

Relation to the AutoPhi Stack

Project Role

02 (AutoPhi Modern) Product consolidation; 18 is the future vision that informs voxel and path evolution

24 (Scale) Foundry packages; 18’s build script sources 24 for Blu-ray content

27 (Scale Ultimate) Voxel die building, hybrid/light/quantum cores. Seed RTL ( autophi_voxel_blank ) originates from 27

28 (Complete Unit) Single-chip, CPU–accelerator symmetry. 18’s whole-quantum and path options inform 28

What Is in the Package

68,612 files total across all sub-projects
9,979 Verilog RTL files — complete HDL source for Light CPU, Quantum CPU, Hybrid CPU, accelerator integration, voxel blank, and ZETTAFLOP_1Z_ACCELERATOR
1,003 GDSII layout files — physical design output including seed voxel and accelerator layouts
1,032 LEF files — Library Exchange Format for foundry handoff
1,545 DEF files — placement and routing data
7,072 EDA reports — synthesis, timing, DRC, LVS reports
2,219 TCL scripts — synthesis and place-and-route flow automation
432 SDF files — Standard Delay Format timing data
1,497 SDC files — timing constraints
2,016 log files — complete flow execution records
14,815 JSON manifests — generated configurations and spec files
13,095 Markdown documents — exhaustive documentation
1,183 part folders (183 APV18 + 1,000 APV20-EPH), each with datasheet, foundry handoff, spec.json, and README
5 foundry-specific packages (TSMC, Samsung, Intel, SkyWater, GlobalFoundries) with handoff structure
Multiple Blu-ray build outputs (verified, with manifests)
10 mathematical depositions with SVG, PNG, and PDF renderings
18 product depositions with HTML and PDF
Seed matrix : SEED.yaml, seed_matrix_template.csv, seed_matrix_example.json, chip_series_cpu_gpu_dpu.yaml
OpenLANE2 seed design : autophi_voxel_blank.v, config.json, completed run artifacts
Build scripts : Blu-ray builder (Python), seed builder (Bash), SKU generators (Python/JS), WordPress importers (Python)
RAG sources : 96-333-fixed.csv (deposition catalog), Yesterday.txt (portfolio), 1 light trigger.txt, 18-docs/
17 HTML pitch pages + 10 Proof-of-Function documents (HTML + PDF)
3 WordPress import files (WXR format)
Product images : 1,032 PNGs + 1,011 SVGs (tier renders, chip images, formula graphics)
LICENSE , MANIFEST.json , CITATION.cff , CHANGELOG.md , CONTACT_INFO.txt

How this is delivered

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

Photo

Render of a PCIe card captioned 'AutoPhi V18 AQCHS Series', 'Quantum-Classical Super' (printed '$2.8T' price removed 2026-10-08)

Footnotes

Product number 8478.
Family: autophi on demand.
Purchase: When you buy, you buy the use of that blueprint only.

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