28-new-path-heights
Asset valuation: $800,000,000. Master index of all projects: PROJECTSINDEX. Last edited: 2026-05-02 Status: Bundle of two semiconductor-discovery projects Maturity (per PACKAGEARCHITECTURE.md): L1 (Research) — pairs the material-discovery project with the method-discovery follow-on
Imagine screening two thousand semiconductor compounds the way a jeweller sorts stones - scoring each on how it conducts, how it grows, how rare the pairing is and what the market wants - and finding at the top of the pile a copper-tin alloy, eighty-eight parts copper to twelve parts tin, far cheaper per kilogram than gallium arsenide or gallium nitride. That is Project 14, Semiconductor Material Discovery. Every candidate in the Alchemy Data V2 database is scored on a hundred-point scale, and the alloy the inventor calls AES came out perfect: a direct 0.8 eV bandgap, electron mobility eight times silicon, hole mobility nearly eighteen times silicon, thermal conductivity close to three times silicon, grown as a single-crystal boule by the Czochralski method and sliced into 300 mm wafers, about seven hundred per boule. The scoring system is patent pending under USPTO application 19/449,352, fifty claims, filed January 14, 2026.
Project 15, Semiconductor Method Discovery, is the follow-on: the complete fabrication method for a chip built on that substrate - ten millimetres tall, thirty-two layers, eight trillion transistors, rated at one hundred yottaflops. Together they trace the path from a new material to a manufacturable integrated circuit.
This is research-grade work for engineering buyers and licensees who want a substrate story that does not start with silicon. The buyer walks away with the two-thousand-compound database in CSV and JSON with its RAG assembly, the ranked top twenty with head-to-head comparisons, the AES specification and wafer-preparation sequence, and the thirty-two-layer method. The patent-pending scoring system stays the inventor's.
Description
New Path Heights — Semiconductor Material and Method Discovery
New Path Heights is a bundled semiconductor-discovery research package pairing two sub-projects from inventor Christopher Gabriel Brown (CRI-ONE). Project 14 — Semiconductor Material Discovery identifies and ranks optimal semiconductor compounds using a patent-pending scoring system (USPTO application 19/449,352, 50 claims, filed January 14, 2026). Project 15 — Semiconductor Method Discovery provides the complete fabrication method for a 10 mm-tall, 32-layer, 8-trillion-transistor, 100 YFLOPS integrated circuit built on the top-ranked substrate. Together they trace the full path from novel material identification through manufacturable IC design.
The material-discovery work screened 2,000 semiconductor compound candidates through the Alchemy Data V2 system and identified AES (Copper-Tin alloy, Cu-Sn) as the highest-scoring material, achieving a perfect 100.0 / 100 semiconductor score. AES is defined as follows:
AES wafer preparation follows a seven-step sequence: (1) Czochralski ingot growth from a controlled 88:12 Cu:Sn melt at 960 °C, pulling at 1–2 mm/hour with a [100]-oriented seed crystal to produce a 310 mm-diameter × 600 mm boule; (2) X-ray diffraction verification of single-crystal alpha-phase uniformity; (3) diamond wire saw slicing into 300 mm, 775 μm-thick wafers (~700 wafers per boule); (4) double-sided lapping to 5 μm TTV; (5) CMP with Cu-Sn-specific colloidal silica slurry to 0.1 particles/cm² at ≥90 nm or crystal defects >1 μm.
The Scoring Algorithm
Every compound in the 2,000-entry database is evaluated on a 0–100 point scale, composed of four weighted categories:
1. Electrical Properties 0–40 points
Bandgap analysis (0–10): optimal for target application scores 8–10.
Electron mobility (0–10): >10,000 cm²/V·s scores 10; 5,000–10,000 scores 8–9; 1,000–5,000 scores 5–7; 5,000 scores 10; 2,000–5,000 scores 8–9; 500–2,000 scores 5–7;
2. Manufacturing Feasibility 0–30 points
Synthesis methods available (0–10): multiple proven methods scores 8–10.
Crystal quality achievable (0–10): high-quality single crystals scores 8–10.
Scalability (0–10): excellent scalability scores 8–10.
3. Novelty & Patent Potential 0–20 points
Element combination rarity (0–10): very rare combination scores 8–10.
Novel properties (0–10): unexpected novel properties scores 8–10.
4. Application Potential 0–10 points
Market need (0–5): high market demand scores 4–5.
Performance advantage (0–3): significant advantage scores 3.
Cost advantage (0–2): significant cost advantage scores 2.
Outcome Per Element is calculated separately by aggregating performance points — electron mobility contribution (0–30), thermal conductivity contribution (0–20), breakdown voltage contribution (0–20), technology maturity contribution (0–15), scalability contribution (0–15) — for a total outcome score of 0–100, then dividing by the number of elements in the compound. Materials are ranked by semiconductor score (primary) and outcome per element (secondary).
Rank Compound Cost/kg Cost/Elem Cost Cat. Score Outcome/Elem Primary Functions
The full 2,000-compound database is available in both CSV and JSON formats with a RAG (Retrieval-Augmented Generation) assembly providing structured metadata, searchable text representations, semantic tags, and fast lookup indices (by name, element, cost category, function, score range, and tag). The RAG assembly supports exact match queries, range queries, semantic queries, and natural language queries, and is formatted for vector database integration.
Database cost distribution: Medium-High: 557 compounds; High: 395; Low: 357; Very High: 271; Medium: 233; Very Low: 187.
The material-discovery methodology, scoring algorithm, and RAG assembly system are covered by a non-provisional utility patent application filed with the United States Patent and Trademark Office.
Title of invention Comprehensive System and Method for Discovering, Scoring, and Indexing Optimal Semiconductor Materials
Documents filed 5 (Application Data Sheet, Claims Document, Fee Worksheet, Oath/Declaration, Micro Entity Certification — 62 pages total)
Key claim areas across the 50 claims: (1) Material discovery module generating a database of semiconductor compounds with cost, function, and electrical-property analysis; (2) Scoring module calculating a 0–100 semiconductor score with four weighted categories plus outcome-per-element calculation and material ranking; (3) RAG assembly module creating structured metadata, searchable text, semantic tags, fast lookup indices, and vector database formatting; (4) Integrated system combining all three components; (5) Method claims covering the step-by-step discovery, scoring, and indexing process; (6) Computer-readable medium storing instructions to perform the method; (7) Output in JSON, CSV, and RAG-ready formats for AI integration.
Project 15 — Semiconductor Method Discovery
Project 15 provides manufacturing instructions and specifications for a 10 mm-tall, 32-layer, 8-trillion-transistor, 100 YFLOPS integrated circuit using AES as the primary semiconductor substrate, integrating the AutoPhi V19-Pinnacle architecture. The final deliverable is a PCIe Half-Height Half-Length (HHHL) card — 167.65 mm × 68.90 mm — that plugs into any standard server or workstation.
The complete fabrication method is classified as a trade secret. The buyer receives the full, unredacted manufacturing instructions upon licensing. The description below outlines the scope of what is included without revealing the proprietary process details.
The method documents cover the entire path from raw AES ingot to finished PCIe card:
- 32-layer vertical IC architecture — a complete layer-by-layer blueprint specifying the function, thickness, materials, and integration constraints for every layer in the 10 mm stack. The design integrates classical compute, GPU arrays, neuromorphic engines, tensor cores, quantum processing, photonic interconnect, DNA molecular logic, power delivery, electromagnetic cooling, LED power recycling, quantum battery, and security/DPU layers into a single vertical package.
- Materials specification — every substrate, metal, dielectric, barrier, process gas, wet chemical, and packaging material identified by name, grade, and sourcing category. Covers the primary AES substrate plus secondary substrates, quantum-layer superconducting materials, photonic waveguide materials, 12-layer metal stack, and all specialty-layer materials.
- Step-by-step fabrication process — eight phases spanning approximately 46 weeks per lot, from AES wafer fabrication through FEOL transistor formation, BEOL interconnect wiring, specialty layer fabrication (quantum, photonic, neuromorphic, LED, EM cooling, DNA, battery), wafer thinning, 3D stacking and assembly, and final test and validation.
- Equipment and tooling catalog — 120 to 160 capital tools across 10 categories (crystal growth, lithography, deposition, etch, CMP, implant/anneal, metrology, 3D stacking/packaging, test, and specialty quantum/photonic/battery lines), with specific equipment names and specifications for each.
- Facility requirements — clean-room classifications (ISO 3 through ISO 7), minimum floor areas per zone, utility specifications (UPW, process gases, vacuum, power, HVAC, vibration), and layout guidelines.
- 25 quality gates — a gate-by-gate quality-control framework (G1 through G25) covering every critical process step from STI etch through final AI throughput verification, with measurement methods and pass/fail criteria at each gate.
- Manufacturing roadmap — a six-phase scaling timeline from material validation through volume production (10,000+ packages/month), with milestones, COGS trajectory, risk register, and key dependencies.
- Yield targets — per-layer and compound-stack yield models with scaling projections.
- TSV integration specifications — four via types (power, signal, thermal, optical) with density, dimensions, and purpose, totalling 12,000 TSVs/mm².
- Project 14 — Semiconductor Material Discovery:
- Top thesis document (BRONZE_TOP_THESIS.md) with full AES material analysis
- 2,000-compound database (CSV and JSON)
- Complete compound summary with all scores, costs, and functions
- RAG assembly (index creation, query interface, query examples, JSON interface file)
- Discovery scripts (run_semiconductor_discovery.py, generate_top2000_compounds.py)
- Test suite (test_semiconductor.py)
- Patent receipts (USPTO application 19/449,352 — application.docx, ADS, fee worksheet, oath/declaration, micro entity certification, plus all 5 patent drawing SVGs)
- Patentability analysis, filing guide, filing record, patent summary, valuation
- IP notice, disclosure policy, tiered disclosure strategy
- Sales pitch, web description, representative image files
- Project 15 — Semiconductor Method Discovery (trade secret):
- Complete fabrication method for the 32-layer, 10 mm, 8T-transistor, 100 YFLOPS IC on AES substrate
- Six proprietary documents covering materials, layer architecture, fabrication process, equipment and tooling, quality control (25 gates), and manufacturing roadmap
- Encrypted archive (AES-256) — decryption key delivered separately upon licensing transaction
- Trade secret notice, royalty pattern, and proposal letters
- Bundle-level files: README, MANIFEST.json (62 files, 34 documentation, 7 web, 6 documents, 5 source, 5 images, 2 data, 2 other, 1 archive), LICENSE, CHANGELOG, CITATION.cff, CONTACT_INFO.txt, PLAYBOOK, 10 proof-of-function documents (HTML + PDF)
- Encrypted archive: 15-semiconductor-method-discovery.tar.gz.enc (AES-256 encrypted; key held by inventor, delivered upon licensing transaction)
Total files: 62. Categories: .md (34), .html (7), .py (5), .svg (5), .pdf (4), .docx (2), .gz (1), .enc (1), .csv (1), .json (1), LICENSE (1).
IP and Terms
Patent posture: USPTO application 19/449,352 (50 claims, filed January 14, 2026) covers the semiconductor material discovery, scoring, and RAG assembly system. The method-discovery work (Project 15) may be the subject of a future filing or extension. All intellectual property rights remain with Christopher Gabriel Brown / CRI-ONE. No IP transfer is implied by any purchase tier. Commercial use requires a separate licensing agreement.
Inventor: Christopher Gabriel Brown, Lawrenceville, Georgia. Contact: christopher@cri-one.com.
Project maturity: L1 (Research).
How this is delivered
This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
Photo
Footnotes
- Product number 8476.
- Family: materials discovery.
- Purchase: When you buy, you buy the use of that blueprint only.