101-c-service — PhantasmPhi PHC10 master @ 1.5 nm · GDSII + C
The PhantasmPhi PHC10 master @ 1.5 nm, taken from RTL to a 270-byte GDSII v6 outline (die + power ring, verified) and to a reference C99 ISA simulator that runs the chip's own self-test. The self-test prints PHANTOMCORE: ALL CHECKS PASS — the same line Icarus Verilog prints — in 112 simulated cycles, 12 of 12. Built with gcc at -Wall -Wextra -Wpedantic, zero warnings. Honest scope on the product image and in the README: no silicon, GDSII is an outline shell (not a routed layout), SKY130 is the only mapped node, KELLY is the only phantasm deposition implemented.
Think of a chip the way you'd think of a letter you haven't posted yet: the words are chosen, the envelope is addressed, the stamp is in the drawer. Nothing is in the mail. That's where this package meets you.
The outline of the chip — exactly where the die ends and where the power ring sits, down to the single micron — is in a 270-byte file that any foundry tool will open. Beside it is the mind of the chip in plain C: a small program that pretends to be the silicon and runs the chip's own test as if it were powered up. It prints the same line the real test prints: PHANTOMCORE: ALL CHECKS PASS. Twelve of twelve. One hundred and twelve simulated heartbeats.
There is a will here, and this is where the way begins.
The PhantasmPhi PHC10 master @ 1.5 nm, taken from RTL (Project 84) to GDSII and to working C firmware. One tangible package that proves the chip's own self-test program runs end to end from C, against the exact same hex file the Verilog testbench loads.
Description
What is in the download
- Spec — FOUNDRY_DELIVERY_PACKAGE_PHC10/SPECIFICATIONS/PHC10_master_1_5nm.txt, the single input to the CRI-ONE GDSII Generator.
- GDSII v6 — PhantasmPhi_PHC10_master_1p5nm.gds, 270 bytes, verified. Die outline 1,000 × 1,000 µm · power ring 900 × 900 µm (50 µm inset) · database = 1 nm · user = 1 µm.
- C firmware (C99) — phc.h (register map · 16-opcode Light-Trigger-lineage ISA · IRQ bits · MMIO helpers), phc_sim.h/.c (reference ISA simulator mirroring phantom_soc.v + phantom_core_cpu.v), phc_selftest.c (loads the chip's hex, runs it, prints the chip's own PASS line).
- Makefile — gcc -std=c99 -Wall -Wextra -Wpedantic -Wshadow -Wconversion -O2.
- scripts/run.sh — regenerates everything from scratch and captures proofs.
- Proofs — the GDSII generation log, the GDSII verifier output, the gcc compile transcript, the gcc version, and the host self-test run (12 of 12 PASS · 112 simulated cycles).
What is NOT in the download (not hidden)
- No silicon. The GDSII is a die outline + power ring shell, not a routed layout.
- Only PHC01 is actually mapped (SKY130, 89,840 cells, 1.43 mm²). The 1.5 nm position is a reticle placeholder; other nodes are extrapolation.
- The C simulator is state-exact at each instruction boundary, not cycle-accurate against the Verilog.
- Only KELLY (deposition 5) is implemented in the phantasm engine stub; other depositions compile but return 0 until the licensee drops in the full engine from Project 83.
Where there is a will, this is where the way begins.
Project 101-c-service, cri-one.com · Christopher Gabriel Brown · 2026-10-04.
The chip
The PhantasmPhi CPU master tier at 1.5 nm (PHC10). "A CPU by design" — fetch, memory hierarchy, interrupts on the Light-Trigger-lineage ISA (32-bit words, 16 registers). The ALU is the seed Color-Math-ALU; the coprocessor is the phantasm_math_engine from Project 83. The real RTL — phantom_core_cpu.v, phantom_soc.v, phantasm_math_engine.v, color_math_alu.v — is Project 84's deliverable. This package is a materialization of two of its outputs: a GDSII outline at the top-of-ladder node, and a reference C firmware that runs its self-test.
Honest scope | The licensee sets the real die size by their SoC composition; this file is the die-outline + power-ring shell the generator writes. Not a routed layout.
32-bit words, 16 registers (r0 reads as 0). Encoding: [31:28] op | [27:24] rd | [23:20] ra | [19:16] rb | [15:0] imm. Each ALU op resolves to a seed Color-Math-ALU wavelength: Red = ADD, Yellow = MUL, Green = DIV. Vectored interrupts (vector = word 2) with EI / DI / IRET; three sources (timer, phantasm-done, external pin).
Build and run
``` cd c make make run # runs ./phc_selftest with the chip's own hex # or cd scripts && ./run.sh # regenerates GDSII, verifies, builds C, runs the self-test, writes all proofs ```
Host self-test (captured 2026-10-04)
``` Loaded 51 instructions from ../../84-phantasmphi-cpu/rtl/sw/phantom_program.hex
[PASS] program halted (did not run out of cycles) [PASS] exactly two DEBUG writes (ticks, PASS) [PASS] DEBUG #1: timer ticks > 0 (ISR fired) [PASS] DEBUG #2: PASS word (0x00000001) [PASS] MUL 6*7 landed in L1[0x100]: 42 [PASS] timer ran down to 0 [PASS] phantasm done flag held by sim [PASS] phantasm KELLY result = 32768 (0.5 Q16.16) [PASS] r3 (MUL result) == 42 [PASS] r4 (loaded back from scratchpad) == 42 [PASS] r10 (timer ticks) > 0 [PASS] r11 (phantasm done) == 1
PhantomCore self-test: 12 passed, 0 failed in 112 cycles PHANTOMCORE: ALL CHECKS PASS
build: cc (GCC) 11.5.0 20240719 (Red Hat 11.5.0-14) -std=c99 -Wall -Wextra -Wpedantic -Wshadow -Wconversion -O2 ```
That is the same PHANTOMCORE: ALL CHECKS PASS line phantom_soc_tb.v prints when run under Icarus Verilog in Project 84 — now printed by a C program built from this package.
Honest scope · what is not here
- No silicon. The GDSII is a die outline + power ring shell, not a routed layout. Routing, placement, DRC/LVS and signoff belong to the licensee and their foundry package.
- Only PHC01 is actually mapped in RTL (SKY130, 89,840 cells, 1.43 mm², official sky130_fd_sc_hd TT liberty). The 1.5 nm position above is a reticle placeholder; other nodes are extrapolation.
- The C simulator is state-exact at each instruction boundary, not cycle-accurate against the Verilog. One instruction per tick; devices tick with the core.
- Only KELLY (deposition 5) is implemented in the phantasm engine stub. Other depositions return 0 until the licensee drops in the full phantasm_math_engine.v from Project 83.
- No cryogenic parts. All CRI-ONE chips are held at 30.0 °C by Peltier nano-magnetic cooling; the functional-safety block that enforces this is 99-normal-resonance.
Relationship to the master IP license
This package is not the full PHC master IP license. The full non-exclusive IP license to the RTL and tests at every node (SKY130 → 22 · 14 · 10 · 7 · 5 · 3 · 2 · 1.8 · 1.5 nm) is the top of the PhantasmPhi calculator ladder, priced accordingly on cri-one.com/calculators.html. This package materialises two outputs of that work — a GDSII outline at the top-of-ladder node, and a working C firmware the licensee can run today.
License and jurisdiction
Perpetual, non-exclusive. US organizations only. USD only. Delivered as the zip linked above. Form of agreement: CRI-ONE Blueprint License v1 (as used for 97, 98, 99). No assignment of underlying patents or copyrights; those remain with the inventor.
Where there is a will, this is where the way begins.
Photo
Footnotes
- Product number 10342.
- Family: phantasmphi.
- Purchase: When you buy, you buy the use of that blueprint only.