74-bga_library-validate

The harness regenerates and cross-validates the complete family — footprints, pinmaps, symbols and reference board — deterministically from named profiles. It wraps project 40's own generators so geometry can be rebuilt without remembering flags, and it adds a geometry report the underlying validator does not produce: ball count, grid, pitch and pad-to-pad clearance measured from the footprint itself rather than trusted from the filename. Exit code is non-zero if any entry fails, so it is usable as an automated gate.

The centrepiece is BGA-900: a 30 × 30 grid at 1.0 mm pitch giving a 29 mm ball span inside a 32 mm body, which matches the canonical 32 mm die exactly. Neither existing package did — BGA-256 spans 15 mm (too small) and BGA-1536 spans 95 mm (roughly three times too large). BGA-900 gives project 28's 100 YFlops IC a package that actually fits its specified 32 mm square chip.

The project comprises 170 files: 38 Python scripts totalling 5,366 lines of code, 49 KiCad schematic sheets, 7 KiCad PCB files, KiCad symbol libraries, reference-design PDFs, a DRC report, a Magento product import CSV, and the assembled product bundle.

The canonical AutoPhi V19 Pinnacle baseline specifies 32 mm package width, 384–1,536 pins across SKUs. The three intermediate entries (BGA-576, BGA-900, BGA-1156) sit inside the documented range rather than inventing a new class. Pad diameters hold the 0.45 × pitch ratio the v19_default profile already uses (0.9 mm pad at 2.0 mm pitch).

Bank ratios are not invented — they are read off the two packages that are already canonical. BGA-256 and BGA-1536 both land on exactly 25.0% ground (1 ball in 4), 12.5% power (1 ball in 8), and 62.5% signal (HSIO + MGMT). That 2:1 ground-to-power split with a third of the array on power delivery is a conventional high-performance BGA scheme.

Placement follows normal BGA practice. HSIO differential pairs sit on the outer rings for short, clean escape routes. Power and ground interleave on a checkerboard through the core, giving every power ball an adjacent return path — which keeps loop inductance low. Differential pairs sit on horizontally adjacent balls so p/n stay length-matched, and a pair is never split across a row boundary. Every lane carries both directions — a transmit-only endpoint could never complete link training.

900 pins in a single KiCad symbol stands 570 mm tall. An A3 sheet is 297 mm. The symbol is physically larger than any sheet it could sit on, so no amount of wire generation can produce a workable schematic. The eight-unit symbol solves this by splitting the part into bank-grouped units capped at 120 pins each — about 152 mm tall, comfortable on A3 with room for wires and labels.

Geometry constants: body width 50.8 mm, pin length 2.54 mm, pin pitch 2.54 mm, wire length 5.08 mm. Wiring computes pin positions from the same geometry the symbol builder uses — a 0.01 mm mismatch silently produces no connection in KiCad, and symbol-library Y runs opposite to schematic Y.

The assign_pinouts.py script (219 lines) assigns signals to all three intermediate packages using the canonical ratios and BGA placement conventions.

The reference board demonstrates the BGA-900 footprint escaping to a PCIe x16 edge connector alongside four TI DS80PCI810 retimers. It is a layout reference, not a working design.

Schematic and board are verified consistent: all 1,380 pads agree on both pad name and net. Importing the netlist is a no-op. The board is safe to open and edit without KiCad offering to delete the routing.

The peripheral schematic is generated in two redriver variants sharing nine of ten sheets. Both carry the same risk-labelling philosophy: the TI variant is buildable today with published test data; the AutoPhi variant has no TI dependency and no test data.

The size_vrm.py script (107 lines) sizes the core voltage regulator from the board's own stated policy. Conversion is 12 V to 1.0 V — a 12:1 step-down. Duty cycle lands near 8.3%, where buck converters face very short on-times. Realistic efficiency at this ratio and current is 87%. Switching frequency is 600 kHz per phase; inductor ripple fraction 30%; per-phase ceiling 25 A.

112 core-power balls is generous: even at the highest scenario the per-ball current stays modest, so the package is not the limit — the VRM is. Output capacitance is set by transient response, not ripple, at these currents.

The validation harness (validate.py, 91 lines) wraps project 40's validate_bga_library.py and validates all five BGA family members in a single pass.

The geometry function measures directly from each footprint file: ball count, column/row count, pitch, X/Y span, pad diameter and pad-to-pad gap. The regeneration pipeline (regenerate.py, 94 lines) is deterministic and mirrors the governance order: footprint → pinmap template → working pinmap → seed → symbol.

A four-stage pipeline converts the reference board into a schematic-verified project.

Back-annotation schematic sheets:

apply_nets_to_board.py (127 lines) maps BGA signal names to board nets using derived mappings — GND direct, PCIe lanes to the ASIC side of AC coupling caps (the _C suffix matters: mapping to bare names would short the BGA past the caps and redrivers). add_core_rail.py (104 lines) creates the VDD_CORE net and bonds 112 core-power balls, with a Cmts.User documentation note recording the current requirement: 59 A at 58.7 W / 100 A at 100 W / 235 A at 235 W (1.0 V core).

The _tools/ directory contains 13 files (including 2 failed experiment files) for automated routing and overnight processing.

The eight-sheet carrier schematic matches the structure project 39 uses: a root .kicad_sch holding only sheet references with sheets in a sibling directory. Same file version (20260306), same generator string, same title-block shape.

Library tables inside the bundle are rewritten to use ${KIPRJMOD}/../library/ so the project resolves on any machine. Sheet references are verified to resolve inside the bundle before packaging.

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

© 2026 Christopher Gabriel Brown