59-verifyphi

The pipeline runs today as delivered software. On the day the patent was filed (2026-07-05), it caught two real chip-design bugs before either could reach the physical write channel: (1) dangling FET sources in a stub toggle-flop that would have silently emitted a dead netlist, and (2) a ripple counter clocked on the wrong edge polarity that would have produced Gray-code-adjacent output instead of binary UP count. Both bugs were fixed in the same iteration session. The rebuilt designs pass 20/20 gate assertions and 12/12 counter-cycle assertions.

VerifyPhi comprises five subsystems, each individually claimed in USPTO application 19/731,098:

The simulator models each VirtualTransistor as a gate-controlled switch. NMOS conducts drain-to-source when its gate voltage is HIGH; PMOS when its gate voltage is LOW. Node values inhabit the domain {LOW, HIGH, FLOATING, CONFLICT}. Nets named VDD are forced HIGH; GND forced LOW; testbench-driven inputs are forced to the caller’s value.

The solve routine iterates to a fixed point:

When a design source file (design.py) is executed, the gate runs five steps in strict order:

The .wpprog byte stream format (WPPROG01 wire format) comprises:

Every writable optical medium carries:

Any write-channel defect (bit flip, sector rewrite) produces a hash mismatch. Post-write medium integrity is verified independently of the writing device. On 2026-07-05, the self-authenticating payload reported 48 ok, 0 mismatch, 0 missing (48/48 clean).

Geometry for the WRITEPHI-BLANK wafer floorplan on a 120 mm BDXL-form-factor substrate:

Wafer-probe card fabrication is buyer scope; VerifyPhi delivers the geometry specification. The wafer floorplan generator (render_wafer.py) produces SVG at 120 mm scale. A companion tool (build_label_pdf.py) generates a print-ready 120 mm × 120 mm PDF label for Primera Bravo / PTPublisher disc publishing.

One command (python tools/loop.py) runs the full design cycle:

The loop refuses to emit a .wpprog for any testbench that fails. It refuses to refresh the burn payload if any IC is red. These refusals are the core guarantee: unverified designs cannot reach the write channel.

Usage:

The bundle includes 11 reference integrated circuit designs. Two are fully simulator-verified with testbenches (20/20 and 12/12 assertions), five are compile-verified, and four additional designs are shipped with compiled .wpprog and rendered die floorplans:

Each design ships with source design.py, compiled design.wpprog, rendered die floorplan design.svg, and a per-die specification (SPEC.md). Total across the original five reference ICs: 4,873 transistors, 61.5 KB of compiled write programs. WPIC-SPI-DAC-01 additionally includes a complete reference carrier board (reference_carrier/) with KiCad 10 schematic (.kicad_sch), schematic generator (gen_schematic.py), and board-level SPEC — an RP2040 host + WRITEPHI-PKG-H socket + 4 SMA outputs, 56 components, ERC-clean.

Five gates on one die, 22 FETs total, all verified 20/20 across every input combination:

VerifyPhi operates on any TargetGrade supported by the WritePhi SDK:

Grade selection is a Design attribute (target_grade=TargetGrade.M). Simulator behaviour does not change with grade — only compile-time constraint checks tighten. Designs exceeding grade limits emit ValueError.

The bundle includes the complete WritePhi SDK (version 0.1.0) and five tool scripts:

All SDK modules and tools are stdlib-only Python 3.10+. No pip dependencies required. build_label_pdf.py optionally uses svglib + reportlab for PDF generation.

Priority anchors trace to Christopher Brown’s 2017 printed publication Invent Depositions (ISBN 978-1-979767-89-7, published 2017-11-24) and the 2018–2019 buyinvent.com catalog entries:

The chain closes with the 2026-05-30 portfolio-wide framework filing (USPTO 19/693,405) and the 2026-07-05 non-provisional utility filing (USPTO 19/731,098).

VerifyPhi is buyable independently of any sibling. It operates on any design source that follows the WritePhi SDK conventions. Its output is netlist-format-neutral — VerifyPhi-verified designs can be routed to a conventional commercial foundry as a legitimate buyer path.

The VerifyPhi standalone bundle (verifyphi.crione.zip, SHA-256: a7156b...) ships 100 files across the following inventory:

Per the inventor’s ceiling — the following are the buyer’s responsibility:

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

© 2026 Christopher Gabriel Brown. All rights reserved.