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57-chip-write
This is the technical specification. The deliverable it describes is the full 57-chip-write blueprint package.
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Inventor: Christopher Gabriel Brown.
Priority date: 2017-11-24 — printed publication Invent Depositions (ISBN 978-1-979767-89-7), single-author, first shipped 2017-11-24, operative under 35 U.S.C. § 102(a)(1).
Inventor-record anchors: entries 1443–1458 of the master IP catalog.
Framework patent filing: USPTO Application No. 19/693,405, Confirmation 5107, filed 2026-05-30, 20 claims, non-provisional utility, pro se.
WritePhi-specific patent filing: USPTO Application No. 19/731,098, Confirmation 5973, Patent Center 78285110, filed 2026-07-05 — Verification-Gated Compile-and-Optical-Write Pipeline for Photolithographic Circuit Substrates.
UniPhi wireless patent: USPTO Application No. 19/717,706, Confirmation 7171, filed 2026-06-24, non-provisional utility, pro se.
Status: DESIGNED — complete engineering package at inventor’s ceiling. No prototype exists. All performance figures are design targets, not measured guarantees.
Specification revision: 0.3 (2026-07-04). SKU 2088.
Priority date: 2017-11-24 — printed publication Invent Depositions (ISBN 978-1-979767-89-7), single-author, first shipped 2017-11-24, operative under 35 U.S.C. § 102(a)(1).
Inventor-record anchors: entries 1443–1458 of the master IP catalog.
Framework patent filing: USPTO Application No. 19/693,405, Confirmation 5107, filed 2026-05-30, 20 claims, non-provisional utility, pro se.
WritePhi-specific patent filing: USPTO Application No. 19/731,098, Confirmation 5973, Patent Center 78285110, filed 2026-07-05 — Verification-Gated Compile-and-Optical-Write Pipeline for Photolithographic Circuit Substrates.
UniPhi wireless patent: USPTO Application No. 19/717,706, Confirmation 7171, filed 2026-06-24, non-provisional utility, pro se.
Status: DESIGNED — complete engineering package at inventor’s ceiling. No prototype exists. All performance figures are design targets, not measured guarantees.
Specification revision: 0.3 (2026-07-04). SKU 2088.
WritePhi is a six-SKU semiconductor-fabrication and user-in-place chip-replacement product family that brings circuit printing to the household, classroom, laboratory, and small-defence workshop. The desktop object writer inscribes circuits onto optically-written blank substrates standardised on the BDXL 100 GB / 128 GB physical envelope — the same 120 mm × 1.2 mm polycarbonate disc, the same 405 nm write laser, and the same multi-layer stack architecture the Blu-ray Disc Association finalised in 2010. The written blank is a circuit processor, not a data-storage medium.
The product family forms a complete fabrication → dicing → packaging → integration vertical: design a chip in Python or C, compile it to a write program, load a blank, press write, dice the written blank into individual dies, socket each die into a user-replaceable BGA package, and populate a multi-socket chassis or PCIe 5.0 add-in card. Die replacement takes under 30 seconds with no tools, no cleanroom, and no PCB rework.
Read section 3 for $1.90The engineering package delivered here is the consumer end of the AutoPhi architecture family — the household counterpart to Day-One Fabrication (Project 21), which ships an appliance to a commercial foundry.
Read section 4 for $1.90Plus WRITEPHI-BED — whole-disc aggregator (8 / 16 / 32 sockets), complementary to CHASSIS.
Read section 5 for $1.90The write head is a matured, commodity BDXL optical-drive assembly — 405 nm blue-violet laser diode, high-NA objective, focus + tracking servos, spindle motor, and blank load/eject mechanism. Consumer BDXL drives have shipped since 2010. WritePhi’s contribution over the stock drive: custom write firmware that retasks the drive from data-storage writing to circuit-processor writing, and a custom-chemistry blank the drive writes into.
Read section 6 for $1.90Material stack (Path 1): anti-reflection coat (100–200 nm) → protective hard-coat cover (100 µm BDXL-standard) → custom circuit-forming recording layers × N (100–400 nm per layer) with inter-layer dielectric (5–20 µm) → bond layer → polycarbonate substrate carrier (1.1 mm) → rear lacquer coat → grade + orientation machine-readable mark.
Read section 7 for $1.90Two paths: Path 1 ships a custom-chemistry blank in the BDXL envelope (the SKU). Path 2 lets early adopters repurpose stock BDXL blanks with a follow-on process step (appendix, not a SKU).
Read section 8 for $1.90The novelty step: vision alignment to WRITER-inscribed fiducials — hub fiducial, six circumferential fiducials at 60° intervals, and per-tile corner fiducials. The DICER reads marks the WRITER inscribed for exactly this purpose, then dices along circuit-tile boundaries known only to the WRITER. This converts a mature laser-cutting subsystem into a matched appliance.
Read section 9 for $1.90The productisation advantage: polycarbonate softens at 145 °C — below any solder reflow profile. The socket architecture is what the physics forces, and it is what turns every WritePhi die into a user-replaceable-in-place chip. Pop out, drop in, close cam lever. No board scrap, no rework station.
Read section 10 for $1.90Hyperthreading backplane: in-board solid-state hyperthreading (§ 1455–1456) at ≥ 25 Gbps per link, ≤ 50 ns socket-to-socket latency. Optional external copper cable (§ 1457, 100 Gbps aggregate, ≤ 500 ns) and fibre-optic (§ 1458, 200 Gbps, ≤ 2 µs at 100 m).
Read section 11 for $1.90CHASSIS-CARD-4C reference board: 91 components, 96 nets, ERC-clean KiCad 10 schematic. BOM cost ~$180 per card at 1,000 volume. Drops into any PCIe 5.0 host — Intel Z690/Z790/Z890, AMD X670E/X870E, Sapphire Rapids Xeon-W, EPYC 9004/9005, or portfolio-native AutoPhi PCIe5-256 (Project 39) / PCIe5-1536 (Project 44).
Read section 12 for $1.90Per-socket: ≤ 40 W burst. Whole-disc aggregation via hyperthreading backplane reads as one system-on-chip to the host. Invention 1453: “many optical circuit objects in order on a server bed of input ports meaning a group of objects working as system on chips.”
Read section 13 for $1.90Annual subscription marketplace of design files that compile to WritePhi write programs. Seed catalog: 1,000 IC designs from Parts Future (Project 24). Compile target: Python SDK, C SDK, or JSON-schema circuit description →
Read section 14 for $1.90.wpprog write program.Each design ships with a compilable
Read section 15 for $1.90design.py, a SPEC, and a ready-to-write .wpprog. A reference carrier board for WPIC-SPI-DAC-01 is included — RP2040 host, WRITEPHI-PKG-H socket, 4 SMA outputs, 56 components, ERC-clean KiCad 10 schematic.Beyond the five reference designs, the burn payload contains 10 additional compiled ICs: WPIC-INVERT-02, WPIC-COUNTER-01, WPIC-COUNTER-04, WPIC-ADD-4, WPIC-REG-8, WPIC-MEGA-COUNTER-ARRAY, WPIC-ADD-08, WPIC-REG-16, WPIC-MEGA-1600, and WPIC-COUNTER-08 — with rendered die SVG floorplans, compiled
Read section 16 for $1.90.wpprog byte streams, and per-IC specs.The compiler embeds a switch-level simulator inside the compile step and refuses to emit the
Read section 17 for $1.90.wpprog byte stream if any testbench assertion fails. A design that does not compute its specified truth table cannot be written to substrate. This verification-gated pipeline is the subject of USPTO Application No. 19/731,098.Writer firmware state machine: POWER_ON → BOOT_SELF_TEST → IDLE_NO_BLANK → IDLE_BLANK_LOADED → CAL_THERMAL → CAL_OPTICAL → WRITE_IN_PROGRESS → WRITE_SELF_VERIFY → WRITE_DONE. Twelve defined fault codes from
Read section 18 for $1.90E_BOOT_INTEGRITY through E_ESTOP.All schematics are generated by Python factories (
Read section 19 for $1.90gen_schematic.py) importing a shared hardware/_factory.py. All target ERC-clean in KiCad 10 (S-expression format, FMT_VERSION 20231120). Every board uses only the Python standard library — no pip dependencies.The store sells downloadable blueprints, not physical hardware. The buyer picks the specific blueprint(s) they want.
Read section 20 for $1.90The downloadable bundle
Read section 21 for $1.90writephi.crione.zip contains 70 files (254,234–319,129 bytes depending on bundle variant). SHA-256 integrity hash on file. The full project source tree spans 277 files across hardware, firmware, SDK, IC designs, patent materials, figures, bundle manifests, and documentation.This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
Read section 22 for $1.90Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
Read section 23 for $1.90© 2026 Christopher Gabriel Brown. All rights reserved.
WritePhi is a retained trademark of Christopher Gabriel Brown.
All performance figures are design targets, not measured guarantees.
Available exclusively to companies incorporated, headquartered, and primarily operating in the United States. USD only.
Communication by email and postal mail only — no phone calls, no brokers, no intermediaries.
Read section 24 for $1.90WritePhi is a retained trademark of Christopher Gabriel Brown.
All performance figures are design targets, not measured guarantees.
Available exclusively to companies incorporated, headquartered, and primarily operating in the United States. USD only.
Communication by email and postal mail only — no phone calls, no brokers, no intermediaries.