54-exitphi-accelerators

The public-facing brand is ExitPhi. Internal engineering artifacts use the WFA-* prefix. Three sibling brands: UniPhi (command-center software), ExitPhi (wireless-exit silicon), AutoPhi (foundry + canonical RTL source). Each is a separate company-shaped entity with its own IP, catalog, and revenue. No source, IP, or revenue is co-mingled.

The family comprises four reference ICs (WFA-Node, WFA-Hub, WFA-Mesh, WFA-Apex) and 22 pre-defined configurations spanning 22 nm through 3 nm process nodes, from single planar dies to 50-layer chiplet stacks. Three subsystem technologies — CoolBeam (phased-array antenna that simultaneously cools the die), PipeBeam (order-preserving linear antenna series), and QBeam (wireless quantum-to-quantum teleportation protocol) — complete the architecture. QBeam is the only wireless quantum-to-quantum fabric on the market.

Current status: step 5.5 of 12 on the engineering ladder. Architecture is shippable today as a WFA-FOUNDRY-PARTNER deliverable. Silicon-in-hand is 12–24 months away depending on configuration.

Single-stream WiFi 6E endpoint / client accelerator. Fits in USB-C dongles, handsets, wearables, IoT devices. Board form factor: 60 × 40 mm, 4-layer FR-4 PCB. Operating temperature: −20 to +70 °C.

4 × 4 MU-MIMO tri-band access-point accelerator. Board form factor: 160 × 100 mm, 4-layer FR-4 PCB. Operating temperature: 0 to +70 °C.

8 × 8 tri-radio mesh backhaul + fronthaul accelerator. Board form factor: 200 × 140 mm, 6-layer FR-4 PCB. Operating temperature: 0 to +65 °C.

8 × 8 WiFi 7 (802.11be) flagship accelerator with all 9 proprietary blocks feature-gated in. Board form factor: 240 × 160 mm, 8-layer hi-Tg FR-4 PCB. Operating temperature: 0 to +65 °C.

Each block is individually patent-pending and owned by the inventor. None are available on the open market. The WFA-Apex is the only IC in the family that carries all nine.

Reads JSON-Lines control frames and length-prefixed binary tunnel frames directly off the RX descriptor at line rate. Drops malformed frames at line rate. Surfaces parsed frame objects to the host via a 64-entry ring per direction. Wire protocol is bit-for-bit interoperable with the software uniphi.dc.fabric implementation — the rack can run a mix of WFA-accelerated and software-only members during rollout. Throughput target: >10 M frames/sec parsed at the engine.

Classifies traffic by inspecting the HELLO frame's flow tag. Four traffic classes with dedicated EDCA-equivalent priority:

Airtime Fairness (ATF) is enforced per fabric peer ID so one noisy node cannot starve the rest of the rack.

A dedicated DMA engine + QSPI controller that owns an external W25Q64JV (or similar 64 Mbit to 256 Mbit QSPI NOR). On every event-log append via host doorbell: reads prepared JSON event from host-DMA region, appends to in-flash log, issues synchronous flash write (block-erase if needed), ACKs host only when durable. End-to-end fsync target: <200 µs per event.

Two rings per direction reduce host interrupt load:

At 64-peer hub saturation, host CPU utilisation stays under 10%.

An 8 × 8 phased-array antenna whose radiating patches are simultaneously the cold-side terminals of a thermoelectric Peltier pump. RF radiates outward. Heat pumps upward. Same metal. Same layers. One structure, two jobs. CoolBeam solves antenna detuning and thermal ignition at the same physical location.

CoolBeam transforms WiFi from omnidirectional broadcast (99% wasted radiated power) into a point-to-point beamformed mesh. A rack with 1,000 WFA-equipped chips can sustain ~30,000 simultaneous beamformed peer-to-peer links without interference. Each link uses ~1% of the power for ~100 × the link budget.

CoolBeam is mandatory for Stack-25, Stack-50, and Stack-100 configurations. The three CoolBeam layers occupy the topmost chiplet layers of the stack.

A sequence-locked linear antenna array where packets enter element 1, exit element N, and arrive in the exact order they were sent — enforced by hardware at the physical layer, not by software at the transport layer. No reorder buffer. No TCP-class retransmit. No upper-layer sorting tax.

Each PipeBeam element contains five sub-blocks:

PipeBeam unlocks: quantum-circuit gate dispatch, drone-swarm command relay, database WAL streaming, sub-frame-timed live media, and deterministic real-time control. Standard WiFi MIMO does not guarantee in-order delivery at L1. PipeBeam does.

QBeam carries quantum information between ExitPhi chips — not by transmitting fragile coherent quantum states through the air, but by quantum teleportation atop the classical WFA channel. Pre-shared entanglement pairs live in the quantum-battery layers (AutoPhi trick #6); Bell measurement on chip A + 2 classical bits over CoolBeam or PipeBeam + Pauli correction on chip B = one teleported qubit. The wireless link itself carries only two classical bits per teleported qubit.

The 22 configurations span from 22 nm planar single-band through 3 nm 50-layer chiplet stacks. Each has a canonical 44-line FOUNDRY_HANDOFF.md document. Representative configs:

Stack configurations trade latency for throughput: each photonic layer adds ~1 ns of propagation. Latency-bound workloads (HFT, defence) take Stack-25; throughput-bound workloads (datacenter ingest, AI training) take Stack-50.

For reference: all published quantum systems on Earth as of 2025 combined deliver less than 0.01 Q-TOPS. Stack-50 delivers 7,500 × that on one chip.

The stacked configurations integrate all 9 AutoPhi process tricks under separate foundry sub-agreement:

CFG-04 thin RTL pin contract: 6 Verilog modules, 345 lines total, all parsing clean with balanced begin/end and parentheses. These are 40–80 line pin-contract stubs; real AutoPhi production RTL files are ~200 lines each.

QBeam RTL: 2 additional Verilog modules, 171 lines total:

Total RTL across the package: 8 Verilog modules, 516 lines.

wfa_sim.py (236 lines): functional model of the WFA backbone + 9 proprietary blocks + AutoPhi-trick interfaces. Bit-exact for crypto and event-log hash chain; cycle-approximate elsewhere. Models: EventLog (SHA-256 hash-chained), DPRBlock (lowest-RTT path picker), ULFBlock (loop-refusing firewall), CLOBlock (closed-loop envelope), CryptoCluster (SHA-256 + HMAC-SHA-256), EntanglementStore (768,000-pair capacity), QBeam (teleportation orchestrator), WFAChip (backbone assembler with deploy/replicate API).

Simulator configuration matrix (from CONFIGS dict):

Test suite (301 lines across 2 files): 14 testbenches passing in ~0.013 s.

TB1: NVRAM Burst Writer hash chain holds across 1,000 writes + detects tamper. TB2: deploy() returns sequential IDs. TB3: ULF refuses re-entering routes. TB4: CLO engages closed-loop posture, refuses deploys when engaged. TB5: DPR picks lowest-RTT peer. TB6: config target matrix — throughput ramps monotonically, planar latency improves with process shrink, stack latency grows with layers, every config beats ESP32-S3 baseline (100 ms). TB7: QBeam teleports one qubit + 1,000 qubits consuming the pool. TB8: QBeam pool exhaustion returns failure; refill restores capacity.

Four generated KiCad-10 schematic packages:

Total schematic records: 7,941. All brackets balanced.

26 FOUNDRY_HANDOFF.md documents at the canonical 44-line scale:

Each document covers: handoff summary, submission steps, required deliverables (GDSII, LEF, DEF, gate-level netlist, DRC, LVS, RTL, synthesis scripts, P&R configs, BOM, performance projections), IP valuation notes, and compliance/NDA terms.

The inventor retains ownership of the IP permanently. This is not a sale of the IP and is not an assignment. Buyers receive (1) the blueprints and (2) a license to use the IP. No tier ever includes the patent rights, the right to resell the design, or the right to claim authorship.

The trillion-tier engagement is defended by a six-method Reasoned-Basis Memo:

The warranty follows a seven-step Defects-and-Remedies Procedure: Notice (30 days) → Acknowledgement (5 business days) → Inspection (30 days) → Cure (60–90 days) → Re-trial (30 days) → Escalation (binding arbitration, AAA or JAMS) → Award (enforceable in U.S. District Court, Northern District of Georgia). Liability cap: the price paid for the deliverable. Excluded: consequential, lost-profit, indirect, punitive damages.

Full DV (Design Verification) is intentionally not in this repository. The DV corpus defines what "right" means; it is the most valuable and most NDA-encumbered tier of the deliverable. The Python reference simulator (14 passing testbenches) is the public-facing equivalent. Canonical DV falls to AutoPhi source under NDA on buyer engagement, scoped per buyer tier.

Total files on disc: 102. Total Verilog: 8 modules, 516 lines. Total Python: 6 files. Total SVG: 13 figures. Total KiCad schematic records: 7,941. Total foundry handoff documents across the portfolio: 26.

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.

© 2026 Christopher Gabriel Brown. All rights reserved.