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51-pcie8-standard - Performance

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Patent Status: Patent pending. The CS-50 substrate is covered by USPTO Non-Provisional Utility Application 19/710,460, filed 2026-06-17 (confirmation number 3169, Patent Center number 77534311), under 35 USC 111(a). Title: “Computational-Storage Apparatus with Inline AES-XTS Encryption Tweaked by Physical-Page Address and a Near-Data Compute Engine Sharing a Single Translation-Layer Command Port.” Additional family applications: USPTO 19/693,405 (CGB Framework umbrella, filed 2026-05-30, confirmation 5107, Patent Center 76837851—20 claims, names AutoPhi under Deposition 3: Voxel Resonance); USPTO 19/646,681 (Hyper Quantum Map, filed 2026-04-14, confirmation 7276); USPTO 19/540,453 (Integrated Technology Portfolio umbrella—Software for Data + Cri-One hardware family). CS-51-specific extensions (N-port FTL arbitration, N-instance ACE fabric, peer arbitration, post-quantum hybrid, confidential attestation) are scoped for a Continuation-in-Part (CIP) filing under 35 USC 120 before the CS-50 PCT window closes 2027-06-17. CIP draft: 26 claims across 6 independent claim families. All applications pending examination. Inventor: Christopher Gabriel Brown.
CS-51 is the scale-out and performance member of the AutoPhi computational-storage chip family—a single-die (or multi-chiplet) integrated circuit that fuses secured NVMe solid-state storage with programmable near-data compute, targeting hyperscale fleets and AI-pipeline preprocessing workloads. It inherits the filed CS-50 substrate (physical-page-tweaked AES-256-XTS encryption, reserved-CID single-port FTL arbitration, vendor-opcode 0xC1 doorbell invocation) and extends it with N-channel FTL parallelism, an N-instance AutoPhi Compute Engine (ACE) fabric with tree/ring reduction, a chip-to-chip peer arbitration plane, five named AI-pipeline kernels, post-quantum hybrid encryption (CRYSTALS-Kyber KEM key wrap), and TPM-class confidential attestation.
This is a soft-IP product—the same product class as ARM Cortex, Synopsys DesignWare, or Cadence Tensilica—packaged as a complete computational-storage chip design rather than a single IP block. The buyer receives engineering blueprints and foundry-handoff artifacts; they fab the silicon on their own foundry account. Patent ownership stays with the inventor.
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The complete bundle comprises 1,166 SHA-256-checksummed files: 1,128 files from the frozen CS-50 baseline plus 124 CS-51-specific extension files. Every refutable claim in the package is machine-verifiable via a single command (python verify.py—12/12 checks green).
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WonderPhi (Project 36, the universal driver in software) → CS-50 (Project 50, the driver fused with secured storage and one ACE on one die) → CS-51 (Project 51, multi-channel secured storage + N ACE instances + peer fabric on the same substrate). The WonderPhi constitution version is 1.0.0 PERMANENT, inherited from CS-50.
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The AES-XTS path is interposed between the FTL and the NAND media. Every write payload is encrypted, and every read payload is decrypted. The tweak input is the packed physical-page address (PPA)—not the host logical block address. The PPA is a 25-bit identifier: 3-bit NAND channel selector, 2-bit die selector, 12-bit block selector, and 8-bit page selector. Two 256-bit cryptographic keys (data key Key1 and tweak key Key2) are loaded at power-on and never appear on any host-readable port.
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Encryption formula per block j within a data unit:
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Decryption is the inverse. Because the tweak is the PPA, ciphertext at rest is bound to its physical location: relocating the same plaintext from PPA P1 to PPA P2 yields different ciphertext because T_base(P1) ≠ T_base(P2). The AES-256 core passes NIST Known-Answer Tests and IEEE 1619 XTS-AES-256 test vectors.
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Python simulator: ace_scaleout.py (20,297 bytes)—18/18 self-test PASS. Covers all 8 compute operations at N=1 (byte-identical to CS-50 reference) and N=4 (VOXEL, SCAN, VECTOR_DOT, TOPK, ARGMAX, EMBED_LOOKUP, SOFTMAX byte-identical; XFORM Merkle fold documented).
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CS-51 adds five named AI-pipeline kernels to CS-50's existing VOXEL, SCAN, and XFORM operations, all invoked through the same NVMe vendor opcode 0xC1:
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Simulator: peer_fabric.py (13,506 bytes)—24/24 self-test PASS. Five topologies modelled:
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Verdict: UCIe intra-package wins at every N≥2. RING is the multi-package fallback. At N=64, UCIe is 4.8× faster than HOST_MEDIATED on the reduction path.
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The canonical CS-51 package is a UCIe G2 substrate carrying multiple tile types:
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Variant SKUs:
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Benchmark script: benchmarks/ai_pipeline_demo.py (8,210 bytes). Workload: per-query retrieval over a ~0.93 GiB embedding table (1,000,000 records Ă— 1,024 bytes each); Top-K = 32; batch = 64 queries; per-query result = 512 bytes.
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Disclaimer: CS-51 numbers are design targets sourced from peer_fabric.py (24/24 self-test PASS) and published UCIe link rates. CS-51 silicon does not yet exist; numbers are not measured.
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Security budget: Effective DEK security ≥2128 even with one primitive broken (classical or post-quantum). Bulk AES-256-XTS: 2256 classical / 2128 quantum (Grover). Kyber-768 KEM: 2252 classical / 2166 quantum.
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The host invokes any ACE operation through a single NVMe doorbell write with vendor opcode 0xC1. The 256-bit submission-queue entry layout:
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A separate 128-bit parameter buffer (ace_param) accompanies the doorbell write. The NVMe engine synthesises a single completion-queue event (CQE) carrying the ACE result back to the host. Host-visible ABI is unchanged from CS-50—fan-out across N ACE instances and peer dies is transparent.
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The CS-51 handoff bundle mirrors the canonical foundry-handoff template designed for the Zettaflop-1Z accelerator (Project 23). The cri-one-pcie8-ssd-performance/handoff/ directory contains:
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Prerequisites: Python 3.10+ (stdlib only, no external dependencies); iverilog 12+ for Verilog testbenches.
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CS-51 Family SKUs:
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The package includes the autophi_engine/ Python package—a board-layout automation engine with RAG-driven design-rule enforcement. Modules:
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The engine includes 6 KiCad footprints in footprints/AutoPhi.pretty/: TPS7A4700_RGW, LP3878_NGT, DS160PR810_NJX, AutoPhi_BGA256, DS280BR810_ZBF, TPS735_DRV, TPD4E004_DRY, PCIe_x16_Edge.
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The TI references RAG knowledge base contains documentation for: DS160PR810, DS280BR810, LP3878-ADJ, MSP430F5529, TPS7A47, TPS735, TPS757, TPD4E004, SLLA335, SLLA414A, and hundreds of indexed application notes (SLYT-series, TIDU796, TIDRD10–TIDRD13, TIDUBG6, SNLU273, SSZT072, SLYP173).
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The tidrd14/ directory contains the TI reference design TIDA-00423 schematic (TIDA00423_Schematic.DSN) and the accompanying Important Notice for Reference Designs (PDF).
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The part-stock-mcp/ directory contains a parts-inventory MCP server (TypeScript/Node.js) with package.json, tsconfig.json, and Claude-settings template for integration.
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This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.
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Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.
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© 2026 Christopher Gabriel Brown. All rights reserved.
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