39-autophi-pcie5-256

Product 39 is the BGA-256 variant of the AutoPhi v19 PCIe 5.0 accelerator board in its QSFP28 optical configuration. It is a full PCIe x16 add-in card design built around a custom 256-ball BGA FPGA/ASIC package (20 × 20 mm, 1.0 mm pitch), carrying four TI DS80PCI810 8-channel linear PCIe redrivers (two banks of 8 lanes each completing a full x16 link), a DS280BR810 Gen 4 retimer, DDR3 memory (16-bit single-chip on BGA-256; 64-bit four-chip on the companion BGA-1536), a TI BQ25798 battery charger with USB-C, an MSP430F5529 management MCU, dual QSFP28 optical cages with Amphenol connectors, and a complete power tree with seven voltage rails. The design is captured in KiCad 10, generated and maintained by a 56-script Python pipeline, and ships with a custom KiCad floorplan plugin, signal-integrity reference data, and all schematic/PCB source files.

The BGA-256 package provides 48 high-speed I/O (HSIO) differential pairs and 64 management GPIOs. HSIO pairs 0–31 carry PCIe lanes (16 TX + 16 RX), pairs 32–47 carry QSFP28 optical lanes. Management GPIOs 0–23 serve I2C, SPI, JTAG, UART, and sideband signals; GPIOs 24–61 are allocated to 16-bit DDR3 (38 pins); GPIOs 62–63 provide charger interrupt and status. All 64 GPIOs are consumed at 100% utilisation on the BGA-256 variant.

Each of the 16 PCIe lanes traverses the following differential signal path (TX direction example):

BGA TX pad (APH_HSIO_PAIR_nn_P/N) → AC coupling cap (0.1 µF 0402 X5R 16 V) → DS80PCI810 INB input → DS80PCI810 OUTA output → AC coupling cap → J5 PCIe edge connector TX pad

The RX direction is the mirror: J5 RX pad → AC cap → DS80PCI810 INA → DS80PCI810 OUTB → AC cap → BGA RX pad. This creates 8 AC coupling capacitors per lane (4 sides × 2 differential lines), for a total of 128 AC coupling caps across all 16 lanes. All caps are identical: 0.1 µF 0402 X5R 16 V.

Redriver configuration (per TIDU796 compliance baseline): Pin mode (ENSMB low); VOD Level 6 (VODA1/VODB1 = 1, VODA0/VODB0 = 0 via 1 kΩ strap resistors); EQ to be derived per-channel via SI simulation (TIDU796 Gen 3 Level 1 is the reference, not a direct copy); RXDET float for auto-detect. Per-retimer decoupling: 8 capacitors (10 µF bulk + 1 µF mid + 0.1 µF fine on VIN pin 24, plus 0.1 µF on each VDD pin 9/14/36/41/51) × 4 retimers = 32 decoupling caps.

Power-good chain: wired-OR of PG_3V3 (U1), PG_5V (U22), and PG_1V5 (U52) into a single PWR_GOOD_ALL signal, pulled up to +3.3 V via 10 kΩ. On BGA-256 (no free GPIO), PWR_GOOD_ALL is read by the MSP430 MCU and forwarded to the FPGA via I2C or MCU_IRQ.

The package includes a custom KiCad 10 action plugin (autophi_floorplan_plugin/) with five tabs:

Plugin files: __init__.py, plugin.py (action-plugin entry point), floorplan_engine.py (algorithmic placement), keepouts.py (keepout zone generation), net_mappers.py (standard pinout mapping), diagnostics.py (board analysis), place_new.py (new-component placement), _test_standalone.py (standalone test harness).

The AutoPhi.pretty/ footprint library contains 21 custom KiCad footprint modules:

This package ships on a single Blu-ray disc, posted to the delivery address on your order. The archive on the disc is AES-256 encrypted; the passphrase is sent separately, by email, once the disc is despatched — so the disc alone is of no use to anyone who intercepts it.

Discs are despatched by tracked, signed-for post. Allow 5 business days for mastering and verification before despatch.