{"id":51154,"date":"2026-06-20T06:36:43","date_gmt":"2026-06-20T06:36:43","guid":{"rendered":"http:\/\/cri-one-archive-dep-1363"},"modified":"2026-06-20T06:36:43","modified_gmt":"2026-06-20T06:36:43","slug":"the-origin-of-archive-invent-deposition-1363","status":"publish","type":"post","link":"https:\/\/cri-one.com\/blog\/2026\/06\/20\/the-origin-of-archive-invent-deposition-1363\/","title":{"rendered":"The Origin of Upgrade Able Secondary Level Chips &#8212; Computing &#038; Semiconductors Series &#8212; Invent Deposition #1363"},"content":{"rendered":"<p><strong>FIRST TO MARKET<\/strong> &middot; Publicly documented in the 2017 <em>Invent Depositions<\/em> corpus &middot; Deposition #1363.<\/p>\n<blockquote>\n<p>&ldquo;upgrade able secondary level chips that co process in an onboard secondary socket that incorporate alternate processing like the central chip but in a on board or in socket form of non graphic non central but in a second level of cache and co processing formation of working computational additions far from a memory take away but a embedded solution market copyright (c) 2018 chris gabriel brown&rdquo;<br \/>&mdash; Christopher Gabriel Brown<\/p>\n<\/blockquote>\n<h3>Recognized properties<\/h3>\n<ul>\n<li><strong>Sector:<\/strong> Computing &amp; Semiconductors<\/li>\n<li><strong>Keywords:<\/strong> secondary,  level,  socket,  processing,  central,  non,  upgrade,  able,  chips,  process,  onboard,  incorporate<\/li>\n<li><strong>Key phrases:<\/strong> upgrade able secondary  &middot;  process onboard secondary  &middot;  incorporate alternate processing  &middot;  central chip  &middot;  board socket form  &middot;  second level cache  &middot;  processing formation working  &middot;  memory take away<\/li>\n<\/ul>\n<p><em>Provenance:<\/em> original 2017 catalog artwork recovered from buyinvent.com via the Internet Archive Wayback Machine; OCR text from the printed <em>Invent Depositions<\/em> book scan (Deposition #1363).<\/p>\n<hr>\n<p>&copy; Christopher Gabriel Brown &middot; Patent Pending &middot; IP retained by CRI-ONE<\/p>\n","protected":false},"excerpt":{"rendered":"<p>FIRST TO MARKET &middot; Publicly documented in the 2017 Invent Depositions corpus &middot; Deposition #1363. &ldquo;upgrade able secondary level chips that co process in an onboard secondary socket that incorporate alternate processing like the central chip but in a on board or in socket form of non graphic non central but in a second level [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[627],"tags":[],"class_list":["post-51154","post","type-post","status-publish","format-standard","hentry","category-gallery"],"_links":{"self":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51154","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/comments?post=51154"}],"version-history":[{"count":1,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51154\/revisions"}],"predecessor-version":[{"id":907263,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51154\/revisions\/907263"}],"wp:attachment":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/media?parent=51154"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/categories?post=51154"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/tags?post=51154"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}