{"id":51085,"date":"2026-06-20T06:36:43","date_gmt":"2026-06-20T06:36:43","guid":{"rendered":"http:\/\/cri-one-archive-dep-1283"},"modified":"2026-06-20T06:36:43","modified_gmt":"2026-06-20T06:36:43","slug":"the-origin-of-archive-invent-deposition-1283","status":"publish","type":"post","link":"https:\/\/cri-one.com\/blog\/2026\/06\/20\/the-origin-of-archive-invent-deposition-1283\/","title":{"rendered":"The Origin of Cube Processors Insulated Chip Levels &#8212; Computing &#038; Semiconductors Series &#8212; Invent Deposition #1283"},"content":{"rendered":"<p><strong>FIRST TO MARKET<\/strong> &middot; Publicly documented in the 2017 <em>Invent Depositions<\/em> corpus &middot; Deposition #1283.<\/p>\n<blockquote>\n<p>&ldquo;cube processors in a insulated chip levels with a coherence of any insulation method of stacking horizontal or vertical chip organization to build a larger chip also said as to make a non conductive layer with small outer inner conductive measures while operation is possible with vertical threads and vertical processing and cube processors copyright (c) 2018 chris gabriel brown patent abstract uti&rdquo;<br \/>&mdash; Christopher Gabriel Brown<\/p>\n<\/blockquote>\n<h3>Recognized properties<\/h3>\n<ul>\n<li><strong>Sector:<\/strong> Computing &amp; Semiconductors<\/li>\n<li><strong>Keywords:<\/strong> chip,  vertical,  cube,  processors,  conductive,  insulated,  levels,  coherence,  insulation,  method,  stacking,  horizontal<\/li>\n<li><strong>Key phrases:<\/strong> cube processors insulated  &middot;  insulation method stacking  &middot;  said make non  &middot;  small outer inner  &middot;  vertical threads  &middot;  vertical processing  &middot;  cube processors  &middot;  abstract utility<\/li>\n<\/ul>\n<p><em>Provenance:<\/em> original 2017 catalog artwork recovered from buyinvent.com via the Internet Archive Wayback Machine; OCR text from the printed <em>Invent Depositions<\/em> book scan (Deposition #1283).<\/p>\n<hr>\n<p>&copy; Christopher Gabriel Brown &middot; Patent Pending &middot; IP retained by CRI-ONE<\/p>\n","protected":false},"excerpt":{"rendered":"<p>FIRST TO MARKET &middot; Publicly documented in the 2017 Invent Depositions corpus &middot; Deposition #1283. &ldquo;cube processors in a insulated chip levels with a coherence of any insulation method of stacking horizontal or vertical chip organization to build a larger chip also said as to make a non conductive layer with small outer inner conductive [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[627],"tags":[],"class_list":["post-51085","post","type-post","status-publish","format-standard","hentry","category-gallery"],"_links":{"self":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51085","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/comments?post=51085"}],"version-history":[{"count":1,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51085\/revisions"}],"predecessor-version":[{"id":907332,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/posts\/51085\/revisions\/907332"}],"wp:attachment":[{"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/media?parent=51085"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/categories?post=51085"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cri-one.com\/blog\/wp-json\/wp\/v2\/tags?post=51085"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}